Lines Matching +full:0 +full:x80c00000
30 #clock-cells = <0>;
38 #clock-cells = <0>;
41 ufs_phy_rx_symbol_0_clk: ufs-phy-rx-symbol-0 {
44 #clock-cells = <0>;
50 #clock-cells = <0>;
53 ufs_phy_tx_symbol_0_clk: ufs-phy-tx-symbol-0 {
56 #clock-cells = <0>;
62 #size-cells = <0>;
64 CPU0: cpu@0 {
67 reg = <0x0 0x0>;
70 qcom,freq-domain = <&cpufreq_hw 0>;
86 reg = <0x0 0x100>;
89 qcom,freq-domain = <&cpufreq_hw 0>;
102 reg = <0x0 0x200>;
105 qcom,freq-domain = <&cpufreq_hw 0>;
118 reg = <0x0 0x300>;
121 qcom,freq-domain = <&cpufreq_hw 0>;
134 reg = <0x0 0x400>;
150 reg = <0x0 0x500>;
167 reg = <0x0 0x600>;
183 reg = <0x0 0x700>;
235 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
238 arm,psci-suspend-param = <0x40000004>;
245 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
248 arm,psci-suspend-param = <0x40000004>;
257 CLUSTER_SLEEP_0: cluster-sleep-0 {
260 arm,psci-suspend-param = <0x4100c344>;
279 reg = <0x0 0x80000000 0x0 0x0>;
292 #power-domain-cells = <0>;
298 #power-domain-cells = <0>;
304 #power-domain-cells = <0>;
310 #power-domain-cells = <0>;
316 #power-domain-cells = <0>;
322 #power-domain-cells = <0>;
328 #power-domain-cells = <0>;
334 #power-domain-cells = <0>;
340 #power-domain-cells = <0>;
389 reg = <0x0 0x80000000 0x0 0x600000>;
395 reg = <0x0 0x80700000 0x0 0x160000>;
400 reg = <0x0 0x80860000 0x0 0x20000>;
405 reg = <0x0 0x80880000 0x0 0x14000>;
410 reg = <0x0 0x80900000 0x0 0x200000>;
415 reg = <0x0 0x80b00000 0x0 0x100000>;
420 reg = <0x0 0x80c00000 0x0 0x4600000>;
425 reg = <0x0 0x85200000 0x0 0x500000>;
430 reg = <0x0 0x85700000 0x0 0x500000>;
435 reg = <0x0 0x85c00000 0x0 0x500000>;
440 reg = <0x0 0x86100000 0x0 0x2100000>;
445 reg = <0x0 0x88200000 0x0 0x1500000>;
450 reg = <0x0 0x89700000 0x0 0x1e00000>;
455 reg = <0x0 0x8b500000 0x0 0x10000>;
460 reg = <0x0 0x8b510000 0x0 0xa000>;
465 reg = <0x0 0x8b51a000 0x0 0x2000>;
470 reg = <0x0 0x8b600000 0x0 0x100000>;
475 reg = <0x0 0x8b800000 0x0 0x10000000>;
481 reg = <0x0 0x9b800000 0x0 0x280000>;
489 reg = <0x0 0xd0000000 0x0 0x800000>;
494 reg = <0x0 0xd0800000 0x0 0x76f7000>;
499 reg = <0x0 0xd7ef7000 0x0 0x9000>;
504 reg = <0x0 0xd7f00000 0x0 0x80000>;
509 reg = <0x0 0xd7f80000 0x0 0x80000>;
514 reg = <0x0 0xd8800000 0x0 0x6800000>;
534 qcom,local-pid = <0>;
558 qcom,local-pid = <0>;
582 qcom,local-pid = <0>;
617 qcom,local-pid = <0>;
632 soc: soc@0 {
635 ranges = <0 0 0 0 0x10 0>;
636 dma-ranges = <0 0 0 0 0x10 0>;
641 reg = <0x0 0x00100000 0x0 0x1f0000>;
659 <0>,
660 <0>,
661 <0>,
662 <0>,
663 <0>,
667 <0>,
668 <0>;
673 reg = <0 0x00408000 0 0x1000>;
682 reg = <0 0x00800000 0 0x60000>;
696 dma-channel-mask = <0xff>;
697 iommus = <&apps_smmu 0x5f6 0x0>;
704 reg = <0x0 0x008c0000 0x0 0x6000>;
708 iommus = <&apps_smmu 0x5e3 0x0>;
716 reg = <0 0x00880000 0 0x4000>;
720 pinctrl-0 = <&qup_i2c14_default>;
722 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
723 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
726 #size-cells = <0>;
732 reg = <0 0x00880000 0 0x4000>;
738 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
739 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
742 #size-cells = <0>;
748 reg = <0 0x00884000 0 0x4000>;
752 pinctrl-0 = <&qup_i2c15_default>;
754 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
758 #size-cells = <0>;
764 reg = <0 0x00884000 0 0x4000>;
770 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
774 #size-cells = <0>;
780 reg = <0 0x00888000 0 0x4000>;
784 pinctrl-0 = <&qup_i2c16_default>;
786 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
790 #size-cells = <0>;
796 reg = <0 0x00888000 0 0x4000>;
802 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
806 #size-cells = <0>;
812 reg = <0 0x0088c000 0 0x4000>;
816 pinctrl-0 = <&qup_i2c17_default>;
818 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
822 #size-cells = <0>;
828 reg = <0 0x0088c000 0 0x4000>;
834 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
838 #size-cells = <0>;
846 reg = <0 0x00890000 0 0x4000>;
852 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
856 #size-cells = <0>;
862 reg = <0 0x00890000 0 0x4000>;
866 pinctrl-0 = <&qup_uart18_default>;
875 reg = <0 0x00894000 0 0x4000>;
879 pinctrl-0 = <&qup_i2c19_default>;
881 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
885 #size-cells = <0>;
891 reg = <0 0x00894000 0 0x4000>;
897 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
901 #size-cells = <0>;
908 reg = <0 0x09800000 0 0x60000>;
922 dma-channel-mask = <0x7e>;
923 iommus = <&apps_smmu 0x5b6 0x0>;
930 reg = <0x0 0x009c0000 0x0 0x6000>;
934 iommus = <&apps_smmu 0x5a3 0>;
942 reg = <0 0x00980000 0 0x4000>;
946 pinctrl-0 = <&qup_i2c0_default>;
948 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
949 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
952 #size-cells = <0>;
958 reg = <0 0x00980000 0 0x4000>;
964 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
965 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
968 #size-cells = <0>;
974 reg = <0 0x00984000 0 0x4000>;
978 pinctrl-0 = <&qup_i2c1_default>;
980 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
984 #size-cells = <0>;
990 reg = <0 0x00984000 0 0x4000>;
996 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1000 #size-cells = <0>;
1006 reg = <0 0x00988000 0 0x4000>;
1010 pinctrl-0 = <&qup_i2c2_default>;
1012 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1016 #size-cells = <0>;
1022 reg = <0 0x00988000 0 0x4000>;
1028 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1032 #size-cells = <0>;
1038 reg = <0 0x0098c000 0 0x4000>;
1042 pinctrl-0 = <&qup_uart3_default_state>;
1047 #size-cells = <0>;
1055 reg = <0 0x0098c000 0 0x4000>;
1061 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1065 #size-cells = <0>;
1071 reg = <0 0x00990000 0 0x4000>;
1075 pinctrl-0 = <&qup_i2c4_default>;
1077 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1081 #size-cells = <0>;
1087 reg = <0 0x00990000 0 0x4000>;
1093 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1097 #size-cells = <0>;
1103 reg = <0 0x00994000 0 0x4000>;
1107 pinctrl-0 = <&qup_i2c5_default>;
1109 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1113 #size-cells = <0>;
1119 reg = <0 0x00994000 0 0x4000>;
1125 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1129 #size-cells = <0>;
1135 reg = <0 0x00998000 0 0x4000>;
1139 pinctrl-0 = <&qup_i2c6_default>;
1141 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1145 #size-cells = <0>;
1151 reg = <0 0x00998000 0 0x4000>;
1157 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1161 #size-cells = <0>;
1167 reg = <0 0x00998000 0 0x4000>;
1171 pinctrl-0 = <&qup_uart6_default>;
1180 reg = <0 0x0099c000 0 0x4000>;
1184 pinctrl-0 = <&qup_i2c7_default>;
1186 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1190 #size-cells = <0>;
1196 reg = <0 0x0099c000 0 0x4000>;
1202 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1206 #size-cells = <0>;
1213 reg = <0 0x00a00000 0 0x60000>;
1227 dma-channel-mask = <0xff>;
1228 iommus = <&apps_smmu 0x56 0x0>;
1235 reg = <0x0 0x00ac0000 0x0 0x6000>;
1239 iommus = <&apps_smmu 0x43 0>;
1247 reg = <0 0x00a80000 0 0x4000>;
1251 pinctrl-0 = <&qup_i2c8_default>;
1253 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1254 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1257 #size-cells = <0>;
1263 reg = <0 0x00a80000 0 0x4000>;
1269 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1270 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1273 #size-cells = <0>;
1279 reg = <0 0x00a84000 0 0x4000>;
1283 pinctrl-0 = <&qup_i2c9_default>;
1285 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1289 #size-cells = <0>;
1295 reg = <0 0x00a84000 0 0x4000>;
1301 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1305 #size-cells = <0>;
1311 reg = <0 0x00a88000 0 0x4000>;
1315 pinctrl-0 = <&qup_i2c10_default>;
1317 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1321 #size-cells = <0>;
1327 reg = <0 0x00a88000 0 0x4000>;
1333 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1337 #size-cells = <0>;
1343 reg = <0 0x00a8c000 0 0x4000>;
1347 pinctrl-0 = <&qup_i2c11_default>;
1349 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1353 #size-cells = <0>;
1359 reg = <0 0x00a8c000 0 0x4000>;
1365 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1369 #size-cells = <0>;
1375 reg = <0 0x00a90000 0 0x4000>;
1379 pinctrl-0 = <&qup_i2c12_default>;
1381 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1385 #size-cells = <0>;
1391 reg = <0 0x00a90000 0 0x4000>;
1397 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1401 #size-cells = <0>;
1407 reg = <0 0x00a94000 0 0x4000>;
1411 pinctrl-0 = <&qup_i2c13_default>;
1413 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1417 #size-cells = <0>;
1423 reg = <0 0x00a94000 0 0x4000>;
1429 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1433 #size-cells = <0>;
1440 reg = <0 0x15000000 0 0x100000>;
1545 reg = <0 0x01500000 0 0xa580>;
1552 reg = <0 0x01580000 0 0x1000>;
1559 reg = <0 0x01680000 0 0x1c200>;
1566 reg = <0 0x016e0000 0 0x1f180>;
1573 reg = <0 0x01700000 0 0x33000>;
1580 reg = <0 0x01740000 0 0x1f080>;
1587 reg = <0 0x03c40000 0 0xf080>;
1594 reg = <0 0x0a0c0000 0 0xa180>;
1602 iommus = <&apps_smmu 0x5c0 0x0>,
1603 <&apps_smmu 0x5c2 0x0>;
1604 reg = <0 0x1e40000 0 0x8000>,
1605 <0 0x1e50000 0 0x4b20>,
1606 <0 0x1e04000 0 0x23000>;
1613 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1630 qcom,smem-states = <&ipa_smp2p_out 0>,
1640 reg = <0x0 0x01f40000 0x0 0x40000>;
1646 reg = <0x0 0x04080000 0x0 0x4040>;
1649 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
1670 qcom,smem-states = <&smp2p_modem_out 0>;
1688 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
1689 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>,
1700 reg = <0 0x0c263000 0 0x1ff>, /* TM */
1701 <0 0x0c222000 0 0x8>; /* SROT */
1711 reg = <0 0x0c265000 0 0x1ff>, /* TM */
1712 <0 0x0c223000 0 0x8>; /* SROT */
1722 reg = <0 0x0c300000 0 0x400>;
1727 #clock-cells = <0>;
1732 reg = <0 0x0c3f0000 0 0x400>;
1737 reg = <0x0 0xc440000 0x0 0x1100>,
1738 <0x0 0xc600000 0x0 0x2000000>,
1739 <0x0 0xe600000 0x0 0x100000>,
1740 <0x0 0xe700000 0x0 0xa0000>,
1741 <0x0 0xc40a000 0x0 0x26000>;
1745 qcom,ee = <0>;
1746 qcom,channel = <0>;
1748 #size-cells = <0>;
1755 reg = <0 0x0f100000 0 0x300000>;
1761 gpio-ranges = <&tlmm 0 0 204>;
1918 reg = <0 0x010d3000 0 0x1000>;
1928 redistributor-stride = <0 0x20000>;
1929 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
1930 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
1938 ranges = <0 0 0 0x20000000>;
1939 reg = <0x0 0x17c20000 0x0 0x1000>;
1943 frame-number = <0>;
1946 reg = <0x17c21000 0x1000>,
1947 <0x17c22000 0x1000>;
1953 reg = <0x17c23000 0x1000>;
1960 reg = <0x17c25000 0x1000>;
1967 reg = <0x17c27000 0x1000>;
1974 reg = <0x17c29000 0x1000>;
1981 reg = <0x17c2b000 0x1000>;
1988 reg = <0x17c2d000 0x1000>;
1996 reg = <0x0 0x18200000 0x0 0x10000>,
1997 <0x0 0x18210000 0x0 0x10000>,
1998 <0x0 0x18220000 0x0 0x10000>;
1999 reg-names = "drv-0", "drv-1", "drv-2";
2003 qcom,tcs-offset = <0xd00>;
2006 <WAKE_TCS 3>, <CONTROL_TCS 0>;
2072 reg = <0 0x18591000 0 0x1000>,
2073 <0 0x18592000 0 0x1000>,
2074 <0 0x18593000 0 0x1000>;
2086 reg = <0 0x01d84000 0 0x3000>;
2097 iommus = <&apps_smmu 0xe0 0x0>;
2119 <0 0>,
2120 <0 0>,
2122 <0 0>,
2123 <0 0>,
2124 <0 0>,
2125 <0 0>;
2131 reg = <0 0x01d87000 0 0x1c4>;
2140 resets = <&ufs_mem_hc 0>;
2145 reg = <0 0x01d87400 0 0x108>,
2146 <0 0x01d87600 0 0x1e0>,
2147 <0 0x01d87c00 0 0x1dc>,
2148 <0 0x01d87800 0 0x108>,
2149 <0 0x01d87a00 0 0x1e0>;
2150 #phy-cells = <0>;
2156 reg = <0 0x05c00000 0 0x4000>;
2159 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2177 qcom,smem-states = <&smp2p_slpi_out 0>;
2198 #size-cells = <0>;
2203 iommus = <&apps_smmu 0x0541 0x0>;
2209 iommus = <&apps_smmu 0x0542 0x0>;
2215 iommus = <&apps_smmu 0x0543 0x0>;
2224 reg = <0 0x098900000 0 0x1400000>;
2227 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
2247 qcom,smem-states = <&smp2p_cdsp_out 0>;
2268 #size-cells = <0>;
2273 iommus = <&apps_smmu 0x2161 0x0400>,
2274 <&apps_smmu 0x1181 0x0420>;
2280 iommus = <&apps_smmu 0x2162 0x0400>,
2281 <&apps_smmu 0x1182 0x0420>;
2287 iommus = <&apps_smmu 0x2163 0x0400>,
2288 <&apps_smmu 0x1183 0x0420>;
2294 iommus = <&apps_smmu 0x2164 0x0400>,
2295 <&apps_smmu 0x1184 0x0420>;
2301 iommus = <&apps_smmu 0x2165 0x0400>,
2302 <&apps_smmu 0x1185 0x0420>;
2308 iommus = <&apps_smmu 0x2166 0x0400>,
2309 <&apps_smmu 0x1186 0x0420>;
2315 iommus = <&apps_smmu 0x2167 0x0400>,
2316 <&apps_smmu 0x1187 0x0420>;
2322 iommus = <&apps_smmu 0x2168 0x0400>,
2323 <&apps_smmu 0x1188 0x0420>;
2334 reg = <0 0x088e3000 0 0x400>;
2336 #phy-cells = <0>;
2347 reg = <0 0x088e4000 0 0x400>;
2349 #phy-cells = <0>;
2359 reg = <0 0x088e9000 0 0x200>,
2360 <0 0x088e8000 0 0x20>;
2376 reg = <0 0x088e9200 0 0x200>,
2377 <0 0x088e9400 0 0x200>,
2378 <0 0x088e9c00 0 0x400>,
2379 <0 0x088e9600 0 0x200>,
2380 <0 0x088e9800 0 0x200>,
2381 <0 0x088e9a00 0 0x100>;
2382 #phy-cells = <0>;
2383 #clock-cells = <0>;
2392 reg = <0 0x088eb000 0 0x200>;
2409 reg = <0 0x088ebe00 0 0x200>,
2410 <0 0x088ec000 0 0x200>,
2411 <0 0x088eb200 0 0x1100>;
2412 #phy-cells = <0>;
2413 #clock-cells = <0>;
2422 reg = <0 0x090c0000 0 0x4200>;
2429 reg = <0 0x09100000 0 0xb4000>;
2436 reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>;
2442 reg = <0 0x0a6f8800 0 0x400>;
2478 reg = <0 0x0a600000 0 0xcd00>;
2480 iommus = <&apps_smmu 0x0 0x0>;
2490 reg = <0 0x0a8f8800 0 0x400>;
2528 reg = <0 0x0a800000 0 0xcd00>;
2530 iommus = <&apps_smmu 0x20 0x0>;
2540 reg = <0 0x0af00000 0 0x10000>;
2542 <0>,
2543 <0>,
2544 <0>,
2545 <0>,
2546 <0>,
2547 <0>;
2565 reg = <0 0x17300000 0 0x100>;
2568 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2586 qcom,smem-states = <&smp2p_adsp_out 0>;
2607 #size-cells = <0>;
2612 iommus = <&apps_smmu 0x1803 0x0>;
2618 iommus = <&apps_smmu 0x1804 0x0>;
2624 iommus = <&apps_smmu 0x1805 0x0>;
3164 thermal-sensors = <&tsens0 0>;
3219 thermal-sensors = <&tsens1 0>;