Lines Matching +full:axi +full:- +full:usb2 +full:- +full:device
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
9 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/clock/qcom,sm8250-lpass-aoncc.h>
12 #include <dt-bindings/clock/qcom,sm8250-lpass-audiocc.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
16 #include <dt-bindings/interconnect/qcom,sm8250.h>
17 #include <dt-bindings/mailbox/qcom-ipcc.h>
18 #include <dt-bindings/power/qcom-rpmpd.h>
19 #include <dt-bindings/soc/qcom,apr.h>
20 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
21 #include <dt-bindings/sound/qcom,q6afe.h>
22 #include <dt-bindings/thermal/thermal.h>
23 #include <dt-bindings/clock/qcom,camcc-sm8250.h>
24 #include <dt-bindings/clock/qcom,videocc-sm8250.h>
27 interrupt-parent = <&intc>;
29 #address-cells = <2>;
30 #size-cells = <2>;
78 xo_board: xo-board {
79 compatible = "fixed-clock";
80 #clock-cells = <0>;
81 clock-frequency = <38400000>;
82 clock-output-names = "xo_board";
85 sleep_clk: sleep-clk {
86 compatible = "fixed-clock";
87 clock-frequency = <32768>;
88 #clock-cells = <0>;
93 #address-cells = <2>;
94 #size-cells = <0>;
100 enable-method = "psci";
101 capacity-dmips-mhz = <448>;
102 dynamic-power-coefficient = <205>;
103 next-level-cache = <&L2_0>;
104 power-domains = <&CPU_PD0>;
105 power-domain-names = "psci";
106 qcom,freq-domain = <&cpufreq_hw 0>;
107 operating-points-v2 = <&cpu0_opp_table>;
110 #cooling-cells = <2>;
111 L2_0: l2-cache {
113 next-level-cache = <&L3_0>;
114 L3_0: l3-cache {
124 enable-method = "psci";
125 capacity-dmips-mhz = <448>;
126 dynamic-power-coefficient = <205>;
127 next-level-cache = <&L2_100>;
128 power-domains = <&CPU_PD1>;
129 power-domain-names = "psci";
130 qcom,freq-domain = <&cpufreq_hw 0>;
131 operating-points-v2 = <&cpu0_opp_table>;
134 #cooling-cells = <2>;
135 L2_100: l2-cache {
137 next-level-cache = <&L3_0>;
145 enable-method = "psci";
146 capacity-dmips-mhz = <448>;
147 dynamic-power-coefficient = <205>;
148 next-level-cache = <&L2_200>;
149 power-domains = <&CPU_PD2>;
150 power-domain-names = "psci";
151 qcom,freq-domain = <&cpufreq_hw 0>;
152 operating-points-v2 = <&cpu0_opp_table>;
155 #cooling-cells = <2>;
156 L2_200: l2-cache {
158 next-level-cache = <&L3_0>;
166 enable-method = "psci";
167 capacity-dmips-mhz = <448>;
168 dynamic-power-coefficient = <205>;
169 next-level-cache = <&L2_300>;
170 power-domains = <&CPU_PD3>;
171 power-domain-names = "psci";
172 qcom,freq-domain = <&cpufreq_hw 0>;
173 operating-points-v2 = <&cpu0_opp_table>;
176 #cooling-cells = <2>;
177 L2_300: l2-cache {
179 next-level-cache = <&L3_0>;
187 enable-method = "psci";
188 capacity-dmips-mhz = <1024>;
189 dynamic-power-coefficient = <379>;
190 next-level-cache = <&L2_400>;
191 power-domains = <&CPU_PD4>;
192 power-domain-names = "psci";
193 qcom,freq-domain = <&cpufreq_hw 1>;
194 operating-points-v2 = <&cpu4_opp_table>;
197 #cooling-cells = <2>;
198 L2_400: l2-cache {
200 next-level-cache = <&L3_0>;
208 enable-method = "psci";
209 capacity-dmips-mhz = <1024>;
210 dynamic-power-coefficient = <379>;
211 next-level-cache = <&L2_500>;
212 power-domains = <&CPU_PD5>;
213 power-domain-names = "psci";
214 qcom,freq-domain = <&cpufreq_hw 1>;
215 operating-points-v2 = <&cpu4_opp_table>;
218 #cooling-cells = <2>;
219 L2_500: l2-cache {
221 next-level-cache = <&L3_0>;
230 enable-method = "psci";
231 capacity-dmips-mhz = <1024>;
232 dynamic-power-coefficient = <379>;
233 next-level-cache = <&L2_600>;
234 power-domains = <&CPU_PD6>;
235 power-domain-names = "psci";
236 qcom,freq-domain = <&cpufreq_hw 1>;
237 operating-points-v2 = <&cpu4_opp_table>;
240 #cooling-cells = <2>;
241 L2_600: l2-cache {
243 next-level-cache = <&L3_0>;
251 enable-method = "psci";
252 capacity-dmips-mhz = <1024>;
253 dynamic-power-coefficient = <444>;
254 next-level-cache = <&L2_700>;
255 power-domains = <&CPU_PD7>;
256 power-domain-names = "psci";
257 qcom,freq-domain = <&cpufreq_hw 2>;
258 operating-points-v2 = <&cpu7_opp_table>;
261 #cooling-cells = <2>;
262 L2_700: l2-cache {
264 next-level-cache = <&L3_0>;
268 cpu-map {
304 idle-states {
305 entry-method = "psci";
307 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
308 compatible = "arm,idle-state";
309 idle-state-name = "silver-rail-power-collapse";
310 arm,psci-suspend-param = <0x40000004>;
311 entry-latency-us = <360>;
312 exit-latency-us = <531>;
313 min-residency-us = <3934>;
314 local-timer-stop;
317 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
318 compatible = "arm,idle-state";
319 idle-state-name = "gold-rail-power-collapse";
320 arm,psci-suspend-param = <0x40000004>;
321 entry-latency-us = <702>;
322 exit-latency-us = <1061>;
323 min-residency-us = <4488>;
324 local-timer-stop;
328 domain-idle-states {
329 CLUSTER_SLEEP_0: cluster-sleep-0 {
330 compatible = "domain-idle-state";
331 idle-state-name = "cluster-llcc-off";
332 arm,psci-suspend-param = <0x4100c244>;
333 entry-latency-us = <3264>;
334 exit-latency-us = <6562>;
335 min-residency-us = <9987>;
336 local-timer-stop;
342 cpu0_opp_table: opp-table-cpu0 {
343 compatible = "operating-points-v2";
344 opp-shared;
346 cpu0_opp1: opp-300000000 {
347 opp-hz = /bits/ 64 <300000000>;
348 opp-peak-kBps = <800000 9600000>;
351 cpu0_opp2: opp-403200000 {
352 opp-hz = /bits/ 64 <403200000>;
353 opp-peak-kBps = <800000 9600000>;
356 cpu0_opp3: opp-518400000 {
357 opp-hz = /bits/ 64 <518400000>;
358 opp-peak-kBps = <800000 16588800>;
361 cpu0_opp4: opp-614400000 {
362 opp-hz = /bits/ 64 <614400000>;
363 opp-peak-kBps = <800000 16588800>;
366 cpu0_opp5: opp-691200000 {
367 opp-hz = /bits/ 64 <691200000>;
368 opp-peak-kBps = <800000 19660800>;
371 cpu0_opp6: opp-787200000 {
372 opp-hz = /bits/ 64 <787200000>;
373 opp-peak-kBps = <1804000 19660800>;
376 cpu0_opp7: opp-883200000 {
377 opp-hz = /bits/ 64 <883200000>;
378 opp-peak-kBps = <1804000 23347200>;
381 cpu0_opp8: opp-979200000 {
382 opp-hz = /bits/ 64 <979200000>;
383 opp-peak-kBps = <1804000 26419200>;
386 cpu0_opp9: opp-1075200000 {
387 opp-hz = /bits/ 64 <1075200000>;
388 opp-peak-kBps = <1804000 29491200>;
391 cpu0_opp10: opp-1171200000 {
392 opp-hz = /bits/ 64 <1171200000>;
393 opp-peak-kBps = <1804000 32563200>;
396 cpu0_opp11: opp-1248000000 {
397 opp-hz = /bits/ 64 <1248000000>;
398 opp-peak-kBps = <1804000 36249600>;
401 cpu0_opp12: opp-1344000000 {
402 opp-hz = /bits/ 64 <1344000000>;
403 opp-peak-kBps = <2188000 36249600>;
406 cpu0_opp13: opp-1420800000 {
407 opp-hz = /bits/ 64 <1420800000>;
408 opp-peak-kBps = <2188000 39321600>;
411 cpu0_opp14: opp-1516800000 {
412 opp-hz = /bits/ 64 <1516800000>;
413 opp-peak-kBps = <3072000 42393600>;
416 cpu0_opp15: opp-1612800000 {
417 opp-hz = /bits/ 64 <1612800000>;
418 opp-peak-kBps = <3072000 42393600>;
421 cpu0_opp16: opp-1708800000 {
422 opp-hz = /bits/ 64 <1708800000>;
423 opp-peak-kBps = <4068000 42393600>;
426 cpu0_opp17: opp-1804800000 {
427 opp-hz = /bits/ 64 <1804800000>;
428 opp-peak-kBps = <4068000 42393600>;
432 cpu4_opp_table: opp-table-cpu4 {
433 compatible = "operating-points-v2";
434 opp-shared;
436 cpu4_opp1: opp-710400000 {
437 opp-hz = /bits/ 64 <710400000>;
438 opp-peak-kBps = <1804000 19660800>;
441 cpu4_opp2: opp-825600000 {
442 opp-hz = /bits/ 64 <825600000>;
443 opp-peak-kBps = <2188000 23347200>;
446 cpu4_opp3: opp-940800000 {
447 opp-hz = /bits/ 64 <940800000>;
448 opp-peak-kBps = <2188000 26419200>;
451 cpu4_opp4: opp-1056000000 {
452 opp-hz = /bits/ 64 <1056000000>;
453 opp-peak-kBps = <3072000 26419200>;
456 cpu4_opp5: opp-1171200000 {
457 opp-hz = /bits/ 64 <1171200000>;
458 opp-peak-kBps = <3072000 29491200>;
461 cpu4_opp6: opp-1286400000 {
462 opp-hz = /bits/ 64 <1286400000>;
463 opp-peak-kBps = <4068000 29491200>;
466 cpu4_opp7: opp-1382400000 {
467 opp-hz = /bits/ 64 <1382400000>;
468 opp-peak-kBps = <4068000 32563200>;
471 cpu4_opp8: opp-1478400000 {
472 opp-hz = /bits/ 64 <1478400000>;
473 opp-peak-kBps = <4068000 32563200>;
476 cpu4_opp9: opp-1574400000 {
477 opp-hz = /bits/ 64 <1574400000>;
478 opp-peak-kBps = <5412000 39321600>;
481 cpu4_opp10: opp-1670400000 {
482 opp-hz = /bits/ 64 <1670400000>;
483 opp-peak-kBps = <5412000 42393600>;
486 cpu4_opp11: opp-1766400000 {
487 opp-hz = /bits/ 64 <1766400000>;
488 opp-peak-kBps = <5412000 45465600>;
491 cpu4_opp12: opp-1862400000 {
492 opp-hz = /bits/ 64 <1862400000>;
493 opp-peak-kBps = <6220000 45465600>;
496 cpu4_opp13: opp-1958400000 {
497 opp-hz = /bits/ 64 <1958400000>;
498 opp-peak-kBps = <6220000 48537600>;
501 cpu4_opp14: opp-2054400000 {
502 opp-hz = /bits/ 64 <2054400000>;
503 opp-peak-kBps = <7216000 48537600>;
506 cpu4_opp15: opp-2150400000 {
507 opp-hz = /bits/ 64 <2150400000>;
508 opp-peak-kBps = <7216000 51609600>;
511 cpu4_opp16: opp-2246400000 {
512 opp-hz = /bits/ 64 <2246400000>;
513 opp-peak-kBps = <7216000 51609600>;
516 cpu4_opp17: opp-2342400000 {
517 opp-hz = /bits/ 64 <2342400000>;
518 opp-peak-kBps = <8368000 51609600>;
521 cpu4_opp18: opp-2419200000 {
522 opp-hz = /bits/ 64 <2419200000>;
523 opp-peak-kBps = <8368000 51609600>;
527 cpu7_opp_table: opp-table-cpu7 {
528 compatible = "operating-points-v2";
529 opp-shared;
531 cpu7_opp1: opp-844800000 {
532 opp-hz = /bits/ 64 <844800000>;
533 opp-peak-kBps = <2188000 19660800>;
536 cpu7_opp2: opp-960000000 {
537 opp-hz = /bits/ 64 <960000000>;
538 opp-peak-kBps = <2188000 26419200>;
541 cpu7_opp3: opp-1075200000 {
542 opp-hz = /bits/ 64 <1075200000>;
543 opp-peak-kBps = <3072000 26419200>;
546 cpu7_opp4: opp-1190400000 {
547 opp-hz = /bits/ 64 <1190400000>;
548 opp-peak-kBps = <3072000 29491200>;
551 cpu7_opp5: opp-1305600000 {
552 opp-hz = /bits/ 64 <1305600000>;
553 opp-peak-kBps = <4068000 32563200>;
556 cpu7_opp6: opp-1401600000 {
557 opp-hz = /bits/ 64 <1401600000>;
558 opp-peak-kBps = <4068000 32563200>;
561 cpu7_opp7: opp-1516800000 {
562 opp-hz = /bits/ 64 <1516800000>;
563 opp-peak-kBps = <4068000 36249600>;
566 cpu7_opp8: opp-1632000000 {
567 opp-hz = /bits/ 64 <1632000000>;
568 opp-peak-kBps = <5412000 39321600>;
571 cpu7_opp9: opp-1747200000 {
572 opp-hz = /bits/ 64 <1708800000>;
573 opp-peak-kBps = <5412000 42393600>;
576 cpu7_opp10: opp-1862400000 {
577 opp-hz = /bits/ 64 <1862400000>;
578 opp-peak-kBps = <6220000 45465600>;
581 cpu7_opp11: opp-1977600000 {
582 opp-hz = /bits/ 64 <1977600000>;
583 opp-peak-kBps = <6220000 48537600>;
586 cpu7_opp12: opp-2073600000 {
587 opp-hz = /bits/ 64 <2073600000>;
588 opp-peak-kBps = <7216000 48537600>;
591 cpu7_opp13: opp-2169600000 {
592 opp-hz = /bits/ 64 <2169600000>;
593 opp-peak-kBps = <7216000 51609600>;
596 cpu7_opp14: opp-2265600000 {
597 opp-hz = /bits/ 64 <2265600000>;
598 opp-peak-kBps = <7216000 51609600>;
601 cpu7_opp15: opp-2361600000 {
602 opp-hz = /bits/ 64 <2361600000>;
603 opp-peak-kBps = <8368000 51609600>;
606 cpu7_opp16: opp-2457600000 {
607 opp-hz = /bits/ 64 <2457600000>;
608 opp-peak-kBps = <8368000 51609600>;
611 cpu7_opp17: opp-2553600000 {
612 opp-hz = /bits/ 64 <2553600000>;
613 opp-peak-kBps = <8368000 51609600>;
616 cpu7_opp18: opp-2649600000 {
617 opp-hz = /bits/ 64 <2649600000>;
618 opp-peak-kBps = <8368000 51609600>;
621 cpu7_opp19: opp-2745600000 {
622 opp-hz = /bits/ 64 <2745600000>;
623 opp-peak-kBps = <8368000 51609600>;
626 cpu7_opp20: opp-2841600000 {
627 opp-hz = /bits/ 64 <2841600000>;
628 opp-peak-kBps = <8368000 51609600>;
634 compatible = "qcom,scm-sm8250", "qcom,scm";
635 #reset-cells = <1>;
646 compatible = "arm,armv8-pmuv3";
651 compatible = "arm,psci-1.0";
655 #power-domain-cells = <0>;
656 power-domains = <&CLUSTER_PD>;
657 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
661 #power-domain-cells = <0>;
662 power-domains = <&CLUSTER_PD>;
663 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
667 #power-domain-cells = <0>;
668 power-domains = <&CLUSTER_PD>;
669 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
673 #power-domain-cells = <0>;
674 power-domains = <&CLUSTER_PD>;
675 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
679 #power-domain-cells = <0>;
680 power-domains = <&CLUSTER_PD>;
681 domain-idle-states = <&BIG_CPU_SLEEP_0>;
685 #power-domain-cells = <0>;
686 power-domains = <&CLUSTER_PD>;
687 domain-idle-states = <&BIG_CPU_SLEEP_0>;
691 #power-domain-cells = <0>;
692 power-domains = <&CLUSTER_PD>;
693 domain-idle-states = <&BIG_CPU_SLEEP_0>;
697 #power-domain-cells = <0>;
698 power-domains = <&CLUSTER_PD>;
699 domain-idle-states = <&BIG_CPU_SLEEP_0>;
702 CLUSTER_PD: cpu-cluster0 {
703 #power-domain-cells = <0>;
704 domain-idle-states = <&CLUSTER_SLEEP_0>;
708 qup_opp_table: opp-table-qup {
709 compatible = "operating-points-v2";
711 opp-50000000 {
712 opp-hz = /bits/ 64 <50000000>;
713 required-opps = <&rpmhpd_opp_min_svs>;
716 opp-75000000 {
717 opp-hz = /bits/ 64 <75000000>;
718 required-opps = <&rpmhpd_opp_low_svs>;
721 opp-120000000 {
722 opp-hz = /bits/ 64 <120000000>;
723 required-opps = <&rpmhpd_opp_svs>;
727 reserved-memory {
728 #address-cells = <2>;
729 #size-cells = <2>;
734 no-map;
739 no-map;
743 compatible = "qcom,cmd-db";
745 no-map;
750 no-map;
755 no-map;
760 no-map;
765 no-map;
770 no-map;
775 no-map;
780 no-map;
785 no-map;
790 no-map;
795 no-map;
800 no-map;
805 no-map;
810 no-map;
815 no-map;
820 no-map;
826 memory-region = <&smem_mem>;
830 smp2p-adsp {
833 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
839 qcom,local-pid = <0>;
840 qcom,remote-pid = <2>;
842 smp2p_adsp_out: master-kernel {
843 qcom,entry-name = "master-kernel";
844 #qcom,smem-state-cells = <1>;
847 smp2p_adsp_in: slave-kernel {
848 qcom,entry-name = "slave-kernel";
849 interrupt-controller;
850 #interrupt-cells = <2>;
854 smp2p-cdsp {
857 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
863 qcom,local-pid = <0>;
864 qcom,remote-pid = <5>;
866 smp2p_cdsp_out: master-kernel {
867 qcom,entry-name = "master-kernel";
868 #qcom,smem-state-cells = <1>;
871 smp2p_cdsp_in: slave-kernel {
872 qcom,entry-name = "slave-kernel";
873 interrupt-controller;
874 #interrupt-cells = <2>;
878 smp2p-slpi {
881 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
887 qcom,local-pid = <0>;
888 qcom,remote-pid = <3>;
890 smp2p_slpi_out: master-kernel {
891 qcom,entry-name = "master-kernel";
892 #qcom,smem-state-cells = <1>;
895 smp2p_slpi_in: slave-kernel {
896 qcom,entry-name = "slave-kernel";
897 interrupt-controller;
898 #interrupt-cells = <2>;
903 #address-cells = <2>;
904 #size-cells = <2>;
906 dma-ranges = <0 0 0 0 0x10 0>;
907 compatible = "simple-bus";
909 gcc: clock-controller@100000 {
910 compatible = "qcom,gcc-sm8250";
912 #clock-cells = <1>;
913 #reset-cells = <1>;
914 #power-domain-cells = <1>;
915 clock-names = "bi_tcxo",
924 compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
927 interrupt-controller;
928 #interrupt-cells = <3>;
929 #mbox-cells = <2>;
933 compatible = "qcom,prng-ee";
936 clock-names = "core";
939 gpi_dma2: dma-controller@800000 {
940 compatible = "qcom,sm8250-gpi-dma";
952 dma-channels = <10>;
953 dma-channel-mask = <0x3f>;
955 #dma-cells = <3>;
960 compatible = "qcom,geni-se-qup";
962 clock-names = "m-ahb", "s-ahb";
965 #address-cells = <2>;
966 #size-cells = <2>;
972 compatible = "qcom,geni-i2c";
974 clock-names = "se";
976 pinctrl-names = "default";
977 pinctrl-0 = <&qup_i2c14_default>;
981 dma-names = "tx", "rx";
982 #address-cells = <1>;
983 #size-cells = <0>;
988 compatible = "qcom,geni-spi";
990 clock-names = "se";
995 dma-names = "tx", "rx";
996 power-domains = <&rpmhpd SM8250_CX>;
997 operating-points-v2 = <&qup_opp_table>;
998 #address-cells = <1>;
999 #size-cells = <0>;
1004 compatible = "qcom,geni-i2c";
1006 clock-names = "se";
1008 pinctrl-names = "default";
1009 pinctrl-0 = <&qup_i2c15_default>;
1013 dma-names = "tx", "rx";
1014 #address-cells = <1>;
1015 #size-cells = <0>;
1020 compatible = "qcom,geni-spi";
1022 clock-names = "se";
1027 dma-names = "tx", "rx";
1028 power-domains = <&rpmhpd SM8250_CX>;
1029 operating-points-v2 = <&qup_opp_table>;
1030 #address-cells = <1>;
1031 #size-cells = <0>;
1036 compatible = "qcom,geni-i2c";
1038 clock-names = "se";
1040 pinctrl-names = "default";
1041 pinctrl-0 = <&qup_i2c16_default>;
1045 dma-names = "tx", "rx";
1046 #address-cells = <1>;
1047 #size-cells = <0>;
1052 compatible = "qcom,geni-spi";
1054 clock-names = "se";
1059 dma-names = "tx", "rx";
1060 power-domains = <&rpmhpd SM8250_CX>;
1061 operating-points-v2 = <&qup_opp_table>;
1062 #address-cells = <1>;
1063 #size-cells = <0>;
1068 compatible = "qcom,geni-i2c";
1070 clock-names = "se";
1072 pinctrl-names = "default";
1073 pinctrl-0 = <&qup_i2c17_default>;
1077 dma-names = "tx", "rx";
1078 #address-cells = <1>;
1079 #size-cells = <0>;
1084 compatible = "qcom,geni-spi";
1086 clock-names = "se";
1091 dma-names = "tx", "rx";
1092 power-domains = <&rpmhpd SM8250_CX>;
1093 operating-points-v2 = <&qup_opp_table>;
1094 #address-cells = <1>;
1095 #size-cells = <0>;
1100 compatible = "qcom,geni-uart";
1102 clock-names = "se";
1104 pinctrl-names = "default";
1105 pinctrl-0 = <&qup_uart17_default>;
1107 power-domains = <&rpmhpd SM8250_CX>;
1108 operating-points-v2 = <&qup_opp_table>;
1113 compatible = "qcom,geni-i2c";
1115 clock-names = "se";
1117 pinctrl-names = "default";
1118 pinctrl-0 = <&qup_i2c18_default>;
1122 dma-names = "tx", "rx";
1123 #address-cells = <1>;
1124 #size-cells = <0>;
1129 compatible = "qcom,geni-spi";
1131 clock-names = "se";
1136 dma-names = "tx", "rx";
1137 power-domains = <&rpmhpd SM8250_CX>;
1138 operating-points-v2 = <&qup_opp_table>;
1139 #address-cells = <1>;
1140 #size-cells = <0>;
1145 compatible = "qcom,geni-uart";
1147 clock-names = "se";
1149 pinctrl-names = "default";
1150 pinctrl-0 = <&qup_uart18_default>;
1152 power-domains = <&rpmhpd SM8250_CX>;
1153 operating-points-v2 = <&qup_opp_table>;
1158 compatible = "qcom,geni-i2c";
1160 clock-names = "se";
1162 pinctrl-names = "default";
1163 pinctrl-0 = <&qup_i2c19_default>;
1167 dma-names = "tx", "rx";
1168 #address-cells = <1>;
1169 #size-cells = <0>;
1174 compatible = "qcom,geni-spi";
1176 clock-names = "se";
1181 dma-names = "tx", "rx";
1182 power-domains = <&rpmhpd SM8250_CX>;
1183 operating-points-v2 = <&qup_opp_table>;
1184 #address-cells = <1>;
1185 #size-cells = <0>;
1190 gpi_dma0: dma-controller@900000 {
1191 compatible = "qcom,sm8250-gpi-dma";
1206 dma-channels = <15>;
1207 dma-channel-mask = <0x7ff>;
1209 #dma-cells = <3>;
1214 compatible = "qcom,geni-se-qup";
1216 clock-names = "m-ahb", "s-ahb";
1219 #address-cells = <2>;
1220 #size-cells = <2>;
1226 compatible = "qcom,geni-i2c";
1228 clock-names = "se";
1230 pinctrl-names = "default";
1231 pinctrl-0 = <&qup_i2c0_default>;
1235 dma-names = "tx", "rx";
1236 #address-cells = <1>;
1237 #size-cells = <0>;
1242 compatible = "qcom,geni-spi";
1244 clock-names = "se";
1249 dma-names = "tx", "rx";
1250 power-domains = <&rpmhpd SM8250_CX>;
1251 operating-points-v2 = <&qup_opp_table>;
1252 #address-cells = <1>;
1253 #size-cells = <0>;
1258 compatible = "qcom,geni-i2c";
1260 clock-names = "se";
1262 pinctrl-names = "default";
1263 pinctrl-0 = <&qup_i2c1_default>;
1267 dma-names = "tx", "rx";
1268 #address-cells = <1>;
1269 #size-cells = <0>;
1274 compatible = "qcom,geni-spi";
1276 clock-names = "se";
1281 dma-names = "tx", "rx";
1282 power-domains = <&rpmhpd SM8250_CX>;
1283 operating-points-v2 = <&qup_opp_table>;
1284 #address-cells = <1>;
1285 #size-cells = <0>;
1290 compatible = "qcom,geni-i2c";
1292 clock-names = "se";
1294 pinctrl-names = "default";
1295 pinctrl-0 = <&qup_i2c2_default>;
1299 dma-names = "tx", "rx";
1300 #address-cells = <1>;
1301 #size-cells = <0>;
1306 compatible = "qcom,geni-spi";
1308 clock-names = "se";
1313 dma-names = "tx", "rx";
1314 power-domains = <&rpmhpd SM8250_CX>;
1315 operating-points-v2 = <&qup_opp_table>;
1316 #address-cells = <1>;
1317 #size-cells = <0>;
1322 compatible = "qcom,geni-debug-uart";
1324 clock-names = "se";
1326 pinctrl-names = "default";
1327 pinctrl-0 = <&qup_uart2_default>;
1329 power-domains = <&rpmhpd SM8250_CX>;
1330 operating-points-v2 = <&qup_opp_table>;
1335 compatible = "qcom,geni-i2c";
1337 clock-names = "se";
1339 pinctrl-names = "default";
1340 pinctrl-0 = <&qup_i2c3_default>;
1344 dma-names = "tx", "rx";
1345 #address-cells = <1>;
1346 #size-cells = <0>;
1351 compatible = "qcom,geni-spi";
1353 clock-names = "se";
1358 dma-names = "tx", "rx";
1359 power-domains = <&rpmhpd SM8250_CX>;
1360 operating-points-v2 = <&qup_opp_table>;
1361 #address-cells = <1>;
1362 #size-cells = <0>;
1367 compatible = "qcom,geni-i2c";
1369 clock-names = "se";
1371 pinctrl-names = "default";
1372 pinctrl-0 = <&qup_i2c4_default>;
1376 dma-names = "tx", "rx";
1377 #address-cells = <1>;
1378 #size-cells = <0>;
1383 compatible = "qcom,geni-spi";
1385 clock-names = "se";
1390 dma-names = "tx", "rx";
1391 power-domains = <&rpmhpd SM8250_CX>;
1392 operating-points-v2 = <&qup_opp_table>;
1393 #address-cells = <1>;
1394 #size-cells = <0>;
1399 compatible = "qcom,geni-i2c";
1401 clock-names = "se";
1403 pinctrl-names = "default";
1404 pinctrl-0 = <&qup_i2c5_default>;
1408 dma-names = "tx", "rx";
1409 #address-cells = <1>;
1410 #size-cells = <0>;
1415 compatible = "qcom,geni-spi";
1417 clock-names = "se";
1422 dma-names = "tx", "rx";
1423 power-domains = <&rpmhpd SM8250_CX>;
1424 operating-points-v2 = <&qup_opp_table>;
1425 #address-cells = <1>;
1426 #size-cells = <0>;
1431 compatible = "qcom,geni-i2c";
1433 clock-names = "se";
1435 pinctrl-names = "default";
1436 pinctrl-0 = <&qup_i2c6_default>;
1440 dma-names = "tx", "rx";
1441 #address-cells = <1>;
1442 #size-cells = <0>;
1447 compatible = "qcom,geni-spi";
1449 clock-names = "se";
1454 dma-names = "tx", "rx";
1455 power-domains = <&rpmhpd SM8250_CX>;
1456 operating-points-v2 = <&qup_opp_table>;
1457 #address-cells = <1>;
1458 #size-cells = <0>;
1463 compatible = "qcom,geni-uart";
1465 clock-names = "se";
1467 pinctrl-names = "default";
1468 pinctrl-0 = <&qup_uart6_default>;
1470 power-domains = <&rpmhpd SM8250_CX>;
1471 operating-points-v2 = <&qup_opp_table>;
1476 compatible = "qcom,geni-i2c";
1478 clock-names = "se";
1480 pinctrl-names = "default";
1481 pinctrl-0 = <&qup_i2c7_default>;
1485 dma-names = "tx", "rx";
1486 #address-cells = <1>;
1487 #size-cells = <0>;
1492 compatible = "qcom,geni-spi";
1494 clock-names = "se";
1499 dma-names = "tx", "rx";
1500 power-domains = <&rpmhpd SM8250_CX>;
1501 operating-points-v2 = <&qup_opp_table>;
1502 #address-cells = <1>;
1503 #size-cells = <0>;
1508 gpi_dma1: dma-controller@a00000 {
1509 compatible = "qcom,sm8250-gpi-dma";
1521 dma-channels = <10>;
1522 dma-channel-mask = <0x3f>;
1524 #dma-cells = <3>;
1529 compatible = "qcom,geni-se-qup";
1531 clock-names = "m-ahb", "s-ahb";
1534 #address-cells = <2>;
1535 #size-cells = <2>;
1541 compatible = "qcom,geni-i2c";
1543 clock-names = "se";
1545 pinctrl-names = "default";
1546 pinctrl-0 = <&qup_i2c8_default>;
1550 dma-names = "tx", "rx";
1551 #address-cells = <1>;
1552 #size-cells = <0>;
1557 compatible = "qcom,geni-spi";
1559 clock-names = "se";
1564 dma-names = "tx", "rx";
1565 power-domains = <&rpmhpd SM8250_CX>;
1566 operating-points-v2 = <&qup_opp_table>;
1567 #address-cells = <1>;
1568 #size-cells = <0>;
1573 compatible = "qcom,geni-i2c";
1575 clock-names = "se";
1577 pinctrl-names = "default";
1578 pinctrl-0 = <&qup_i2c9_default>;
1582 dma-names = "tx", "rx";
1583 #address-cells = <1>;
1584 #size-cells = <0>;
1589 compatible = "qcom,geni-spi";
1591 clock-names = "se";
1596 dma-names = "tx", "rx";
1597 power-domains = <&rpmhpd SM8250_CX>;
1598 operating-points-v2 = <&qup_opp_table>;
1599 #address-cells = <1>;
1600 #size-cells = <0>;
1605 compatible = "qcom,geni-i2c";
1607 clock-names = "se";
1609 pinctrl-names = "default";
1610 pinctrl-0 = <&qup_i2c10_default>;
1614 dma-names = "tx", "rx";
1615 #address-cells = <1>;
1616 #size-cells = <0>;
1621 compatible = "qcom,geni-spi";
1623 clock-names = "se";
1628 dma-names = "tx", "rx";
1629 power-domains = <&rpmhpd SM8250_CX>;
1630 operating-points-v2 = <&qup_opp_table>;
1631 #address-cells = <1>;
1632 #size-cells = <0>;
1637 compatible = "qcom,geni-i2c";
1639 clock-names = "se";
1641 pinctrl-names = "default";
1642 pinctrl-0 = <&qup_i2c11_default>;
1646 dma-names = "tx", "rx";
1647 #address-cells = <1>;
1648 #size-cells = <0>;
1653 compatible = "qcom,geni-spi";
1655 clock-names = "se";
1660 dma-names = "tx", "rx";
1661 power-domains = <&rpmhpd SM8250_CX>;
1662 operating-points-v2 = <&qup_opp_table>;
1663 #address-cells = <1>;
1664 #size-cells = <0>;
1669 compatible = "qcom,geni-i2c";
1671 clock-names = "se";
1673 pinctrl-names = "default";
1674 pinctrl-0 = <&qup_i2c12_default>;
1678 dma-names = "tx", "rx";
1679 #address-cells = <1>;
1680 #size-cells = <0>;
1685 compatible = "qcom,geni-spi";
1687 clock-names = "se";
1692 dma-names = "tx", "rx";
1693 power-domains = <&rpmhpd SM8250_CX>;
1694 operating-points-v2 = <&qup_opp_table>;
1695 #address-cells = <1>;
1696 #size-cells = <0>;
1701 compatible = "qcom,geni-debug-uart";
1703 clock-names = "se";
1705 pinctrl-names = "default";
1706 pinctrl-0 = <&qup_uart12_default>;
1708 power-domains = <&rpmhpd SM8250_CX>;
1709 operating-points-v2 = <&qup_opp_table>;
1714 compatible = "qcom,geni-i2c";
1716 clock-names = "se";
1718 pinctrl-names = "default";
1719 pinctrl-0 = <&qup_i2c13_default>;
1723 dma-names = "tx", "rx";
1724 #address-cells = <1>;
1725 #size-cells = <0>;
1730 compatible = "qcom,geni-spi";
1732 clock-names = "se";
1737 dma-names = "tx", "rx";
1738 power-domains = <&rpmhpd SM8250_CX>;
1739 operating-points-v2 = <&qup_opp_table>;
1740 #address-cells = <1>;
1741 #size-cells = <0>;
1747 compatible = "qcom,sm8250-config-noc";
1749 #interconnect-cells = <1>;
1750 qcom,bcm-voters = <&apps_bcm_voter>;
1754 compatible = "qcom,sm8250-system-noc";
1756 #interconnect-cells = <1>;
1757 qcom,bcm-voters = <&apps_bcm_voter>;
1761 compatible = "qcom,sm8250-mc-virt";
1763 #interconnect-cells = <1>;
1764 qcom,bcm-voters = <&apps_bcm_voter>;
1768 compatible = "qcom,sm8250-aggre1-noc";
1770 #interconnect-cells = <1>;
1771 qcom,bcm-voters = <&apps_bcm_voter>;
1775 compatible = "qcom,sm8250-aggre2-noc";
1777 #interconnect-cells = <1>;
1778 qcom,bcm-voters = <&apps_bcm_voter>;
1782 compatible = "qcom,sm8250-compute-noc";
1784 #interconnect-cells = <1>;
1785 qcom,bcm-voters = <&apps_bcm_voter>;
1789 compatible = "qcom,sm8250-mmss-noc";
1791 #interconnect-cells = <1>;
1792 qcom,bcm-voters = <&apps_bcm_voter>;
1796 compatible = "qcom,pcie-sm8250";
1802 reg-names = "parf", "dbi", "elbi", "atu", "config";
1804 linux,pci-domain = <0>;
1805 bus-range = <0x00 0xff>;
1806 num-lanes = <1>;
1808 #address-cells = <3>;
1809 #size-cells = <2>;
1822 interrupt-names = "msi0", "msi1", "msi2", "msi3",
1824 #interrupt-cells = <1>;
1825 interrupt-map-mask = <0 0 0 0x7>;
1826 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1839 clock-names = "pipe",
1849 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1853 reset-names = "pci";
1855 power-domains = <&gcc PCIE_0_GDSC>;
1858 phy-names = "pciephy";
1860 perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
1861 wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
1863 pinctrl-names = "default";
1864 pinctrl-0 = <&pcie0_default_state>;
1870 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
1872 #address-cells = <2>;
1873 #size-cells = <2>;
1879 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1882 reset-names = "phy";
1884 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1885 assigned-clock-rates = <100000000>;
1895 clock-names = "pipe0";
1897 #phy-cells = <0>;
1899 #clock-cells = <0>;
1900 clock-output-names = "pcie_0_pipe_clk";
1905 compatible = "qcom,pcie-sm8250";
1911 reg-names = "parf", "dbi", "elbi", "atu", "config";
1913 linux,pci-domain = <1>;
1914 bus-range = <0x00 0xff>;
1915 num-lanes = <2>;
1917 #address-cells = <3>;
1918 #size-cells = <2>;
1924 interrupt-names = "msi";
1925 #interrupt-cells = <1>;
1926 interrupt-map-mask = <0 0 0 0x7>;
1927 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1941 clock-names = "pipe",
1951 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1952 assigned-clock-rates = <19200000>;
1955 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1959 reset-names = "pci";
1961 power-domains = <&gcc PCIE_1_GDSC>;
1964 phy-names = "pciephy";
1966 perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>;
1967 wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>;
1969 pinctrl-names = "default";
1970 pinctrl-0 = <&pcie1_default_state>;
1976 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
1978 #address-cells = <2>;
1979 #size-cells = <2>;
1985 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1988 reset-names = "phy";
1990 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1991 assigned-clock-rates = <100000000>;
2003 clock-names = "pipe0";
2005 #phy-cells = <0>;
2007 #clock-cells = <0>;
2008 clock-output-names = "pcie_1_pipe_clk";
2013 compatible = "qcom,pcie-sm8250";
2019 reg-names = "parf", "dbi", "elbi", "atu", "config";
2021 linux,pci-domain = <2>;
2022 bus-range = <0x00 0xff>;
2023 num-lanes = <2>;
2025 #address-cells = <3>;
2026 #size-cells = <2>;
2032 interrupt-names = "msi";
2033 #interrupt-cells = <1>;
2034 interrupt-map-mask = <0 0 0 0x7>;
2035 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2049 clock-names = "pipe",
2059 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2060 assigned-clock-rates = <19200000>;
2063 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2067 reset-names = "pci";
2069 power-domains = <&gcc PCIE_2_GDSC>;
2072 phy-names = "pciephy";
2074 perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
2075 wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
2077 pinctrl-names = "default";
2078 pinctrl-0 = <&pcie2_default_state>;
2084 compatible = "qcom,sm8250-qmp-modem-pcie-phy";
2086 #address-cells = <2>;
2087 #size-cells = <2>;
2093 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2096 reset-names = "phy";
2098 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2099 assigned-clock-rates = <100000000>;
2111 clock-names = "pipe0";
2113 #phy-cells = <0>;
2115 #clock-cells = <0>;
2116 clock-output-names = "pcie_2_pipe_clk";
2121 compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
2122 "jedec,ufs-2.0";
2126 phy-names = "ufsphy";
2127 lanes-per-direction = <2>;
2128 #reset-cells = <1>;
2130 reset-names = "rst";
2132 power-domains = <&gcc UFS_PHY_GDSC>;
2136 clock-names =
2154 freq-table-hz =
2168 compatible = "qcom,sm8250-qmp-ufs-phy";
2170 #address-cells = <2>;
2171 #size-cells = <2>;
2173 clock-names = "ref",
2179 reset-names = "ufsphy";
2188 #phy-cells = <0>;
2193 compatible = "qcom,sm8250-ipa-virt";
2195 #interconnect-cells = <1>;
2196 qcom,bcm-voters = <&apps_bcm_voter>;
2200 compatible = "qcom,tcsr-mutex";
2202 #hwlock-cells = <1>;
2206 compatible = "qcom,sm8250-lpass-wsa-macro";
2215 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen";
2217 #clock-cells = <0>;
2218 clock-frequency = <9600000>;
2219 clock-output-names = "mclk";
2220 #sound-dai-cells = <1>;
2222 pinctrl-names = "default";
2223 pinctrl-0 = <&wsa_swr_active>;
2226 swr0: soundwire-controller@3250000 {
2228 compatible = "qcom,soundwire-v1.5.1";
2231 clock-names = "iface";
2233 qcom,din-ports = <2>;
2234 qcom,dout-ports = <6>;
2236 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2237 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2238 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2239 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
2241 #sound-dai-cells = <1>;
2242 #address-cells = <2>;
2243 #size-cells = <0>;
2246 audiocc: clock-controller@3300000 {
2247 compatible = "qcom,sm8250-lpass-audiocc";
2249 #clock-cells = <1>;
2253 clock-names = "core", "audio", "bus";
2257 compatible = "qcom,sm8250-lpass-va-macro";
2263 clock-names = "mclk", "macro", "dcodec";
2265 #clock-cells = <0>;
2266 clock-frequency = <9600000>;
2267 clock-output-names = "fsgen";
2268 #sound-dai-cells = <1>;
2272 pinctrl-names = "default";
2273 pinctrl-0 = <&rx_swr_active>;
2274 compatible = "qcom,sm8250-lpass-rx-macro";
2284 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2286 #clock-cells = <0>;
2287 clock-frequency = <9600000>;
2288 clock-output-names = "mclk";
2289 #sound-dai-cells = <1>;
2292 swr1: soundwire-controller@3210000 {
2294 compatible = "qcom,soundwire-v1.5.1";
2298 clock-names = "iface";
2300 qcom,din-ports = <0>;
2301 qcom,dout-ports = <5>;
2303 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1F 0x1F 0x07 0x00>;
2304 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>;
2305 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>;
2306 qcom,ports-hstart = /bits/ 8 <0xFF 0x03 0xFF 0xFF 0xFF>;
2307 qcom,ports-hstop = /bits/ 8 <0xFF 0x06 0xFF 0xFF 0xFF>;
2308 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xFF 0xFF>;
2309 qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0x00 0x01 0xFF 0xFF>;
2310 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2311 qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0x00>;
2313 #sound-dai-cells = <1>;
2314 #address-cells = <2>;
2315 #size-cells = <0>;
2319 pinctrl-names = "default";
2320 pinctrl-0 = <&tx_swr_active>;
2321 compatible = "qcom,sm8250-lpass-tx-macro";
2331 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2333 #clock-cells = <0>;
2334 clock-frequency = <9600000>;
2335 clock-output-names = "mclk";
2336 #address-cells = <2>;
2337 #size-cells = <2>;
2338 #sound-dai-cells = <1>;
2342 swr2: soundwire-controller@3230000 {
2344 compatible = "qcom,soundwire-v1.5.1";
2345 interrupts-extended = <&intc GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
2346 interrupt-names = "core";
2350 clock-names = "iface";
2353 qcom,din-ports = <5>;
2354 qcom,dout-ports = <0>;
2355 qcom,ports-sinterval-low = /bits/ 8 <0xFF 0x01 0x01 0x03 0x03>;
2356 qcom,ports-offset1 = /bits/ 8 <0xFF 0x01 0x00 0x02 0x00>;
2357 qcom,ports-offset2 = /bits/ 8 <0xFF 0x00 0x00 0x00 0x00>;
2358 qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2359 qcom,ports-hstart = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2360 qcom,ports-hstop = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2361 qcom,ports-word-length = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2362 qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2363 qcom,ports-lane-control = /bits/ 8 <0xFF 0x00 0x01 0x00 0x01>;
2364 qcom,port-offset = <1>;
2365 #sound-dai-cells = <1>;
2366 #address-cells = <2>;
2367 #size-cells = <0>;
2370 aoncc: clock-controller@3380000 {
2371 compatible = "qcom,sm8250-lpass-aoncc";
2373 #clock-cells = <1>;
2377 clock-names = "core", "audio", "bus";
2381 compatible = "qcom,sm8250-lpass-lpi-pinctrl";
2384 gpio-controller;
2385 #gpio-cells = <2>;
2386 gpio-ranges = <&lpass_tlmm 0 0 14>;
2390 clock-names = "core", "audio";
2392 wsa_swr_active: wsa-swr-active-pins {
2396 drive-strength = <2>;
2397 slew-rate = <1>;
2398 bias-disable;
2404 drive-strength = <2>;
2405 slew-rate = <1>;
2406 bias-bus-hold;
2411 wsa_swr_sleep: wsa-swr-sleep-pins {
2415 drive-strength = <2>;
2416 input-enable;
2417 bias-pull-down;
2423 drive-strength = <2>;
2424 input-enable;
2425 bias-pull-down;
2430 dmic01_active: dmic01-active-pins {
2434 drive-strength = <8>;
2435 output-high;
2440 drive-strength = <8>;
2441 input-enable;
2445 dmic01_sleep: dmic01-sleep-pins {
2449 drive-strength = <2>;
2450 bias-disable;
2451 output-low;
2457 drive-strength = <2>;
2458 pull-down;
2459 input-enable;
2463 rx_swr_active: rx_swr-active-pins {
2467 drive-strength = <2>;
2468 slew-rate = <1>;
2469 bias-disable;
2475 drive-strength = <2>;
2476 slew-rate = <1>;
2477 bias-bus-hold;
2481 tx_swr_active: tx_swr-active-pins {
2485 drive-strength = <2>;
2486 slew-rate = <1>;
2487 bias-disable;
2493 drive-strength = <2>;
2494 slew-rate = <1>;
2495 bias-bus-hold;
2499 tx_swr_sleep: tx_swr-sleep-pins {
2503 drive-strength = <2>;
2504 input-enable;
2505 bias-pull-down;
2511 drive-strength = <2>;
2512 input-enable;
2513 bias-bus-hold;
2519 drive-strength = <2>;
2520 input-enable;
2521 bias-pull-down;
2527 compatible = "qcom,adreno-650.2",
2531 reg-names = "kgsl_3d0_reg_memory";
2537 operating-points-v2 = <&gpu_opp_table>;
2543 zap-shader {
2544 memory-region = <&gpu_mem>;
2548 gpu_opp_table: opp-table {
2549 compatible = "operating-points-v2";
2551 opp-670000000 {
2552 opp-hz = /bits/ 64 <670000000>;
2553 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2556 opp-587000000 {
2557 opp-hz = /bits/ 64 <587000000>;
2558 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2561 opp-525000000 {
2562 opp-hz = /bits/ 64 <525000000>;
2563 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2566 opp-490000000 {
2567 opp-hz = /bits/ 64 <490000000>;
2568 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2571 opp-441600000 {
2572 opp-hz = /bits/ 64 <441600000>;
2573 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2576 opp-400000000 {
2577 opp-hz = /bits/ 64 <400000000>;
2578 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2581 opp-305000000 {
2582 opp-hz = /bits/ 64 <305000000>;
2583 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2589 compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
2595 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
2599 interrupt-names = "hfi", "gmu";
2606 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2608 power-domains = <&gpucc GPU_CX_GDSC>,
2610 power-domain-names = "cx", "gx";
2614 operating-points-v2 = <&gmu_opp_table>;
2618 gmu_opp_table: opp-table {
2619 compatible = "operating-points-v2";
2621 opp-200000000 {
2622 opp-hz = /bits/ 64 <200000000>;
2623 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2628 gpucc: clock-controller@3d90000 {
2629 compatible = "qcom,sm8250-gpucc";
2634 clock-names = "bi_tcxo",
2637 #clock-cells = <1>;
2638 #reset-cells = <1>;
2639 #power-domain-cells = <1>;
2643 compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu", "arm,mmu-500";
2645 #iommu-cells = <2>;
2646 #global-interrupts = <2>;
2660 clock-names = "ahb", "bus", "iface";
2662 power-domains = <&gpucc GPU_CX_GDSC>;
2666 compatible = "qcom,sm8250-slpi-pas";
2669 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
2674 interrupt-names = "wdog", "fatal", "ready",
2675 "handover", "stop-ack";
2678 clock-names = "xo";
2680 power-domains = <&rpmhpd SM8250_LCX>,
2682 power-domain-names = "lcx", "lmx";
2684 memory-region = <&slpi_mem>;
2688 qcom,smem-states = <&smp2p_slpi_out 0>;
2689 qcom,smem-state-names = "stop";
2693 glink-edge {
2694 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2701 qcom,remote-pid = <3>;
2705 qcom,glink-channels = "fastrpcglink-apps-dsp";
2707 qcom,non-secure-domain;
2708 #address-cells = <1>;
2709 #size-cells = <0>;
2711 compute-cb@1 {
2712 compatible = "qcom,fastrpc-compute-cb";
2717 compute-cb@2 {
2718 compatible = "qcom,fastrpc-compute-cb";
2723 compute-cb@3 {
2724 compatible = "qcom,fastrpc-compute-cb";
2727 /* note: shared-cb = <4> in downstream */
2734 compatible = "qcom,sm8250-cdsp-pas";
2737 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
2742 interrupt-names = "wdog", "fatal", "ready",
2743 "handover", "stop-ack";
2746 clock-names = "xo";
2748 power-domains = <&rpmhpd SM8250_CX>;
2750 memory-region = <&cdsp_mem>;
2754 qcom,smem-states = <&smp2p_cdsp_out 0>;
2755 qcom,smem-state-names = "stop";
2759 glink-edge {
2760 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2767 qcom,remote-pid = <5>;
2771 qcom,glink-channels = "fastrpcglink-apps-dsp";
2773 qcom,non-secure-domain;
2774 #address-cells = <1>;
2775 #size-cells = <0>;
2777 compute-cb@1 {
2778 compatible = "qcom,fastrpc-compute-cb";
2783 compute-cb@2 {
2784 compatible = "qcom,fastrpc-compute-cb";
2789 compute-cb@3 {
2790 compatible = "qcom,fastrpc-compute-cb";
2795 compute-cb@4 {
2796 compatible = "qcom,fastrpc-compute-cb";
2801 compute-cb@5 {
2802 compatible = "qcom,fastrpc-compute-cb";
2807 compute-cb@6 {
2808 compatible = "qcom,fastrpc-compute-cb";
2813 compute-cb@7 {
2814 compatible = "qcom,fastrpc-compute-cb";
2819 compute-cb@8 {
2820 compatible = "qcom,fastrpc-compute-cb";
2834 compatible = "qcom,sm8250-usb-hs-phy",
2835 "qcom,usb-snps-hs-7nm-phy";
2838 #phy-cells = <0>;
2841 clock-names = "ref";
2847 compatible = "qcom,sm8250-usb-hs-phy",
2848 "qcom,usb-snps-hs-7nm-phy";
2851 #phy-cells = <0>;
2854 clock-names = "ref";
2860 compatible = "qcom,sm8250-qmp-usb3-dp-phy";
2865 #address-cells = <2>;
2866 #size-cells = <2>;
2872 clock-names = "aux", "ref_clk_src", "com_aux";
2876 reset-names = "phy", "common";
2878 usb_1_ssphy: usb3-phy@88e9200 {
2885 #clock-cells = <0>;
2886 #phy-cells = <0>;
2888 clock-names = "pipe0";
2889 clock-output-names = "usb3_phy_pipe_clk_src";
2892 dp_phy: dp-phy@88ea200 {
2899 #phy-cells = <0>;
2900 #clock-cells = <1>;
2902 clock-names = "pipe0";
2903 clock-output-names = "usb3_phy_pipe_clk_src";
2908 compatible = "qcom,sm8250-qmp-usb3-uni-phy";
2911 #address-cells = <2>;
2912 #size-cells = <2>;
2919 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
2923 reset-names = "phy", "common";
2929 #clock-cells = <0>;
2930 #phy-cells = <0>;
2932 clock-names = "pipe0";
2933 clock-output-names = "usb3_uni_phy_pipe_clk_src";
2938 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
2943 interrupt-names = "hc_irq", "pwr_irq";
2948 clock-names = "iface", "core", "xo";
2950 qcom,dll-config = <0x0007642c>;
2951 qcom,ddr-config = <0x80040868>;
2952 power-domains = <&rpmhpd SM8250_CX>;
2953 operating-points-v2 = <&sdhc2_opp_table>;
2957 sdhc2_opp_table: opp-table {
2958 compatible = "operating-points-v2";
2960 opp-19200000 {
2961 opp-hz = /bits/ 64 <19200000>;
2962 required-opps = <&rpmhpd_opp_min_svs>;
2965 opp-50000000 {
2966 opp-hz = /bits/ 64 <50000000>;
2967 required-opps = <&rpmhpd_opp_low_svs>;
2970 opp-100000000 {
2971 opp-hz = /bits/ 64 <100000000>;
2972 required-opps = <&rpmhpd_opp_svs>;
2975 opp-202000000 {
2976 opp-hz = /bits/ 64 <202000000>;
2977 required-opps = <&rpmhpd_opp_svs_l1>;
2983 compatible = "qcom,sm8250-dc-noc";
2985 #interconnect-cells = <1>;
2986 qcom,bcm-voters = <&apps_bcm_voter>;
2990 compatible = "qcom,sm8250-gem-noc";
2992 #interconnect-cells = <1>;
2993 qcom,bcm-voters = <&apps_bcm_voter>;
2997 compatible = "qcom,sm8250-npu-noc";
2999 #interconnect-cells = <1>;
3000 qcom,bcm-voters = <&apps_bcm_voter>;
3004 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
3007 #address-cells = <2>;
3008 #size-cells = <2>;
3010 dma-ranges;
3018 clock-names = "cfg_noc",
3025 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3027 assigned-clock-rates = <19200000>, <200000000>;
3029 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3033 interrupt-names = "hs_phy_irq",
3038 power-domains = <&gcc USB30_PRIM_GDSC>;
3050 phy-names = "usb2-phy", "usb3-phy";
3054 system-cache-controller@9200000 {
3055 compatible = "qcom,sm8250-llcc";
3057 reg-names = "llcc_base", "llcc_broadcast_base";
3061 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
3064 #address-cells = <2>;
3065 #size-cells = <2>;
3067 dma-ranges;
3075 clock-names = "cfg_noc",
3082 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3084 assigned-clock-rates = <19200000>, <200000000>;
3086 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3090 interrupt-names = "hs_phy_irq",
3095 power-domains = <&gcc USB30_SEC_GDSC>;
3107 phy-names = "usb2-phy", "usb3-phy";
3111 venus: video-codec@aa00000 {
3112 compatible = "qcom,sm8250-venus";
3115 power-domains = <&videocc MVS0C_GDSC>,
3118 power-domain-names = "venus", "vcodec0", "mx";
3119 operating-points-v2 = <&venus_opp_table>;
3124 clock-names = "iface", "core", "vcodec0_core";
3128 interconnect-names = "cpu-cfg", "video-mem";
3131 memory-region = <&video_mem>;
3135 reset-names = "bus", "core";
3139 video-decoder {
3140 compatible = "venus-decoder";
3143 video-encoder {
3144 compatible = "venus-encoder";
3147 venus_opp_table: opp-table {
3148 compatible = "operating-points-v2";
3150 opp-720000000 {
3151 opp-hz = /bits/ 64 <720000000>;
3152 required-opps = <&rpmhpd_opp_low_svs>;
3155 opp-1014000000 {
3156 opp-hz = /bits/ 64 <1014000000>;
3157 required-opps = <&rpmhpd_opp_svs>;
3160 opp-1098000000 {
3161 opp-hz = /bits/ 64 <1098000000>;
3162 required-opps = <&rpmhpd_opp_svs_l1>;
3165 opp-1332000000 {
3166 opp-hz = /bits/ 64 <1332000000>;
3167 required-opps = <&rpmhpd_opp_nom>;
3172 videocc: clock-controller@abf0000 {
3173 compatible = "qcom,sm8250-videocc";
3178 power-domains = <&rpmhpd SM8250_MMCX>;
3179 required-opps = <&rpmhpd_opp_low_svs>;
3180 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao";
3181 #clock-cells = <1>;
3182 #reset-cells = <1>;
3183 #power-domain-cells = <1>;
3187 compatible = "qcom,sm8250-cci";
3188 #address-cells = <1>;
3189 #size-cells = <0>;
3193 power-domains = <&camcc TITAN_TOP_GDSC>;
3200 clock-names = "camnoc_axi",
3206 pinctrl-0 = <&cci0_default>;
3207 pinctrl-1 = <&cci0_sleep>;
3208 pinctrl-names = "default", "sleep";
3212 cci0_i2c0: i2c-bus@0 {
3214 clock-frequency = <1000000>;
3215 #address-cells = <1>;
3216 #size-cells = <0>;
3219 cci0_i2c1: i2c-bus@1 {
3221 clock-frequency = <1000000>;
3222 #address-cells = <1>;
3223 #size-cells = <0>;
3228 compatible = "qcom,sm8250-cci";
3229 #address-cells = <1>;
3230 #size-cells = <0>;
3234 power-domains = <&camcc TITAN_TOP_GDSC>;
3241 clock-names = "camnoc_axi",
3247 pinctrl-0 = <&cci1_default>;
3248 pinctrl-1 = <&cci1_sleep>;
3249 pinctrl-names = "default", "sleep";
3253 cci1_i2c0: i2c-bus@0 {
3255 clock-frequency = <1000000>;
3256 #address-cells = <1>;
3257 #size-cells = <0>;
3260 cci1_i2c1: i2c-bus@1 {
3262 clock-frequency = <1000000>;
3263 #address-cells = <1>;
3264 #size-cells = <0>;
3269 compatible = "qcom,sm8250-camss";
3282 reg-names = "csiphy0",
3307 interrupt-names = "csiphy0",
3322 power-domains = <&camcc IFE_0_GDSC>,
3364 clock-names = "cam_ahb_clk",
3415 interconnect-names = "cam_ahb",
3421 camcc: clock-controller@ad00000 {
3422 compatible = "qcom,sm8250-camcc";
3428 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
3429 power-domains = <&rpmhpd SM8250_MMCX>;
3430 required-opps = <&rpmhpd_opp_low_svs>;
3432 #clock-cells = <1>;
3433 #reset-cells = <1>;
3434 #power-domain-cells = <1>;
3438 compatible = "qcom,sm8250-mdss";
3440 reg-names = "mdss";
3444 interconnect-names = "mdp0-mem", "mdp1-mem";
3446 power-domains = <&dispcc MDSS_GDSC>;
3452 clock-names = "iface", "bus", "nrt_bus", "core";
3455 interrupt-controller;
3456 #interrupt-cells = <1>;
3462 #address-cells = <2>;
3463 #size-cells = <2>;
3466 mdss_mdp: display-controller@ae01000 {
3467 compatible = "qcom,sm8250-dpu";
3470 reg-names = "mdp", "vbif";
3476 clock-names = "iface", "bus", "core", "vsync";
3478 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3479 assigned-clock-rates = <19200000>;
3481 operating-points-v2 = <&mdp_opp_table>;
3482 power-domains = <&rpmhpd SM8250_MMCX>;
3484 interrupt-parent = <&mdss>;
3488 #address-cells = <1>;
3489 #size-cells = <0>;
3494 remote-endpoint = <&dsi0_in>;
3501 remote-endpoint = <&dsi1_in>;
3506 mdp_opp_table: opp-table {
3507 compatible = "operating-points-v2";
3509 opp-200000000 {
3510 opp-hz = /bits/ 64 <200000000>;
3511 required-opps = <&rpmhpd_opp_low_svs>;
3514 opp-300000000 {
3515 opp-hz = /bits/ 64 <300000000>;
3516 required-opps = <&rpmhpd_opp_svs>;
3519 opp-345000000 {
3520 opp-hz = /bits/ 64 <345000000>;
3521 required-opps = <&rpmhpd_opp_svs_l1>;
3524 opp-460000000 {
3525 opp-hz = /bits/ 64 <460000000>;
3526 required-opps = <&rpmhpd_opp_nom>;
3532 compatible = "qcom,mdss-dsi-ctrl";
3534 reg-names = "dsi_ctrl";
3536 interrupt-parent = <&mdss>;
3545 clock-names = "byte",
3552 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3553 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
3555 operating-points-v2 = <&dsi_opp_table>;
3556 power-domains = <&rpmhpd SM8250_MMCX>;
3559 phy-names = "dsi";
3563 #address-cells = <1>;
3564 #size-cells = <0>;
3567 #address-cells = <1>;
3568 #size-cells = <0>;
3573 remote-endpoint = <&dpu_intf1_out>;
3584 dsi_opp_table: opp-table {
3585 compatible = "operating-points-v2";
3587 opp-187500000 {
3588 opp-hz = /bits/ 64 <187500000>;
3589 required-opps = <&rpmhpd_opp_low_svs>;
3592 opp-300000000 {
3593 opp-hz = /bits/ 64 <300000000>;
3594 required-opps = <&rpmhpd_opp_svs>;
3597 opp-358000000 {
3598 opp-hz = /bits/ 64 <358000000>;
3599 required-opps = <&rpmhpd_opp_svs_l1>;
3604 dsi0_phy: dsi-phy@ae94400 {
3605 compatible = "qcom,dsi-phy-7nm";
3609 reg-names = "dsi_phy",
3613 #clock-cells = <1>;
3614 #phy-cells = <0>;
3618 clock-names = "iface", "ref";
3624 compatible = "qcom,mdss-dsi-ctrl";
3626 reg-names = "dsi_ctrl";
3628 interrupt-parent = <&mdss>;
3637 clock-names = "byte",
3644 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
3645 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
3647 operating-points-v2 = <&dsi_opp_table>;
3648 power-domains = <&rpmhpd SM8250_MMCX>;
3651 phy-names = "dsi";
3655 #address-cells = <1>;
3656 #size-cells = <0>;
3659 #address-cells = <1>;
3660 #size-cells = <0>;
3665 remote-endpoint = <&dpu_intf2_out>;
3677 dsi1_phy: dsi-phy@ae96400 {
3678 compatible = "qcom,dsi-phy-7nm";
3682 reg-names = "dsi_phy",
3686 #clock-cells = <1>;
3687 #phy-cells = <0>;
3691 clock-names = "iface", "ref";
3697 dispcc: clock-controller@af00000 {
3698 compatible = "qcom,sm8250-dispcc";
3700 power-domains = <&rpmhpd SM8250_MMCX>;
3701 required-opps = <&rpmhpd_opp_low_svs>;
3709 clock-names = "bi_tcxo",
3716 #clock-cells = <1>;
3717 #reset-cells = <1>;
3718 #power-domain-cells = <1>;
3721 pdc: interrupt-controller@b220000 {
3722 compatible = "qcom,sm8250-pdc", "qcom,pdc";
3724 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
3726 #interrupt-cells = <2>;
3727 interrupt-parent = <&intc>;
3728 interrupt-controller;
3731 tsens0: thermal-sensor@c263000 {
3732 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
3738 interrupt-names = "uplow", "critical";
3739 #thermal-sensor-cells = <1>;
3742 tsens1: thermal-sensor@c265000 {
3743 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
3749 interrupt-names = "uplow", "critical";
3750 #thermal-sensor-cells = <1>;
3753 aoss_qmp: power-controller@c300000 {
3754 compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp";
3756 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
3762 #clock-cells = <0>;
3766 compatible = "qcom,rpmh-stats";
3771 compatible = "qcom,spmi-pmic-arb";
3777 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3778 interrupt-names = "periph_irq";
3779 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3782 #address-cells = <2>;
3783 #size-cells = <0>;
3784 interrupt-controller;
3785 #interrupt-cells = <4>;
3789 compatible = "qcom,sm8250-pinctrl";
3793 reg-names = "west", "south", "north";
3795 gpio-controller;
3796 #gpio-cells = <2>;
3797 interrupt-controller;
3798 #interrupt-cells = <2>;
3799 gpio-ranges = <&tlmm 0 0 181>;
3800 wakeup-parent = <&pdc>;
3802 cci0_default: cci0-default {
3803 cci0_i2c0_default: cci0-i2c0-default {
3808 bias-pull-up;
3809 drive-strength = <2>; /* 2 mA */
3812 cci0_i2c1_default: cci0-i2c1-default {
3817 bias-pull-up;
3818 drive-strength = <2>; /* 2 mA */
3822 cci0_sleep: cci0-sleep {
3823 cci0_i2c0_sleep: cci0-i2c0-sleep {
3828 drive-strength = <2>; /* 2 mA */
3829 bias-pull-down;
3832 cci0_i2c1_sleep: cci0-i2c1-sleep {
3837 drive-strength = <2>; /* 2 mA */
3838 bias-pull-down;
3842 cci1_default: cci1-default {
3843 cci1_i2c0_default: cci1-i2c0-default {
3848 bias-pull-up;
3849 drive-strength = <2>; /* 2 mA */
3852 cci1_i2c1_default: cci1-i2c1-default {
3857 bias-pull-up;
3858 drive-strength = <2>; /* 2 mA */
3862 cci1_sleep: cci1-sleep {
3863 cci1_i2c0_sleep: cci1-i2c0-sleep {
3868 bias-pull-down;
3869 drive-strength = <2>; /* 2 mA */
3872 cci1_i2c1_sleep: cci1-i2c1-sleep {
3877 bias-pull-down;
3878 drive-strength = <2>; /* 2 mA */
3882 pri_mi2s_active: pri-mi2s-active {
3886 drive-strength = <8>;
3887 bias-disable;
3893 drive-strength = <8>;
3894 output-high;
3900 drive-strength = <8>;
3901 bias-disable;
3902 output-high;
3908 drive-strength = <8>;
3909 output-high;
3913 qup_i2c0_default: qup-i2c0-default {
3921 drive-strength = <2>;
3922 bias-disable;
3926 qup_i2c1_default: qup-i2c1-default {
3934 drive-strength = <2>;
3935 bias-disable;
3939 qup_i2c2_default: qup-i2c2-default {
3947 drive-strength = <2>;
3948 bias-disable;
3952 qup_i2c3_default: qup-i2c3-default {
3960 drive-strength = <2>;
3961 bias-disable;
3965 qup_i2c4_default: qup-i2c4-default {
3973 drive-strength = <2>;
3974 bias-disable;
3978 qup_i2c5_default: qup-i2c5-default {
3986 drive-strength = <2>;
3987 bias-disable;
3991 qup_i2c6_default: qup-i2c6-default {
3999 drive-strength = <2>;
4000 bias-disable;
4004 qup_i2c7_default: qup-i2c7-default {
4012 drive-strength = <2>;
4013 bias-disable;
4017 qup_i2c8_default: qup-i2c8-default {
4025 drive-strength = <2>;
4026 bias-disable;
4030 qup_i2c9_default: qup-i2c9-default {
4038 drive-strength = <2>;
4039 bias-disable;
4043 qup_i2c10_default: qup-i2c10-default {
4051 drive-strength = <2>;
4052 bias-disable;
4056 qup_i2c11_default: qup-i2c11-default {
4064 drive-strength = <2>;
4065 bias-disable;
4069 qup_i2c12_default: qup-i2c12-default {
4077 drive-strength = <2>;
4078 bias-disable;
4082 qup_i2c13_default: qup-i2c13-default {
4090 drive-strength = <2>;
4091 bias-disable;
4095 qup_i2c14_default: qup-i2c14-default {
4103 drive-strength = <2>;
4104 bias-disable;
4108 qup_i2c15_default: qup-i2c15-default {
4116 drive-strength = <2>;
4117 bias-disable;
4121 qup_i2c16_default: qup-i2c16-default {
4129 drive-strength = <2>;
4130 bias-disable;
4134 qup_i2c17_default: qup-i2c17-default {
4142 drive-strength = <2>;
4143 bias-disable;
4147 qup_i2c18_default: qup-i2c18-default {
4155 drive-strength = <2>;
4156 bias-disable;
4160 qup_i2c19_default: qup-i2c19-default {
4168 drive-strength = <2>;
4169 bias-disable;
4173 qup_spi0_cs: qup-spi0-cs {
4178 qup_spi0_cs_gpio: qup-spi0-cs-gpio {
4183 qup_spi0_data_clk: qup-spi0-data-clk {
4189 qup_spi1_cs: qup-spi1-cs {
4194 qup_spi1_cs_gpio: qup-spi1-cs-gpio {
4199 qup_spi1_data_clk: qup-spi1-data-clk {
4205 qup_spi2_cs: qup-spi2-cs {
4210 qup_spi2_cs_gpio: qup-spi2-cs-gpio {
4215 qup_spi2_data_clk: qup-spi2-data-clk {
4221 qup_spi3_cs: qup-spi3-cs {
4226 qup_spi3_cs_gpio: qup-spi3-cs-gpio {
4231 qup_spi3_data_clk: qup-spi3-data-clk {
4237 qup_spi4_cs: qup-spi4-cs {
4242 qup_spi4_cs_gpio: qup-spi4-cs-gpio {
4247 qup_spi4_data_clk: qup-spi4-data-clk {
4253 qup_spi5_cs: qup-spi5-cs {
4258 qup_spi5_cs_gpio: qup-spi5-cs-gpio {
4263 qup_spi5_data_clk: qup-spi5-data-clk {
4269 qup_spi6_cs: qup-spi6-cs {
4274 qup_spi6_cs_gpio: qup-spi6-cs-gpio {
4279 qup_spi6_data_clk: qup-spi6-data-clk {
4285 qup_spi7_cs: qup-spi7-cs {
4290 qup_spi7_cs_gpio: qup-spi7-cs-gpio {
4295 qup_spi7_data_clk: qup-spi7-data-clk {
4301 qup_spi8_cs: qup-spi8-cs {
4306 qup_spi8_cs_gpio: qup-spi8-cs-gpio {
4311 qup_spi8_data_clk: qup-spi8-data-clk {
4317 qup_spi9_cs: qup-spi9-cs {
4322 qup_spi9_cs_gpio: qup-spi9-cs-gpio {
4327 qup_spi9_data_clk: qup-spi9-data-clk {
4333 qup_spi10_cs: qup-spi10-cs {
4338 qup_spi10_cs_gpio: qup-spi10-cs-gpio {
4343 qup_spi10_data_clk: qup-spi10-data-clk {
4349 qup_spi11_cs: qup-spi11-cs {
4354 qup_spi11_cs_gpio: qup-spi11-cs-gpio {
4359 qup_spi11_data_clk: qup-spi11-data-clk {
4365 qup_spi12_cs: qup-spi12-cs {
4370 qup_spi12_cs_gpio: qup-spi12-cs-gpio {
4375 qup_spi12_data_clk: qup-spi12-data-clk {
4381 qup_spi13_cs: qup-spi13-cs {
4386 qup_spi13_cs_gpio: qup-spi13-cs-gpio {
4391 qup_spi13_data_clk: qup-spi13-data-clk {
4397 qup_spi14_cs: qup-spi14-cs {
4402 qup_spi14_cs_gpio: qup-spi14-cs-gpio {
4407 qup_spi14_data_clk: qup-spi14-data-clk {
4413 qup_spi15_cs: qup-spi15-cs {
4418 qup_spi15_cs_gpio: qup-spi15-cs-gpio {
4423 qup_spi15_data_clk: qup-spi15-data-clk {
4429 qup_spi16_cs: qup-spi16-cs {
4434 qup_spi16_cs_gpio: qup-spi16-cs-gpio {
4439 qup_spi16_data_clk: qup-spi16-data-clk {
4445 qup_spi17_cs: qup-spi17-cs {
4450 qup_spi17_cs_gpio: qup-spi17-cs-gpio {
4455 qup_spi17_data_clk: qup-spi17-data-clk {
4461 qup_spi18_cs: qup-spi18-cs {
4466 qup_spi18_cs_gpio: qup-spi18-cs-gpio {
4471 qup_spi18_data_clk: qup-spi18-data-clk {
4477 qup_spi19_cs: qup-spi19-cs {
4482 qup_spi19_cs_gpio: qup-spi19-cs-gpio {
4487 qup_spi19_data_clk: qup-spi19-data-clk {
4493 qup_uart2_default: qup-uart2-default {
4500 qup_uart6_default: qup-uart6-default {
4508 qup_uart12_default: qup-uart12-default {
4515 qup_uart17_default: qup-uart17-default {
4523 qup_uart18_default: qup-uart18-default {
4530 tert_mi2s_active: tert-mi2s-active {
4534 drive-strength = <8>;
4535 bias-disable;
4541 drive-strength = <8>;
4542 bias-disable;
4543 output-high;
4549 drive-strength = <8>;
4550 output-high;
4554 sdc2_sleep_state: sdc2-sleep {
4557 drive-strength = <2>;
4558 bias-disable;
4563 drive-strength = <2>;
4564 bias-pull-up;
4569 drive-strength = <2>;
4570 bias-pull-up;
4574 pcie0_default_state: pcie0-default {
4578 drive-strength = <2>;
4579 bias-pull-down;
4585 drive-strength = <2>;
4586 bias-pull-up;
4592 drive-strength = <2>;
4593 bias-pull-up;
4597 pcie1_default_state: pcie1-default {
4601 drive-strength = <2>;
4602 bias-pull-down;
4608 drive-strength = <2>;
4609 bias-pull-up;
4615 drive-strength = <2>;
4616 bias-pull-up;
4620 pcie2_default_state: pcie2-default {
4624 drive-strength = <2>;
4625 bias-pull-down;
4631 drive-strength = <2>;
4632 bias-pull-up;
4638 drive-strength = <2>;
4639 bias-pull-up;
4645 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
4647 #iommu-cells = <2>;
4648 #global-interrupts = <2>;
4750 compatible = "qcom,sm8250-adsp-pas";
4753 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
4758 interrupt-names = "wdog", "fatal", "ready",
4759 "handover", "stop-ack";
4762 clock-names = "xo";
4764 power-domains = <&rpmhpd SM8250_LCX>,
4766 power-domain-names = "lcx", "lmx";
4768 memory-region = <&adsp_mem>;
4772 qcom,smem-states = <&smp2p_adsp_out 0>;
4773 qcom,smem-state-names = "stop";
4777 glink-edge {
4778 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
4785 qcom,remote-pid = <2>;
4788 compatible = "qcom,apr-v2";
4789 qcom,glink-channels = "apr_audio_svc";
4791 #address-cells = <1>;
4792 #size-cells = <0>;
4794 apr-service@3 {
4797 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
4800 q6afe: apr-service@4 {
4803 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
4805 compatible = "qcom,q6afe-dais";
4806 #address-cells = <1>;
4807 #size-cells = <0>;
4808 #sound-dai-cells = <1>;
4812 compatible = "qcom,q6afe-clocks";
4813 #clock-cells = <2>;
4817 q6asm: apr-service@7 {
4820 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
4822 compatible = "qcom,q6asm-dais";
4823 #address-cells = <1>;
4824 #size-cells = <0>;
4825 #sound-dai-cells = <1>;
4830 q6adm: apr-service@8 {
4833 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
4835 compatible = "qcom,q6adm-routing";
4836 #sound-dai-cells = <0>;
4843 qcom,glink-channels = "fastrpcglink-apps-dsp";
4845 qcom,non-secure-domain;
4846 #address-cells = <1>;
4847 #size-cells = <0>;
4849 compute-cb@3 {
4850 compatible = "qcom,fastrpc-compute-cb";
4855 compute-cb@4 {
4856 compatible = "qcom,fastrpc-compute-cb";
4861 compute-cb@5 {
4862 compatible = "qcom,fastrpc-compute-cb";
4870 intc: interrupt-controller@17a00000 {
4871 compatible = "arm,gic-v3";
4872 #interrupt-cells = <3>;
4873 interrupt-controller;
4880 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
4887 #address-cells = <1>;
4888 #size-cells = <1>;
4890 compatible = "arm,armv7-timer-mem";
4892 clock-frequency = <19200000>;
4895 frame-number = <0>;
4903 frame-number = <1>;
4910 frame-number = <2>;
4917 frame-number = <3>;
4924 frame-number = <4>;
4931 frame-number = <5>;
4938 frame-number = <6>;
4947 compatible = "qcom,rpmh-rsc";
4951 reg-names = "drv-0", "drv-1", "drv-2";
4955 qcom,tcs-offset = <0xd00>;
4956 qcom,drv-id = <2>;
4957 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
4960 rpmhcc: clock-controller {
4961 compatible = "qcom,sm8250-rpmh-clk";
4962 #clock-cells = <1>;
4963 clock-names = "xo";
4967 rpmhpd: power-controller {
4968 compatible = "qcom,sm8250-rpmhpd";
4969 #power-domain-cells = <1>;
4970 operating-points-v2 = <&rpmhpd_opp_table>;
4972 rpmhpd_opp_table: opp-table {
4973 compatible = "operating-points-v2";
4976 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4980 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4984 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4988 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4992 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4996 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5000 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5004 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5008 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5012 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5017 apps_bcm_voter: bcm-voter {
5018 compatible = "qcom,bcm-voter";
5023 compatible = "qcom,sm8250-epss-l3";
5027 clock-names = "xo", "alternate";
5029 #interconnect-cells = <1>;
5033 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
5037 reg-names = "freq-domain0", "freq-domain1",
5038 "freq-domain2";
5041 clock-names = "xo", "alternate";
5045 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
5046 #freq-domain-cells = <1>;
5051 compatible = "arm,armv8-timer";
5062 thermal-zones {
5063 cpu0-thermal {
5064 polling-delay-passive = <250>;
5065 polling-delay = <1000>;
5067 thermal-sensors = <&tsens0 1>;
5070 cpu0_alert0: trip-point0 {
5076 cpu0_alert1: trip-point1 {
5089 cooling-maps {
5092 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5099 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5107 cpu1-thermal {
5108 polling-delay-passive = <250>;
5109 polling-delay = <1000>;
5111 thermal-sensors = <&tsens0 2>;
5114 cpu1_alert0: trip-point0 {
5120 cpu1_alert1: trip-point1 {
5133 cooling-maps {
5136 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5143 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5151 cpu2-thermal {
5152 polling-delay-passive = <250>;
5153 polling-delay = <1000>;
5155 thermal-sensors = <&tsens0 3>;
5158 cpu2_alert0: trip-point0 {
5164 cpu2_alert1: trip-point1 {
5177 cooling-maps {
5180 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5187 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5195 cpu3-thermal {
5196 polling-delay-passive = <250>;
5197 polling-delay = <1000>;
5199 thermal-sensors = <&tsens0 4>;
5202 cpu3_alert0: trip-point0 {
5208 cpu3_alert1: trip-point1 {
5221 cooling-maps {
5224 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5231 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5239 cpu4-top-thermal {
5240 polling-delay-passive = <250>;
5241 polling-delay = <1000>;
5243 thermal-sensors = <&tsens0 7>;
5246 cpu4_top_alert0: trip-point0 {
5252 cpu4_top_alert1: trip-point1 {
5265 cooling-maps {
5268 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5275 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5283 cpu5-top-thermal {
5284 polling-delay-passive = <250>;
5285 polling-delay = <1000>;
5287 thermal-sensors = <&tsens0 8>;
5290 cpu5_top_alert0: trip-point0 {
5296 cpu5_top_alert1: trip-point1 {
5309 cooling-maps {
5312 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5319 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5327 cpu6-top-thermal {
5328 polling-delay-passive = <250>;
5329 polling-delay = <1000>;
5331 thermal-sensors = <&tsens0 9>;
5334 cpu6_top_alert0: trip-point0 {
5340 cpu6_top_alert1: trip-point1 {
5353 cooling-maps {
5356 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5363 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5371 cpu7-top-thermal {
5372 polling-delay-passive = <250>;
5373 polling-delay = <1000>;
5375 thermal-sensors = <&tsens0 10>;
5378 cpu7_top_alert0: trip-point0 {
5384 cpu7_top_alert1: trip-point1 {
5397 cooling-maps {
5400 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5407 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5415 cpu4-bottom-thermal {
5416 polling-delay-passive = <250>;
5417 polling-delay = <1000>;
5419 thermal-sensors = <&tsens0 11>;
5422 cpu4_bottom_alert0: trip-point0 {
5428 cpu4_bottom_alert1: trip-point1 {
5441 cooling-maps {
5444 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5451 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5459 cpu5-bottom-thermal {
5460 polling-delay-passive = <250>;
5461 polling-delay = <1000>;
5463 thermal-sensors = <&tsens0 12>;
5466 cpu5_bottom_alert0: trip-point0 {
5472 cpu5_bottom_alert1: trip-point1 {
5485 cooling-maps {
5488 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5495 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5503 cpu6-bottom-thermal {
5504 polling-delay-passive = <250>;
5505 polling-delay = <1000>;
5507 thermal-sensors = <&tsens0 13>;
5510 cpu6_bottom_alert0: trip-point0 {
5516 cpu6_bottom_alert1: trip-point1 {
5529 cooling-maps {
5532 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5539 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5547 cpu7-bottom-thermal {
5548 polling-delay-passive = <250>;
5549 polling-delay = <1000>;
5551 thermal-sensors = <&tsens0 14>;
5554 cpu7_bottom_alert0: trip-point0 {
5560 cpu7_bottom_alert1: trip-point1 {
5573 cooling-maps {
5576 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5583 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5591 aoss0-thermal {
5592 polling-delay-passive = <250>;
5593 polling-delay = <1000>;
5595 thermal-sensors = <&tsens0 0>;
5598 aoss0_alert0: trip-point0 {
5606 cluster0-thermal {
5607 polling-delay-passive = <250>;
5608 polling-delay = <1000>;
5610 thermal-sensors = <&tsens0 5>;
5613 cluster0_alert0: trip-point0 {
5626 cluster1-thermal {
5627 polling-delay-passive = <250>;
5628 polling-delay = <1000>;
5630 thermal-sensors = <&tsens0 6>;
5633 cluster1_alert0: trip-point0 {
5646 gpu-top-thermal {
5647 polling-delay-passive = <250>;
5648 polling-delay = <1000>;
5650 thermal-sensors = <&tsens0 15>;
5653 gpu1_alert0: trip-point0 {
5661 aoss1-thermal {
5662 polling-delay-passive = <250>;
5663 polling-delay = <1000>;
5665 thermal-sensors = <&tsens1 0>;
5668 aoss1_alert0: trip-point0 {
5676 wlan-thermal {
5677 polling-delay-passive = <250>;
5678 polling-delay = <1000>;
5680 thermal-sensors = <&tsens1 1>;
5683 wlan_alert0: trip-point0 {
5691 video-thermal {
5692 polling-delay-passive = <250>;
5693 polling-delay = <1000>;
5695 thermal-sensors = <&tsens1 2>;
5698 video_alert0: trip-point0 {
5706 mem-thermal {
5707 polling-delay-passive = <250>;
5708 polling-delay = <1000>;
5710 thermal-sensors = <&tsens1 3>;
5713 mem_alert0: trip-point0 {
5721 q6-hvx-thermal {
5722 polling-delay-passive = <250>;
5723 polling-delay = <1000>;
5725 thermal-sensors = <&tsens1 4>;
5728 q6_hvx_alert0: trip-point0 {
5736 camera-thermal {
5737 polling-delay-passive = <250>;
5738 polling-delay = <1000>;
5740 thermal-sensors = <&tsens1 5>;
5743 camera_alert0: trip-point0 {
5751 compute-thermal {
5752 polling-delay-passive = <250>;
5753 polling-delay = <1000>;
5755 thermal-sensors = <&tsens1 6>;
5758 compute_alert0: trip-point0 {
5766 npu-thermal {
5767 polling-delay-passive = <250>;
5768 polling-delay = <1000>;
5770 thermal-sensors = <&tsens1 7>;
5773 npu_alert0: trip-point0 {
5781 gpu-bottom-thermal {
5782 polling-delay-passive = <250>;
5783 polling-delay = <1000>;
5785 thermal-sensors = <&tsens1 8>;
5788 gpu2_alert0: trip-point0 {