Lines Matching +full:0 +full:x0aeb0000
80 #clock-cells = <0>;
88 #clock-cells = <0>;
94 #size-cells = <0>;
96 CPU0: cpu@0 {
99 reg = <0x0 0x0>;
106 qcom,freq-domain = <&cpufreq_hw 0>;
123 reg = <0x0 0x100>;
130 qcom,freq-domain = <&cpufreq_hw 0>;
144 reg = <0x0 0x200>;
151 qcom,freq-domain = <&cpufreq_hw 0>;
165 reg = <0x0 0x300>;
172 qcom,freq-domain = <&cpufreq_hw 0>;
186 reg = <0x0 0x400>;
207 reg = <0x0 0x500>;
229 reg = <0x0 0x600>;
250 reg = <0x0 0x700>;
307 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
310 arm,psci-suspend-param = <0x40000004>;
317 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
320 arm,psci-suspend-param = <0x40000004>;
329 CLUSTER_SLEEP_0: cluster-sleep-0 {
332 arm,psci-suspend-param = <0x4100c244>;
642 reg = <0x0 0x80000000 0x0 0x0>;
655 #power-domain-cells = <0>;
661 #power-domain-cells = <0>;
667 #power-domain-cells = <0>;
673 #power-domain-cells = <0>;
679 #power-domain-cells = <0>;
685 #power-domain-cells = <0>;
691 #power-domain-cells = <0>;
697 #power-domain-cells = <0>;
703 #power-domain-cells = <0>;
733 reg = <0x0 0x80000000 0x0 0x600000>;
738 reg = <0x0 0x80700000 0x0 0x160000>;
744 reg = <0x0 0x80860000 0x0 0x20000>;
749 reg = <0x0 0x80900000 0x0 0x200000>;
754 reg = <0x0 0x80b00000 0x0 0x5300000>;
759 reg = <0x0 0x86200000 0x0 0x500000>;
764 reg = <0x0 0x86700000 0x0 0x100000>;
769 reg = <0x0 0x86800000 0x0 0x10000>;
774 reg = <0x0 0x86810000 0x0 0xa000>;
779 reg = <0x0 0x8681a000 0x0 0x2000>;
784 reg = <0x0 0x86900000 0x0 0x500000>;
789 reg = <0x0 0x86e00000 0x0 0x500000>;
794 reg = <0x0 0x87300000 0x0 0x500000>;
799 reg = <0x0 0x87800000 0x0 0x1400000>;
804 reg = <0x0 0x88c00000 0x0 0x1500000>;
809 reg = <0x0 0x8a100000 0x0 0x1d00000>;
814 reg = <0x0 0x8be00000 0x0 0x100000>;
819 reg = <0x0 0x8bf00000 0x0 0x4600000>;
839 qcom,local-pid = <0>;
863 qcom,local-pid = <0>;
887 qcom,local-pid = <0>;
902 soc: soc@0 {
905 ranges = <0 0 0 0 0x10 0>;
906 dma-ranges = <0 0 0 0 0x10 0>;
911 reg = <0x0 0x00100000 0x0 0x1f0000>;
925 reg = <0 0x00408000 0 0x1000>;
934 reg = <0 0x00793000 0 0x1000>;
941 reg = <0 0x00800000 0 0x70000>;
953 dma-channel-mask = <0x3f>;
954 iommus = <&apps_smmu 0x76 0x0>;
961 reg = <0x0 0x008c0000 0x0 0x6000>;
967 iommus = <&apps_smmu 0x63 0x0>;
973 reg = <0 0x00880000 0 0x4000>;
977 pinctrl-0 = <&qup_i2c14_default>;
979 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
980 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
983 #size-cells = <0>;
989 reg = <0 0x00880000 0 0x4000>;
993 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
994 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
999 #size-cells = <0>;
1005 reg = <0 0x00884000 0 0x4000>;
1009 pinctrl-0 = <&qup_i2c15_default>;
1011 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1015 #size-cells = <0>;
1021 reg = <0 0x00884000 0 0x4000>;
1025 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1031 #size-cells = <0>;
1037 reg = <0 0x00888000 0 0x4000>;
1041 pinctrl-0 = <&qup_i2c16_default>;
1043 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1047 #size-cells = <0>;
1053 reg = <0 0x00888000 0 0x4000>;
1057 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1063 #size-cells = <0>;
1069 reg = <0 0x0088c000 0 0x4000>;
1073 pinctrl-0 = <&qup_i2c17_default>;
1075 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1079 #size-cells = <0>;
1085 reg = <0 0x0088c000 0 0x4000>;
1089 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1095 #size-cells = <0>;
1101 reg = <0 0x0088c000 0 0x4000>;
1105 pinctrl-0 = <&qup_uart17_default>;
1114 reg = <0 0x00890000 0 0x4000>;
1118 pinctrl-0 = <&qup_i2c18_default>;
1120 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1124 #size-cells = <0>;
1130 reg = <0 0x00890000 0 0x4000>;
1134 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1140 #size-cells = <0>;
1146 reg = <0 0x00890000 0 0x4000>;
1150 pinctrl-0 = <&qup_uart18_default>;
1159 reg = <0 0x00894000 0 0x4000>;
1163 pinctrl-0 = <&qup_i2c19_default>;
1165 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1169 #size-cells = <0>;
1175 reg = <0 0x00894000 0 0x4000>;
1179 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1185 #size-cells = <0>;
1192 reg = <0 0x00900000 0 0x70000>;
1207 dma-channel-mask = <0x7ff>;
1208 iommus = <&apps_smmu 0x5b6 0x0>;
1215 reg = <0x0 0x009c0000 0x0 0x6000>;
1221 iommus = <&apps_smmu 0x5a3 0x0>;
1227 reg = <0 0x00980000 0 0x4000>;
1231 pinctrl-0 = <&qup_i2c0_default>;
1233 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1234 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1237 #size-cells = <0>;
1243 reg = <0 0x00980000 0 0x4000>;
1247 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1248 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1253 #size-cells = <0>;
1259 reg = <0 0x00984000 0 0x4000>;
1263 pinctrl-0 = <&qup_i2c1_default>;
1265 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1269 #size-cells = <0>;
1275 reg = <0 0x00984000 0 0x4000>;
1279 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1285 #size-cells = <0>;
1291 reg = <0 0x00988000 0 0x4000>;
1295 pinctrl-0 = <&qup_i2c2_default>;
1297 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1301 #size-cells = <0>;
1307 reg = <0 0x00988000 0 0x4000>;
1311 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1317 #size-cells = <0>;
1323 reg = <0 0x00988000 0 0x4000>;
1327 pinctrl-0 = <&qup_uart2_default>;
1336 reg = <0 0x0098c000 0 0x4000>;
1340 pinctrl-0 = <&qup_i2c3_default>;
1342 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1346 #size-cells = <0>;
1352 reg = <0 0x0098c000 0 0x4000>;
1356 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1362 #size-cells = <0>;
1368 reg = <0 0x00990000 0 0x4000>;
1372 pinctrl-0 = <&qup_i2c4_default>;
1374 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1378 #size-cells = <0>;
1384 reg = <0 0x00990000 0 0x4000>;
1388 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1394 #size-cells = <0>;
1400 reg = <0 0x00994000 0 0x4000>;
1404 pinctrl-0 = <&qup_i2c5_default>;
1406 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1410 #size-cells = <0>;
1416 reg = <0 0x00994000 0 0x4000>;
1420 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1426 #size-cells = <0>;
1432 reg = <0 0x00998000 0 0x4000>;
1436 pinctrl-0 = <&qup_i2c6_default>;
1438 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1442 #size-cells = <0>;
1448 reg = <0 0x00998000 0 0x4000>;
1452 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1458 #size-cells = <0>;
1464 reg = <0 0x00998000 0 0x4000>;
1468 pinctrl-0 = <&qup_uart6_default>;
1477 reg = <0 0x0099c000 0 0x4000>;
1481 pinctrl-0 = <&qup_i2c7_default>;
1483 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1487 #size-cells = <0>;
1493 reg = <0 0x0099c000 0 0x4000>;
1497 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1503 #size-cells = <0>;
1510 reg = <0 0x00a00000 0 0x70000>;
1522 dma-channel-mask = <0x3f>;
1523 iommus = <&apps_smmu 0x56 0x0>;
1530 reg = <0x0 0x00ac0000 0x0 0x6000>;
1536 iommus = <&apps_smmu 0x43 0x0>;
1542 reg = <0 0x00a80000 0 0x4000>;
1546 pinctrl-0 = <&qup_i2c8_default>;
1548 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1549 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1552 #size-cells = <0>;
1558 reg = <0 0x00a80000 0 0x4000>;
1562 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1563 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1568 #size-cells = <0>;
1574 reg = <0 0x00a84000 0 0x4000>;
1578 pinctrl-0 = <&qup_i2c9_default>;
1580 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1584 #size-cells = <0>;
1590 reg = <0 0x00a84000 0 0x4000>;
1594 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1600 #size-cells = <0>;
1606 reg = <0 0x00a88000 0 0x4000>;
1610 pinctrl-0 = <&qup_i2c10_default>;
1612 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1616 #size-cells = <0>;
1622 reg = <0 0x00a88000 0 0x4000>;
1626 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1632 #size-cells = <0>;
1638 reg = <0 0x00a8c000 0 0x4000>;
1642 pinctrl-0 = <&qup_i2c11_default>;
1644 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1648 #size-cells = <0>;
1654 reg = <0 0x00a8c000 0 0x4000>;
1658 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1664 #size-cells = <0>;
1670 reg = <0 0x00a90000 0 0x4000>;
1674 pinctrl-0 = <&qup_i2c12_default>;
1676 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1680 #size-cells = <0>;
1686 reg = <0 0x00a90000 0 0x4000>;
1690 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1696 #size-cells = <0>;
1702 reg = <0x0 0x00a90000 0x0 0x4000>;
1706 pinctrl-0 = <&qup_uart12_default>;
1715 reg = <0 0x00a94000 0 0x4000>;
1719 pinctrl-0 = <&qup_i2c13_default>;
1721 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1725 #size-cells = <0>;
1731 reg = <0 0x00a94000 0 0x4000>;
1735 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1741 #size-cells = <0>;
1748 reg = <0 0x01500000 0 0xa580>;
1755 reg = <0 0x01620000 0 0x1c200>;
1762 reg = <0 0x0163d000 0 0x1000>;
1769 reg = <0 0x016e0000 0 0x1f180>;
1776 reg = <0 0x01700000 0 0x33000>;
1783 reg = <0 0x01733000 0 0xa180>;
1790 reg = <0 0x01740000 0 0x1f080>;
1797 reg = <0 0x01c00000 0 0x3000>,
1798 <0 0x60000000 0 0xf1d>,
1799 <0 0x60000f20 0 0xa8>,
1800 <0 0x60001000 0 0x1000>,
1801 <0 0x60100000 0 0x100000>;
1804 linux,pci-domain = <0>;
1805 bus-range = <0x00 0xff>;
1811 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
1812 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
1825 interrupt-map-mask = <0 0 0 0x7>;
1826 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1827 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1828 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1829 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1848 iommus = <&apps_smmu 0x1c00 0x7f>;
1849 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1850 <0x100 &apps_smmu 0x1c01 0x1>;
1864 pinctrl-0 = <&pcie0_default_state>;
1871 reg = <0 0x01c06000 0 0x1c0>;
1890 reg = <0 0x1c06200 0 0x170>, /* tx */
1891 <0 0x1c06400 0 0x200>, /* rx */
1892 <0 0x1c06800 0 0x1f0>, /* pcs */
1893 <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */
1897 #phy-cells = <0>;
1899 #clock-cells = <0>;
1906 reg = <0 0x01c08000 0 0x3000>,
1907 <0 0x40000000 0 0xf1d>,
1908 <0 0x40000f20 0 0xa8>,
1909 <0 0x40001000 0 0x1000>,
1910 <0 0x40100000 0 0x100000>;
1914 bus-range = <0x00 0xff>;
1920 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
1921 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1926 interrupt-map-mask = <0 0 0 0x7>;
1927 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1928 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1929 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1930 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1954 iommus = <&apps_smmu 0x1c80 0x7f>;
1955 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1956 <0x100 &apps_smmu 0x1c81 0x1>;
1970 pinctrl-0 = <&pcie1_default_state>;
1977 reg = <0 0x01c0e000 0 0x1c0>;
1996 reg = <0 0x1c0e200 0 0x170>, /* tx0 */
1997 <0 0x1c0e400 0 0x200>, /* rx0 */
1998 <0 0x1c0ea00 0 0x1f0>, /* pcs */
1999 <0 0x1c0e600 0 0x170>, /* tx1 */
2000 <0 0x1c0e800 0 0x200>, /* rx1 */
2001 <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
2005 #phy-cells = <0>;
2007 #clock-cells = <0>;
2014 reg = <0 0x01c10000 0 0x3000>,
2015 <0 0x64000000 0 0xf1d>,
2016 <0 0x64000f20 0 0xa8>,
2017 <0 0x64001000 0 0x1000>,
2018 <0 0x64100000 0 0x100000>;
2022 bus-range = <0x00 0xff>;
2028 ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>,
2029 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
2034 interrupt-map-mask = <0 0 0 0x7>;
2035 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2036 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2037 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2038 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2062 iommus = <&apps_smmu 0x1d00 0x7f>;
2063 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2064 <0x100 &apps_smmu 0x1d01 0x1>;
2078 pinctrl-0 = <&pcie2_default_state>;
2085 reg = <0 0x1c16000 0 0x1c0>;
2104 reg = <0 0x1c16200 0 0x170>, /* tx0 */
2105 <0 0x1c16400 0 0x200>, /* rx0 */
2106 <0 0x1c16a00 0 0x1f0>, /* pcs */
2107 <0 0x1c16600 0 0x170>, /* tx1 */
2108 <0 0x1c16800 0 0x200>, /* rx1 */
2109 <0 0x1c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
2113 #phy-cells = <0>;
2115 #clock-cells = <0>;
2123 reg = <0 0x01d84000 0 0x3000>;
2134 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>;
2156 <0 0>,
2157 <0 0>,
2159 <0 0>,
2160 <0 0>,
2161 <0 0>,
2162 <0 0>;
2169 reg = <0 0x01d87000 0 0x1c0>;
2178 resets = <&ufs_mem_hc 0>;
2183 reg = <0 0x01d87400 0 0x108>,
2184 <0 0x01d87600 0 0x1e0>,
2185 <0 0x01d87c00 0 0x1dc>,
2186 <0 0x01d87800 0 0x108>,
2187 <0 0x01d87a00 0 0x1e0>;
2188 #phy-cells = <0>;
2194 reg = <0 0x01e00000 0 0x1000>;
2201 reg = <0x0 0x01f40000 0x0 0x40000>;
2207 reg = <0 0x03240000 0 0x1000>;
2217 #clock-cells = <0>;
2223 pinctrl-0 = <&wsa_swr_active>;
2227 reg = <0 0x03250000 0 0x2000>;
2236 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2237 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2238 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2239 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
2243 #size-cells = <0>;
2248 reg = <0 0x03300000 0 0x30000>;
2258 reg = <0 0x03370000 0 0x1000>;
2265 #clock-cells = <0>;
2273 pinctrl-0 = <&rx_swr_active>;
2275 reg = <0 0x3200000 0 0x1000>;
2286 #clock-cells = <0>;
2293 reg = <0 0x3210000 0 0x2000>;
2300 qcom,din-ports = <0>;
2303 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1F 0x1F 0x07 0x00>;
2304 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>;
2305 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>;
2306 qcom,ports-hstart = /bits/ 8 <0xFF 0x03 0xFF 0xFF 0xFF>;
2307 qcom,ports-hstop = /bits/ 8 <0xFF 0x06 0xFF 0xFF 0xFF>;
2308 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xFF 0xFF>;
2309 qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0x00 0x01 0xFF 0xFF>;
2310 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2311 qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0x00>;
2315 #size-cells = <0>;
2320 pinctrl-0 = <&tx_swr_active>;
2322 reg = <0 0x3220000 0 0x1000>;
2333 #clock-cells = <0>;
2343 reg = <0 0x3230000 0 0x2000>;
2354 qcom,dout-ports = <0>;
2355 qcom,ports-sinterval-low = /bits/ 8 <0xFF 0x01 0x01 0x03 0x03>;
2356 qcom,ports-offset1 = /bits/ 8 <0xFF 0x01 0x00 0x02 0x00>;
2357 qcom,ports-offset2 = /bits/ 8 <0xFF 0x00 0x00 0x00 0x00>;
2358 qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2359 qcom,ports-hstart = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2360 qcom,ports-hstop = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2361 qcom,ports-word-length = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2362 qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2363 qcom,ports-lane-control = /bits/ 8 <0xFF 0x00 0x01 0x00 0x01>;
2367 #size-cells = <0>;
2372 reg = <0 0x03380000 0 0x40000>;
2382 reg = <0 0x033c0000 0x0 0x20000>,
2383 <0 0x03550000 0x0 0x10000>;
2386 gpio-ranges = <&lpass_tlmm 0 0 14>;
2530 reg = <0 0x03d00000 0 0x40000>;
2535 iommus = <&adreno_smmu 0 0x401>;
2591 reg = <0 0x03d6a000 0 0x30000>,
2592 <0 0x3de0000 0 0x10000>,
2593 <0 0xb290000 0 0x10000>,
2594 <0 0xb490000 0 0x10000>;
2612 iommus = <&adreno_smmu 5 0x400>;
2630 reg = <0 0x03d90000 0 0x9000>;
2644 reg = <0 0x03da0000 0 0x10000>;
2667 reg = <0 0x05c00000 0 0x4000>;
2670 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2688 qcom,smem-states = <&smp2p_slpi_out 0>;
2709 #size-cells = <0>;
2714 iommus = <&apps_smmu 0x0541 0x0>;
2720 iommus = <&apps_smmu 0x0542 0x0>;
2726 iommus = <&apps_smmu 0x0543 0x0>;
2735 reg = <0 0x08300000 0 0x10000>;
2738 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
2754 qcom,smem-states = <&smp2p_cdsp_out 0>;
2775 #size-cells = <0>;
2780 iommus = <&apps_smmu 0x1001 0x0460>;
2786 iommus = <&apps_smmu 0x1002 0x0460>;
2792 iommus = <&apps_smmu 0x1003 0x0460>;
2798 iommus = <&apps_smmu 0x1004 0x0460>;
2804 iommus = <&apps_smmu 0x1005 0x0460>;
2810 iommus = <&apps_smmu 0x1006 0x0460>;
2816 iommus = <&apps_smmu 0x1007 0x0460>;
2822 iommus = <&apps_smmu 0x1008 0x0460>;
2836 reg = <0 0x088e3000 0 0x400>;
2838 #phy-cells = <0>;
2849 reg = <0 0x088e4000 0 0x400>;
2851 #phy-cells = <0>;
2861 reg = <0 0x088e9000 0 0x200>,
2862 <0 0x088e8000 0 0x40>,
2863 <0 0x088ea000 0 0x200>;
2879 reg = <0 0x088e9200 0 0x200>,
2880 <0 0x088e9400 0 0x200>,
2881 <0 0x088e9c00 0 0x400>,
2882 <0 0x088e9600 0 0x200>,
2883 <0 0x088e9800 0 0x200>,
2884 <0 0x088e9a00 0 0x100>;
2885 #clock-cells = <0>;
2886 #phy-cells = <0>;
2893 reg = <0 0x088ea200 0 0x200>,
2894 <0 0x088ea400 0 0x200>,
2895 <0 0x088eac00 0 0x400>,
2896 <0 0x088ea600 0 0x200>,
2897 <0 0x088ea800 0 0x200>,
2898 <0 0x088eaa00 0 0x100>;
2899 #phy-cells = <0>;
2909 reg = <0 0x088eb000 0 0x200>;
2926 reg = <0 0x088eb200 0 0x200>,
2927 <0 0x088eb400 0 0x200>,
2928 <0 0x088eb800 0 0x800>;
2929 #clock-cells = <0>;
2930 #phy-cells = <0>;
2939 reg = <0 0x08804000 0 0x1000>;
2949 iommus = <&apps_smmu 0x4a0 0x0>;
2950 qcom,dll-config = <0x0007642c>;
2951 qcom,ddr-config = <0x80040868>;
2984 reg = <0 0x090c0000 0 0x4200>;
2991 reg = <0 0x09100000 0 0xb4000>;
2998 reg = <0 0x09990000 0 0x1600>;
3005 reg = <0 0x0a6f8800 0 0x400>;
3044 reg = <0 0x0a600000 0 0xcd00>;
3046 iommus = <&apps_smmu 0x0 0x0>;
3056 reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>;
3062 reg = <0 0x0a8f8800 0 0x400>;
3101 reg = <0 0x0a800000 0 0xcd00>;
3103 iommus = <&apps_smmu 0x20 0>;
3113 reg = <0 0x0aa00000 0 0x100000>;
3130 iommus = <&apps_smmu 0x2100 0x0400>;
3174 reg = <0 0x0abf0000 0 0x10000>;
3189 #size-cells = <0>;
3191 reg = <0 0x0ac4f000 0 0x1000>;
3206 pinctrl-0 = <&cci0_default>;
3212 cci0_i2c0: i2c-bus@0 {
3213 reg = <0>;
3216 #size-cells = <0>;
3223 #size-cells = <0>;
3230 #size-cells = <0>;
3232 reg = <0 0x0ac50000 0 0x1000>;
3247 pinctrl-0 = <&cci1_default>;
3253 cci1_i2c0: i2c-bus@0 {
3254 reg = <0>;
3257 #size-cells = <0>;
3264 #size-cells = <0>;
3272 reg = <0 0xac6a000 0 0x2000>,
3273 <0 0xac6c000 0 0x2000>,
3274 <0 0xac6e000 0 0x1000>,
3275 <0 0xac70000 0 0x1000>,
3276 <0 0xac72000 0 0x1000>,
3277 <0 0xac74000 0 0x1000>,
3278 <0 0xacb4000 0 0xd000>,
3279 <0 0xacc3000 0 0xd000>,
3280 <0 0xacd9000 0 0x2200>,
3281 <0 0xacdb200 0 0x2200>;
3402 iommus = <&apps_smmu 0x800 0x400>,
3403 <&apps_smmu 0x801 0x400>,
3404 <&apps_smmu 0x840 0x400>,
3405 <&apps_smmu 0x841 0x400>,
3406 <&apps_smmu 0xc00 0x400>,
3407 <&apps_smmu 0xc01 0x400>,
3408 <&apps_smmu 0xc40 0x400>,
3409 <&apps_smmu 0xc41 0x400>;
3423 reg = <0 0x0ad00000 0 0x10000>;
3439 reg = <0 0x0ae00000 0 0x1000>;
3458 iommus = <&apps_smmu 0x820 0x402>;
3468 reg = <0 0x0ae01000 0 0x8f000>,
3469 <0 0x0aeb0000 0 0x2008>;
3485 interrupts = <0>;
3489 #size-cells = <0>;
3491 port@0 {
3492 reg = <0>;
3533 reg = <0 0x0ae94000 0 0x400>;
3553 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
3564 #size-cells = <0>;
3568 #size-cells = <0>;
3570 port@0 {
3571 reg = <0>;
3606 reg = <0 0x0ae94400 0 0x200>,
3607 <0 0x0ae94600 0 0x280>,
3608 <0 0x0ae94900 0 0x260>;
3614 #phy-cells = <0>;
3625 reg = <0 0x0ae96000 0 0x400>;
3645 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
3656 #size-cells = <0>;
3660 #size-cells = <0>;
3662 port@0 {
3663 reg = <0>;
3679 reg = <0 0x0ae96400 0 0x200>,
3680 <0 0x0ae96600 0 0x280>,
3681 <0 0x0ae96900 0 0x260>;
3687 #phy-cells = <0>;
3699 reg = <0 0x0af00000 0 0x10000>;
3703 <&dsi0_phy 0>,
3705 <&dsi1_phy 0>,
3707 <&dp_phy 0>,
3723 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
3724 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
3733 reg = <0 0x0c263000 0 0x1ff>, /* TM */
3734 <0 0x0c222000 0 0x1ff>; /* SROT */
3744 reg = <0 0x0c265000 0 0x1ff>, /* TM */
3745 <0 0x0c223000 0 0x1ff>; /* SROT */
3755 reg = <0 0x0c300000 0 0x400>;
3762 #clock-cells = <0>;
3767 reg = <0 0x0c3f0000 0 0x400>;
3772 reg = <0x0 0x0c440000 0x0 0x0001100>,
3773 <0x0 0x0c600000 0x0 0x2000000>,
3774 <0x0 0x0e600000 0x0 0x0100000>,
3775 <0x0 0x0e700000 0x0 0x00a0000>,
3776 <0x0 0x0c40a000 0x0 0x0026000>;
3780 qcom,ee = <0>;
3781 qcom,channel = <0>;
3783 #size-cells = <0>;
3790 reg = <0 0x0f100000 0 0x300000>,
3791 <0 0x0f500000 0 0x300000>,
3792 <0 0x0f900000 0 0x300000>;
3799 gpio-ranges = <&tlmm 0 0 181>;
4646 reg = <0 0x15000000 0 0x100000>;
4751 reg = <0 0x17300000 0 0x100>;
4754 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
4772 qcom,smem-states = <&smp2p_adsp_out 0>;
4792 #size-cells = <0>;
4807 #size-cells = <0>;
4824 #size-cells = <0>;
4826 iommus = <&apps_smmu 0x1801 0x0>;
4836 #sound-dai-cells = <0>;
4847 #size-cells = <0>;
4852 iommus = <&apps_smmu 0x1803 0x0>;
4858 iommus = <&apps_smmu 0x1804 0x0>;
4864 iommus = <&apps_smmu 0x1805 0x0>;
4874 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
4875 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
4881 reg = <0 0x17c10000 0 0x1000>;
4883 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
4889 ranges = <0 0 0 0x20000000>;
4891 reg = <0x0 0x17c20000 0x0 0x1000>;
4895 frame-number = <0>;
4898 reg = <0x17c21000 0x1000>,
4899 <0x17c22000 0x1000>;
4905 reg = <0x17c23000 0x1000>;
4912 reg = <0x17c25000 0x1000>;
4919 reg = <0x17c27000 0x1000>;
4926 reg = <0x17c29000 0x1000>;
4933 reg = <0x17c2b000 0x1000>;
4940 reg = <0x17c2d000 0x1000>;
4948 reg = <0x0 0x18200000 0x0 0x10000>,
4949 <0x0 0x18210000 0x0 0x10000>,
4950 <0x0 0x18220000 0x0 0x10000>;
4951 reg-names = "drv-0", "drv-1", "drv-2";
4955 qcom,tcs-offset = <0xd00>;
5024 reg = <0 0x18590000 0 0x1000>;
5034 reg = <0 0x18591000 0 0x1000>,
5035 <0 0x18592000 0 0x1000>,
5036 <0 0x18593000 0 0x1000>;
5045 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
5595 thermal-sensors = <&tsens0 0>;
5665 thermal-sensors = <&tsens1 0>;