Lines Matching +full:axi +full:- +full:usb2 +full:- +full:device
1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
7 #include <dt-bindings/dma/qcom-gpi.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/power/qcom-rpmpd.h>
10 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
11 #include <dt-bindings/clock/qcom,rpmh.h>
12 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
13 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
15 #include <dt-bindings/interconnect/qcom,sm8150.h>
16 #include <dt-bindings/thermal/thermal.h>
19 interrupt-parent = <&intc>;
21 #address-cells = <2>;
22 #size-cells = <2>;
27 xo_board: xo-board {
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <38400000>;
31 clock-output-names = "xo_board";
34 sleep_clk: sleep-clk {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <32764>;
38 clock-output-names = "sleep_clk";
43 #address-cells = <2>;
44 #size-cells = <0>;
50 enable-method = "psci";
51 capacity-dmips-mhz = <488>;
52 dynamic-power-coefficient = <232>;
53 next-level-cache = <&L2_0>;
54 qcom,freq-domain = <&cpufreq_hw 0>;
55 operating-points-v2 = <&cpu0_opp_table>;
58 power-domains = <&CPU_PD0>;
59 power-domain-names = "psci";
60 #cooling-cells = <2>;
61 L2_0: l2-cache {
63 next-level-cache = <&L3_0>;
64 L3_0: l3-cache {
74 enable-method = "psci";
75 capacity-dmips-mhz = <488>;
76 dynamic-power-coefficient = <232>;
77 next-level-cache = <&L2_100>;
78 qcom,freq-domain = <&cpufreq_hw 0>;
79 operating-points-v2 = <&cpu0_opp_table>;
82 power-domains = <&CPU_PD1>;
83 power-domain-names = "psci";
84 #cooling-cells = <2>;
85 L2_100: l2-cache {
87 next-level-cache = <&L3_0>;
96 enable-method = "psci";
97 capacity-dmips-mhz = <488>;
98 dynamic-power-coefficient = <232>;
99 next-level-cache = <&L2_200>;
100 qcom,freq-domain = <&cpufreq_hw 0>;
101 operating-points-v2 = <&cpu0_opp_table>;
104 power-domains = <&CPU_PD2>;
105 power-domain-names = "psci";
106 #cooling-cells = <2>;
107 L2_200: l2-cache {
109 next-level-cache = <&L3_0>;
117 enable-method = "psci";
118 capacity-dmips-mhz = <488>;
119 dynamic-power-coefficient = <232>;
120 next-level-cache = <&L2_300>;
121 qcom,freq-domain = <&cpufreq_hw 0>;
122 operating-points-v2 = <&cpu0_opp_table>;
125 power-domains = <&CPU_PD3>;
126 power-domain-names = "psci";
127 #cooling-cells = <2>;
128 L2_300: l2-cache {
130 next-level-cache = <&L3_0>;
138 enable-method = "psci";
139 capacity-dmips-mhz = <1024>;
140 dynamic-power-coefficient = <369>;
141 next-level-cache = <&L2_400>;
142 qcom,freq-domain = <&cpufreq_hw 1>;
143 operating-points-v2 = <&cpu4_opp_table>;
146 power-domains = <&CPU_PD4>;
147 power-domain-names = "psci";
148 #cooling-cells = <2>;
149 L2_400: l2-cache {
151 next-level-cache = <&L3_0>;
159 enable-method = "psci";
160 capacity-dmips-mhz = <1024>;
161 dynamic-power-coefficient = <369>;
162 next-level-cache = <&L2_500>;
163 qcom,freq-domain = <&cpufreq_hw 1>;
164 operating-points-v2 = <&cpu4_opp_table>;
167 power-domains = <&CPU_PD5>;
168 power-domain-names = "psci";
169 #cooling-cells = <2>;
170 L2_500: l2-cache {
172 next-level-cache = <&L3_0>;
180 enable-method = "psci";
181 capacity-dmips-mhz = <1024>;
182 dynamic-power-coefficient = <369>;
183 next-level-cache = <&L2_600>;
184 qcom,freq-domain = <&cpufreq_hw 1>;
185 operating-points-v2 = <&cpu4_opp_table>;
188 power-domains = <&CPU_PD6>;
189 power-domain-names = "psci";
190 #cooling-cells = <2>;
191 L2_600: l2-cache {
193 next-level-cache = <&L3_0>;
201 enable-method = "psci";
202 capacity-dmips-mhz = <1024>;
203 dynamic-power-coefficient = <421>;
204 next-level-cache = <&L2_700>;
205 qcom,freq-domain = <&cpufreq_hw 2>;
206 operating-points-v2 = <&cpu7_opp_table>;
209 power-domains = <&CPU_PD7>;
210 power-domain-names = "psci";
211 #cooling-cells = <2>;
212 L2_700: l2-cache {
214 next-level-cache = <&L3_0>;
218 cpu-map {
254 idle-states {
255 entry-method = "psci";
257 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
258 compatible = "arm,idle-state";
259 idle-state-name = "little-rail-power-collapse";
260 arm,psci-suspend-param = <0x40000004>;
261 entry-latency-us = <355>;
262 exit-latency-us = <909>;
263 min-residency-us = <3934>;
264 local-timer-stop;
267 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
268 compatible = "arm,idle-state";
269 idle-state-name = "big-rail-power-collapse";
270 arm,psci-suspend-param = <0x40000004>;
271 entry-latency-us = <241>;
272 exit-latency-us = <1461>;
273 min-residency-us = <4488>;
274 local-timer-stop;
278 domain-idle-states {
279 CLUSTER_SLEEP_0: cluster-sleep-0 {
280 compatible = "domain-idle-state";
281 idle-state-name = "cluster-power-collapse";
282 arm,psci-suspend-param = <0x4100c244>;
283 entry-latency-us = <3263>;
284 exit-latency-us = <6562>;
285 min-residency-us = <9987>;
286 local-timer-stop;
291 cpu0_opp_table: opp-table-cpu0 {
292 compatible = "operating-points-v2";
293 opp-shared;
295 cpu0_opp1: opp-300000000 {
296 opp-hz = /bits/ 64 <300000000>;
297 opp-peak-kBps = <800000 9600000>;
300 cpu0_opp2: opp-403200000 {
301 opp-hz = /bits/ 64 <403200000>;
302 opp-peak-kBps = <800000 9600000>;
305 cpu0_opp3: opp-499200000 {
306 opp-hz = /bits/ 64 <499200000>;
307 opp-peak-kBps = <800000 12902400>;
310 cpu0_opp4: opp-576000000 {
311 opp-hz = /bits/ 64 <576000000>;
312 opp-peak-kBps = <800000 12902400>;
315 cpu0_opp5: opp-672000000 {
316 opp-hz = /bits/ 64 <672000000>;
317 opp-peak-kBps = <800000 15974400>;
320 cpu0_opp6: opp-768000000 {
321 opp-hz = /bits/ 64 <768000000>;
322 opp-peak-kBps = <1804000 19660800>;
325 cpu0_opp7: opp-844800000 {
326 opp-hz = /bits/ 64 <844800000>;
327 opp-peak-kBps = <1804000 19660800>;
330 cpu0_opp8: opp-940800000 {
331 opp-hz = /bits/ 64 <940800000>;
332 opp-peak-kBps = <1804000 22732800>;
335 cpu0_opp9: opp-1036800000 {
336 opp-hz = /bits/ 64 <1036800000>;
337 opp-peak-kBps = <1804000 22732800>;
340 cpu0_opp10: opp-1113600000 {
341 opp-hz = /bits/ 64 <1113600000>;
342 opp-peak-kBps = <2188000 25804800>;
345 cpu0_opp11: opp-1209600000 {
346 opp-hz = /bits/ 64 <1209600000>;
347 opp-peak-kBps = <2188000 31948800>;
350 cpu0_opp12: opp-1305600000 {
351 opp-hz = /bits/ 64 <1305600000>;
352 opp-peak-kBps = <3072000 31948800>;
355 cpu0_opp13: opp-1382400000 {
356 opp-hz = /bits/ 64 <1382400000>;
357 opp-peak-kBps = <3072000 31948800>;
360 cpu0_opp14: opp-1478400000 {
361 opp-hz = /bits/ 64 <1478400000>;
362 opp-peak-kBps = <3072000 31948800>;
365 cpu0_opp15: opp-1555200000 {
366 opp-hz = /bits/ 64 <1555200000>;
367 opp-peak-kBps = <3072000 40550400>;
370 cpu0_opp16: opp-1632000000 {
371 opp-hz = /bits/ 64 <1632000000>;
372 opp-peak-kBps = <3072000 40550400>;
375 cpu0_opp17: opp-1708800000 {
376 opp-hz = /bits/ 64 <1708800000>;
377 opp-peak-kBps = <3072000 43008000>;
380 cpu0_opp18: opp-1785600000 {
381 opp-hz = /bits/ 64 <1785600000>;
382 opp-peak-kBps = <3072000 43008000>;
386 cpu4_opp_table: opp-table-cpu4 {
387 compatible = "operating-points-v2";
388 opp-shared;
390 cpu4_opp1: opp-710400000 {
391 opp-hz = /bits/ 64 <710400000>;
392 opp-peak-kBps = <1804000 15974400>;
395 cpu4_opp2: opp-825600000 {
396 opp-hz = /bits/ 64 <825600000>;
397 opp-peak-kBps = <2188000 19660800>;
400 cpu4_opp3: opp-940800000 {
401 opp-hz = /bits/ 64 <940800000>;
402 opp-peak-kBps = <2188000 22732800>;
405 cpu4_opp4: opp-1056000000 {
406 opp-hz = /bits/ 64 <1056000000>;
407 opp-peak-kBps = <3072000 25804800>;
410 cpu4_opp5: opp-1171200000 {
411 opp-hz = /bits/ 64 <1171200000>;
412 opp-peak-kBps = <3072000 31948800>;
415 cpu4_opp6: opp-1286400000 {
416 opp-hz = /bits/ 64 <1286400000>;
417 opp-peak-kBps = <4068000 31948800>;
420 cpu4_opp7: opp-1401600000 {
421 opp-hz = /bits/ 64 <1401600000>;
422 opp-peak-kBps = <4068000 31948800>;
425 cpu4_opp8: opp-1497600000 {
426 opp-hz = /bits/ 64 <1497600000>;
427 opp-peak-kBps = <4068000 40550400>;
430 cpu4_opp9: opp-1612800000 {
431 opp-hz = /bits/ 64 <1612800000>;
432 opp-peak-kBps = <4068000 40550400>;
435 cpu4_opp10: opp-1708800000 {
436 opp-hz = /bits/ 64 <1708800000>;
437 opp-peak-kBps = <4068000 43008000>;
440 cpu4_opp11: opp-1804800000 {
441 opp-hz = /bits/ 64 <1804800000>;
442 opp-peak-kBps = <6220000 43008000>;
445 cpu4_opp12: opp-1920000000 {
446 opp-hz = /bits/ 64 <1920000000>;
447 opp-peak-kBps = <6220000 49152000>;
450 cpu4_opp13: opp-2016000000 {
451 opp-hz = /bits/ 64 <2016000000>;
452 opp-peak-kBps = <7216000 49152000>;
455 cpu4_opp14: opp-2131200000 {
456 opp-hz = /bits/ 64 <2131200000>;
457 opp-peak-kBps = <8368000 49152000>;
460 cpu4_opp15: opp-2227200000 {
461 opp-hz = /bits/ 64 <2227200000>;
462 opp-peak-kBps = <8368000 51609600>;
465 cpu4_opp16: opp-2323200000 {
466 opp-hz = /bits/ 64 <2323200000>;
467 opp-peak-kBps = <8368000 51609600>;
470 cpu4_opp17: opp-2419200000 {
471 opp-hz = /bits/ 64 <2419200000>;
472 opp-peak-kBps = <8368000 51609600>;
476 cpu7_opp_table: opp-table-cpu7 {
477 compatible = "operating-points-v2";
478 opp-shared;
480 cpu7_opp1: opp-825600000 {
481 opp-hz = /bits/ 64 <825600000>;
482 opp-peak-kBps = <2188000 19660800>;
485 cpu7_opp2: opp-940800000 {
486 opp-hz = /bits/ 64 <940800000>;
487 opp-peak-kBps = <2188000 22732800>;
490 cpu7_opp3: opp-1056000000 {
491 opp-hz = /bits/ 64 <1056000000>;
492 opp-peak-kBps = <3072000 25804800>;
495 cpu7_opp4: opp-1171200000 {
496 opp-hz = /bits/ 64 <1171200000>;
497 opp-peak-kBps = <3072000 31948800>;
500 cpu7_opp5: opp-1286400000 {
501 opp-hz = /bits/ 64 <1286400000>;
502 opp-peak-kBps = <4068000 31948800>;
505 cpu7_opp6: opp-1401600000 {
506 opp-hz = /bits/ 64 <1401600000>;
507 opp-peak-kBps = <4068000 31948800>;
510 cpu7_opp7: opp-1497600000 {
511 opp-hz = /bits/ 64 <1497600000>;
512 opp-peak-kBps = <4068000 40550400>;
515 cpu7_opp8: opp-1612800000 {
516 opp-hz = /bits/ 64 <1612800000>;
517 opp-peak-kBps = <4068000 40550400>;
520 cpu7_opp9: opp-1708800000 {
521 opp-hz = /bits/ 64 <1708800000>;
522 opp-peak-kBps = <4068000 43008000>;
525 cpu7_opp10: opp-1804800000 {
526 opp-hz = /bits/ 64 <1804800000>;
527 opp-peak-kBps = <6220000 43008000>;
530 cpu7_opp11: opp-1920000000 {
531 opp-hz = /bits/ 64 <1920000000>;
532 opp-peak-kBps = <6220000 49152000>;
535 cpu7_opp12: opp-2016000000 {
536 opp-hz = /bits/ 64 <2016000000>;
537 opp-peak-kBps = <7216000 49152000>;
540 cpu7_opp13: opp-2131200000 {
541 opp-hz = /bits/ 64 <2131200000>;
542 opp-peak-kBps = <8368000 49152000>;
545 cpu7_opp14: opp-2227200000 {
546 opp-hz = /bits/ 64 <2227200000>;
547 opp-peak-kBps = <8368000 51609600>;
550 cpu7_opp15: opp-2323200000 {
551 opp-hz = /bits/ 64 <2323200000>;
552 opp-peak-kBps = <8368000 51609600>;
555 cpu7_opp16: opp-2419200000 {
556 opp-hz = /bits/ 64 <2419200000>;
557 opp-peak-kBps = <8368000 51609600>;
560 cpu7_opp17: opp-2534400000 {
561 opp-hz = /bits/ 64 <2534400000>;
562 opp-peak-kBps = <8368000 51609600>;
565 cpu7_opp18: opp-2649600000 {
566 opp-hz = /bits/ 64 <2649600000>;
567 opp-peak-kBps = <8368000 51609600>;
570 cpu7_opp19: opp-2745600000 {
571 opp-hz = /bits/ 64 <2745600000>;
572 opp-peak-kBps = <8368000 51609600>;
575 cpu7_opp20: opp-2841600000 {
576 opp-hz = /bits/ 64 <2841600000>;
577 opp-peak-kBps = <8368000 51609600>;
583 compatible = "qcom,scm-sm8150", "qcom,scm";
584 #reset-cells = <1>;
595 compatible = "arm,armv8-pmuv3";
600 compatible = "arm,psci-1.0";
604 #power-domain-cells = <0>;
605 power-domains = <&CLUSTER_PD>;
606 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
610 #power-domain-cells = <0>;
611 power-domains = <&CLUSTER_PD>;
612 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
616 #power-domain-cells = <0>;
617 power-domains = <&CLUSTER_PD>;
618 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
622 #power-domain-cells = <0>;
623 power-domains = <&CLUSTER_PD>;
624 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
628 #power-domain-cells = <0>;
629 power-domains = <&CLUSTER_PD>;
630 domain-idle-states = <&BIG_CPU_SLEEP_0>;
634 #power-domain-cells = <0>;
635 power-domains = <&CLUSTER_PD>;
636 domain-idle-states = <&BIG_CPU_SLEEP_0>;
640 #power-domain-cells = <0>;
641 power-domains = <&CLUSTER_PD>;
642 domain-idle-states = <&BIG_CPU_SLEEP_0>;
646 #power-domain-cells = <0>;
647 power-domains = <&CLUSTER_PD>;
648 domain-idle-states = <&BIG_CPU_SLEEP_0>;
651 CLUSTER_PD: cpu-cluster0 {
652 #power-domain-cells = <0>;
653 domain-idle-states = <&CLUSTER_SLEEP_0>;
657 reserved-memory {
658 #address-cells = <2>;
659 #size-cells = <2>;
664 no-map;
669 no-map;
674 no-map;
678 compatible = "qcom,cmd-db";
680 no-map;
685 no-map;
690 no-map;
694 compatible = "qcom,rmtfs-mem";
696 no-map;
698 qcom,client-id = <1>;
704 no-map;
709 no-map;
714 no-map;
719 no-map;
724 no-map;
729 no-map;
734 no-map;
739 no-map;
744 no-map;
749 no-map;
754 no-map;
759 no-map;
764 no-map;
770 memory-region = <&smem_mem>;
774 smp2p-cdsp {
782 qcom,local-pid = <0>;
783 qcom,remote-pid = <5>;
785 cdsp_smp2p_out: master-kernel {
786 qcom,entry-name = "master-kernel";
787 #qcom,smem-state-cells = <1>;
790 cdsp_smp2p_in: slave-kernel {
791 qcom,entry-name = "slave-kernel";
793 interrupt-controller;
794 #interrupt-cells = <2>;
798 smp2p-lpass {
806 qcom,local-pid = <0>;
807 qcom,remote-pid = <2>;
809 adsp_smp2p_out: master-kernel {
810 qcom,entry-name = "master-kernel";
811 #qcom,smem-state-cells = <1>;
814 adsp_smp2p_in: slave-kernel {
815 qcom,entry-name = "slave-kernel";
817 interrupt-controller;
818 #interrupt-cells = <2>;
822 smp2p-mpss {
830 qcom,local-pid = <0>;
831 qcom,remote-pid = <1>;
833 modem_smp2p_out: master-kernel {
834 qcom,entry-name = "master-kernel";
835 #qcom,smem-state-cells = <1>;
838 modem_smp2p_in: slave-kernel {
839 qcom,entry-name = "slave-kernel";
841 interrupt-controller;
842 #interrupt-cells = <2>;
846 smp2p-slpi {
854 qcom,local-pid = <0>;
855 qcom,remote-pid = <3>;
857 slpi_smp2p_out: master-kernel {
858 qcom,entry-name = "master-kernel";
859 #qcom,smem-state-cells = <1>;
862 slpi_smp2p_in: slave-kernel {
863 qcom,entry-name = "slave-kernel";
865 interrupt-controller;
866 #interrupt-cells = <2>;
871 #address-cells = <2>;
872 #size-cells = <2>;
874 dma-ranges = <0 0 0 0 0x10 0>;
875 compatible = "simple-bus";
877 gcc: clock-controller@100000 {
878 compatible = "qcom,gcc-sm8150";
880 #clock-cells = <1>;
881 #reset-cells = <1>;
882 #power-domain-cells = <1>;
883 clock-names = "bi_tcxo",
889 gpi_dma0: dma-controller@800000 {
890 compatible = "qcom,sm8150-gpi-dma";
905 dma-channels = <13>;
906 dma-channel-mask = <0xfa>;
908 #dma-cells = <3>;
913 compatible = "qcom,sm8150-ethqos";
916 reg-names = "stmmaceth", "rgmii";
917 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
924 interrupt-names = "macirq", "eth_lpi";
926 power-domains = <&gcc EMAC_GDSC>;
932 rx-fifo-depth = <4096>;
933 tx-fifo-depth = <4096>;
940 compatible = "qcom,geni-se-qup";
942 clock-names = "m-ahb", "s-ahb";
946 #address-cells = <2>;
947 #size-cells = <2>;
952 compatible = "qcom,geni-i2c";
954 clock-names = "se";
958 dma-names = "tx", "rx";
959 pinctrl-names = "default";
960 pinctrl-0 = <&qup_i2c0_default>;
962 #address-cells = <1>;
963 #size-cells = <0>;
968 compatible = "qcom,geni-spi";
970 reg-names = "se";
971 clock-names = "se";
975 dma-names = "tx", "rx";
976 pinctrl-names = "default";
977 pinctrl-0 = <&qup_spi0_default>;
979 spi-max-frequency = <50000000>;
980 #address-cells = <1>;
981 #size-cells = <0>;
986 compatible = "qcom,geni-i2c";
988 clock-names = "se";
992 dma-names = "tx", "rx";
993 pinctrl-names = "default";
994 pinctrl-0 = <&qup_i2c1_default>;
996 #address-cells = <1>;
997 #size-cells = <0>;
1002 compatible = "qcom,geni-spi";
1004 reg-names = "se";
1005 clock-names = "se";
1009 dma-names = "tx", "rx";
1010 pinctrl-names = "default";
1011 pinctrl-0 = <&qup_spi1_default>;
1013 spi-max-frequency = <50000000>;
1014 #address-cells = <1>;
1015 #size-cells = <0>;
1020 compatible = "qcom,geni-i2c";
1022 clock-names = "se";
1026 dma-names = "tx", "rx";
1027 pinctrl-names = "default";
1028 pinctrl-0 = <&qup_i2c2_default>;
1030 #address-cells = <1>;
1031 #size-cells = <0>;
1036 compatible = "qcom,geni-spi";
1038 reg-names = "se";
1039 clock-names = "se";
1043 dma-names = "tx", "rx";
1044 pinctrl-names = "default";
1045 pinctrl-0 = <&qup_spi2_default>;
1047 spi-max-frequency = <50000000>;
1048 #address-cells = <1>;
1049 #size-cells = <0>;
1054 compatible = "qcom,geni-i2c";
1056 clock-names = "se";
1060 dma-names = "tx", "rx";
1061 pinctrl-names = "default";
1062 pinctrl-0 = <&qup_i2c3_default>;
1064 #address-cells = <1>;
1065 #size-cells = <0>;
1070 compatible = "qcom,geni-spi";
1072 reg-names = "se";
1073 clock-names = "se";
1077 dma-names = "tx", "rx";
1078 pinctrl-names = "default";
1079 pinctrl-0 = <&qup_spi3_default>;
1081 spi-max-frequency = <50000000>;
1082 #address-cells = <1>;
1083 #size-cells = <0>;
1088 compatible = "qcom,geni-i2c";
1090 clock-names = "se";
1094 dma-names = "tx", "rx";
1095 pinctrl-names = "default";
1096 pinctrl-0 = <&qup_i2c4_default>;
1098 #address-cells = <1>;
1099 #size-cells = <0>;
1104 compatible = "qcom,geni-spi";
1106 reg-names = "se";
1107 clock-names = "se";
1111 dma-names = "tx", "rx";
1112 pinctrl-names = "default";
1113 pinctrl-0 = <&qup_spi4_default>;
1115 spi-max-frequency = <50000000>;
1116 #address-cells = <1>;
1117 #size-cells = <0>;
1122 compatible = "qcom,geni-i2c";
1124 clock-names = "se";
1128 dma-names = "tx", "rx";
1129 pinctrl-names = "default";
1130 pinctrl-0 = <&qup_i2c5_default>;
1132 #address-cells = <1>;
1133 #size-cells = <0>;
1138 compatible = "qcom,geni-spi";
1140 reg-names = "se";
1141 clock-names = "se";
1145 dma-names = "tx", "rx";
1146 pinctrl-names = "default";
1147 pinctrl-0 = <&qup_spi5_default>;
1149 spi-max-frequency = <50000000>;
1150 #address-cells = <1>;
1151 #size-cells = <0>;
1156 compatible = "qcom,geni-i2c";
1158 clock-names = "se";
1162 dma-names = "tx", "rx";
1163 pinctrl-names = "default";
1164 pinctrl-0 = <&qup_i2c6_default>;
1166 #address-cells = <1>;
1167 #size-cells = <0>;
1172 compatible = "qcom,geni-spi";
1174 reg-names = "se";
1175 clock-names = "se";
1179 dma-names = "tx", "rx";
1180 pinctrl-names = "default";
1181 pinctrl-0 = <&qup_spi6_default>;
1183 spi-max-frequency = <50000000>;
1184 #address-cells = <1>;
1185 #size-cells = <0>;
1190 compatible = "qcom,geni-i2c";
1192 clock-names = "se";
1196 dma-names = "tx", "rx";
1197 pinctrl-names = "default";
1198 pinctrl-0 = <&qup_i2c7_default>;
1200 #address-cells = <1>;
1201 #size-cells = <0>;
1206 compatible = "qcom,geni-spi";
1208 reg-names = "se";
1209 clock-names = "se";
1213 dma-names = "tx", "rx";
1214 pinctrl-names = "default";
1215 pinctrl-0 = <&qup_spi7_default>;
1217 spi-max-frequency = <50000000>;
1218 #address-cells = <1>;
1219 #size-cells = <0>;
1224 gpi_dma1: dma-controller@a00000 {
1225 compatible = "qcom,sm8150-gpi-dma";
1240 dma-channels = <13>;
1241 dma-channel-mask = <0xfa>;
1243 #dma-cells = <3>;
1248 compatible = "qcom,geni-se-qup";
1250 clock-names = "m-ahb", "s-ahb";
1254 #address-cells = <2>;
1255 #size-cells = <2>;
1260 compatible = "qcom,geni-i2c";
1262 clock-names = "se";
1266 dma-names = "tx", "rx";
1267 pinctrl-names = "default";
1268 pinctrl-0 = <&qup_i2c8_default>;
1270 #address-cells = <1>;
1271 #size-cells = <0>;
1276 compatible = "qcom,geni-spi";
1278 reg-names = "se";
1279 clock-names = "se";
1283 dma-names = "tx", "rx";
1284 pinctrl-names = "default";
1285 pinctrl-0 = <&qup_spi8_default>;
1287 spi-max-frequency = <50000000>;
1288 #address-cells = <1>;
1289 #size-cells = <0>;
1294 compatible = "qcom,geni-i2c";
1296 clock-names = "se";
1300 dma-names = "tx", "rx";
1301 pinctrl-names = "default";
1302 pinctrl-0 = <&qup_i2c9_default>;
1304 #address-cells = <1>;
1305 #size-cells = <0>;
1310 compatible = "qcom,geni-spi";
1312 reg-names = "se";
1313 clock-names = "se";
1317 dma-names = "tx", "rx";
1318 pinctrl-names = "default";
1319 pinctrl-0 = <&qup_spi9_default>;
1321 spi-max-frequency = <50000000>;
1322 #address-cells = <1>;
1323 #size-cells = <0>;
1328 compatible = "qcom,geni-i2c";
1330 clock-names = "se";
1334 dma-names = "tx", "rx";
1335 pinctrl-names = "default";
1336 pinctrl-0 = <&qup_i2c10_default>;
1338 #address-cells = <1>;
1339 #size-cells = <0>;
1344 compatible = "qcom,geni-spi";
1346 reg-names = "se";
1347 clock-names = "se";
1351 dma-names = "tx", "rx";
1352 pinctrl-names = "default";
1353 pinctrl-0 = <&qup_spi10_default>;
1355 spi-max-frequency = <50000000>;
1356 #address-cells = <1>;
1357 #size-cells = <0>;
1362 compatible = "qcom,geni-i2c";
1364 clock-names = "se";
1368 dma-names = "tx", "rx";
1369 pinctrl-names = "default";
1370 pinctrl-0 = <&qup_i2c11_default>;
1372 #address-cells = <1>;
1373 #size-cells = <0>;
1378 compatible = "qcom,geni-spi";
1380 reg-names = "se";
1381 clock-names = "se";
1385 dma-names = "tx", "rx";
1386 pinctrl-names = "default";
1387 pinctrl-0 = <&qup_spi11_default>;
1389 spi-max-frequency = <50000000>;
1390 #address-cells = <1>;
1391 #size-cells = <0>;
1396 compatible = "qcom,geni-debug-uart";
1398 clock-names = "se";
1405 compatible = "qcom,geni-i2c";
1407 clock-names = "se";
1411 dma-names = "tx", "rx";
1412 pinctrl-names = "default";
1413 pinctrl-0 = <&qup_i2c12_default>;
1415 #address-cells = <1>;
1416 #size-cells = <0>;
1421 compatible = "qcom,geni-spi";
1423 reg-names = "se";
1424 clock-names = "se";
1428 dma-names = "tx", "rx";
1429 pinctrl-names = "default";
1430 pinctrl-0 = <&qup_spi12_default>;
1432 spi-max-frequency = <50000000>;
1433 #address-cells = <1>;
1434 #size-cells = <0>;
1439 compatible = "qcom,geni-i2c";
1441 clock-names = "se";
1445 dma-names = "tx", "rx";
1446 pinctrl-names = "default";
1447 pinctrl-0 = <&qup_i2c16_default>;
1449 #address-cells = <1>;
1450 #size-cells = <0>;
1455 compatible = "qcom,geni-spi";
1457 reg-names = "se";
1458 clock-names = "se";
1462 dma-names = "tx", "rx";
1463 pinctrl-names = "default";
1464 pinctrl-0 = <&qup_spi16_default>;
1466 spi-max-frequency = <50000000>;
1467 #address-cells = <1>;
1468 #size-cells = <0>;
1473 gpi_dma2: dma-controller@c00000 {
1474 compatible = "qcom,sm8150-gpi-dma";
1489 dma-channels = <13>;
1490 dma-channel-mask = <0xfa>;
1492 #dma-cells = <3>;
1497 compatible = "qcom,geni-se-qup";
1500 clock-names = "m-ahb", "s-ahb";
1504 #address-cells = <2>;
1505 #size-cells = <2>;
1510 compatible = "qcom,geni-i2c";
1512 clock-names = "se";
1516 dma-names = "tx", "rx";
1517 pinctrl-names = "default";
1518 pinctrl-0 = <&qup_i2c17_default>;
1520 #address-cells = <1>;
1521 #size-cells = <0>;
1526 compatible = "qcom,geni-spi";
1528 reg-names = "se";
1529 clock-names = "se";
1533 dma-names = "tx", "rx";
1534 pinctrl-names = "default";
1535 pinctrl-0 = <&qup_spi17_default>;
1537 spi-max-frequency = <50000000>;
1538 #address-cells = <1>;
1539 #size-cells = <0>;
1544 compatible = "qcom,geni-i2c";
1546 clock-names = "se";
1550 dma-names = "tx", "rx";
1551 pinctrl-names = "default";
1552 pinctrl-0 = <&qup_i2c18_default>;
1554 #address-cells = <1>;
1555 #size-cells = <0>;
1560 compatible = "qcom,geni-spi";
1562 reg-names = "se";
1563 clock-names = "se";
1567 dma-names = "tx", "rx";
1568 pinctrl-names = "default";
1569 pinctrl-0 = <&qup_spi18_default>;
1571 spi-max-frequency = <50000000>;
1572 #address-cells = <1>;
1573 #size-cells = <0>;
1578 compatible = "qcom,geni-i2c";
1580 clock-names = "se";
1584 dma-names = "tx", "rx";
1585 pinctrl-names = "default";
1586 pinctrl-0 = <&qup_i2c19_default>;
1588 #address-cells = <1>;
1589 #size-cells = <0>;
1594 compatible = "qcom,geni-spi";
1596 reg-names = "se";
1597 clock-names = "se";
1601 dma-names = "tx", "rx";
1602 pinctrl-names = "default";
1603 pinctrl-0 = <&qup_spi19_default>;
1605 spi-max-frequency = <50000000>;
1606 #address-cells = <1>;
1607 #size-cells = <0>;
1612 compatible = "qcom,geni-i2c";
1614 clock-names = "se";
1618 dma-names = "tx", "rx";
1619 pinctrl-names = "default";
1620 pinctrl-0 = <&qup_i2c13_default>;
1622 #address-cells = <1>;
1623 #size-cells = <0>;
1628 compatible = "qcom,geni-spi";
1630 reg-names = "se";
1631 clock-names = "se";
1635 dma-names = "tx", "rx";
1636 pinctrl-names = "default";
1637 pinctrl-0 = <&qup_spi13_default>;
1639 spi-max-frequency = <50000000>;
1640 #address-cells = <1>;
1641 #size-cells = <0>;
1646 compatible = "qcom,geni-i2c";
1648 clock-names = "se";
1652 dma-names = "tx", "rx";
1653 pinctrl-names = "default";
1654 pinctrl-0 = <&qup_i2c14_default>;
1656 #address-cells = <1>;
1657 #size-cells = <0>;
1662 compatible = "qcom,geni-spi";
1664 reg-names = "se";
1665 clock-names = "se";
1669 dma-names = "tx", "rx";
1670 pinctrl-names = "default";
1671 pinctrl-0 = <&qup_spi14_default>;
1673 spi-max-frequency = <50000000>;
1674 #address-cells = <1>;
1675 #size-cells = <0>;
1680 compatible = "qcom,geni-i2c";
1682 clock-names = "se";
1686 dma-names = "tx", "rx";
1687 pinctrl-names = "default";
1688 pinctrl-0 = <&qup_i2c15_default>;
1690 #address-cells = <1>;
1691 #size-cells = <0>;
1696 compatible = "qcom,geni-spi";
1698 reg-names = "se";
1699 clock-names = "se";
1703 dma-names = "tx", "rx";
1704 pinctrl-names = "default";
1705 pinctrl-0 = <&qup_spi15_default>;
1707 spi-max-frequency = <50000000>;
1708 #address-cells = <1>;
1709 #size-cells = <0>;
1715 compatible = "qcom,sm8150-config-noc";
1717 #interconnect-cells = <1>;
1718 qcom,bcm-voters = <&apps_bcm_voter>;
1722 compatible = "qcom,sm8150-system-noc";
1724 #interconnect-cells = <1>;
1725 qcom,bcm-voters = <&apps_bcm_voter>;
1729 compatible = "qcom,sm8150-mc-virt";
1731 #interconnect-cells = <1>;
1732 qcom,bcm-voters = <&apps_bcm_voter>;
1736 compatible = "qcom,sm8150-aggre1-noc";
1738 #interconnect-cells = <1>;
1739 qcom,bcm-voters = <&apps_bcm_voter>;
1743 compatible = "qcom,sm8150-aggre2-noc";
1745 #interconnect-cells = <1>;
1746 qcom,bcm-voters = <&apps_bcm_voter>;
1750 compatible = "qcom,sm8150-compute-noc";
1752 #interconnect-cells = <1>;
1753 qcom,bcm-voters = <&apps_bcm_voter>;
1757 compatible = "qcom,sm8150-mmss-noc";
1759 #interconnect-cells = <1>;
1760 qcom,bcm-voters = <&apps_bcm_voter>;
1763 system-cache-controller@9200000 {
1764 compatible = "qcom,sm8150-llcc";
1766 reg-names = "llcc_base", "llcc_broadcast_base";
1771 compatible = "qcom,pcie-sm8150", "snps,dw-pcie";
1777 reg-names = "parf", "dbi", "elbi", "atu", "config";
1779 linux,pci-domain = <0>;
1780 bus-range = <0x00 0xff>;
1781 num-lanes = <1>;
1783 #address-cells = <3>;
1784 #size-cells = <2>;
1790 interrupt-names = "msi";
1791 #interrupt-cells = <1>;
1792 interrupt-map-mask = <0 0 0 0x7>;
1793 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1805 clock-names = "pipe",
1814 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
1818 reset-names = "pci";
1820 power-domains = <&gcc PCIE_0_GDSC>;
1823 phy-names = "pciephy";
1825 perst-gpio = <&tlmm 35 GPIO_ACTIVE_HIGH>;
1826 enable-gpio = <&tlmm 37 GPIO_ACTIVE_HIGH>;
1828 pinctrl-names = "default";
1829 pinctrl-0 = <&pcie0_default_state>;
1835 compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy";
1837 #address-cells = <2>;
1838 #size-cells = <2>;
1843 clock-names = "aux", "cfg_ahb", "refgen";
1846 reset-names = "phy";
1848 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1849 assigned-clock-rates = <100000000>;
1859 clock-names = "pipe0";
1861 #phy-cells = <0>;
1862 clock-output-names = "pcie_0_pipe_clk";
1867 compatible = "qcom,pcie-sm8150", "snps,dw-pcie";
1873 reg-names = "parf", "dbi", "elbi", "atu", "config";
1875 linux,pci-domain = <1>;
1876 bus-range = <0x00 0xff>;
1877 num-lanes = <2>;
1879 #address-cells = <3>;
1880 #size-cells = <2>;
1886 interrupt-names = "msi";
1887 #interrupt-cells = <1>;
1888 interrupt-map-mask = <0 0 0 0x7>;
1889 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1901 clock-names = "pipe",
1909 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1910 assigned-clock-rates = <19200000>;
1913 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
1917 reset-names = "pci";
1919 power-domains = <&gcc PCIE_1_GDSC>;
1922 phy-names = "pciephy";
1924 perst-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>;
1925 enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>;
1927 pinctrl-names = "default";
1928 pinctrl-0 = <&pcie1_default_state>;
1934 compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy";
1936 #address-cells = <2>;
1937 #size-cells = <2>;
1942 clock-names = "aux", "cfg_ahb", "refgen";
1945 reset-names = "phy";
1947 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1948 assigned-clock-rates = <100000000>;
1960 clock-names = "pipe0";
1962 #phy-cells = <0>;
1963 clock-output-names = "pcie_1_pipe_clk";
1968 compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
1969 "jedec,ufs-2.0";
1972 reg-names = "std", "ice";
1975 phy-names = "ufsphy";
1976 lanes-per-direction = <2>;
1977 #reset-cells = <1>;
1979 reset-names = "rst";
1983 clock-names =
2003 freq-table-hz =
2018 compatible = "qcom,sm8150-qmp-ufs-phy";
2020 #address-cells = <2>;
2021 #size-cells = <2>;
2023 clock-names = "ref",
2028 power-domains = <&gcc UFS_PHY_GDSC>;
2031 reset-names = "ufsphy";
2040 #phy-cells = <0>;
2045 compatible = "qcom,sm8150-ipa-virt";
2047 #interconnect-cells = <1>;
2048 qcom,bcm-voters = <&apps_bcm_voter>;
2052 compatible = "qcom,tcsr-mutex";
2054 #hwlock-cells = <1>;
2058 compatible = "qcom,sm8150-tcsr", "syscon";
2063 compatible = "qcom,sm8150-slpi-pas";
2066 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
2071 interrupt-names = "wdog", "fatal", "ready",
2072 "handover", "stop-ack";
2075 clock-names = "xo";
2077 power-domains = <&rpmhpd 3>,
2079 power-domain-names = "lcx", "lmx";
2081 memory-region = <&slpi_mem>;
2085 qcom,smem-states = <&slpi_smp2p_out 0>;
2086 qcom,smem-state-names = "stop";
2090 glink-edge {
2093 qcom,remote-pid = <3>;
2098 qcom,glink-channels = "fastrpcglink-apps-dsp";
2100 qcom,non-secure-domain;
2101 #address-cells = <1>;
2102 #size-cells = <0>;
2104 compute-cb@1 {
2105 compatible = "qcom,fastrpc-compute-cb";
2110 compute-cb@2 {
2111 compatible = "qcom,fastrpc-compute-cb";
2116 compute-cb@3 {
2117 compatible = "qcom,fastrpc-compute-cb";
2120 /* note: shared-cb = <4> in downstream */
2132 compatible = "qcom,adreno-640.1",
2137 reg-names = "kgsl_3d0_reg_memory";
2143 operating-points-v2 = <&gpu_opp_table>;
2149 zap-shader {
2150 memory-region = <&gpu_mem>;
2154 gpu_opp_table: opp-table {
2155 compatible = "operating-points-v2";
2157 opp-675000000 {
2158 opp-hz = /bits/ 64 <675000000>;
2159 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2162 opp-585000000 {
2163 opp-hz = /bits/ 64 <585000000>;
2164 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2167 opp-499200000 {
2168 opp-hz = /bits/ 64 <499200000>;
2169 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2172 opp-427000000 {
2173 opp-hz = /bits/ 64 <427000000>;
2174 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2177 opp-345000000 {
2178 opp-hz = /bits/ 64 <345000000>;
2179 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2182 opp-257000000 {
2183 opp-hz = /bits/ 64 <257000000>;
2184 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2190 compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu";
2195 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2199 interrupt-names = "hfi", "gmu";
2206 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2208 power-domains = <&gpucc GPU_CX_GDSC>,
2210 power-domain-names = "cx", "gx";
2214 operating-points-v2 = <&gmu_opp_table>;
2218 gmu_opp_table: opp-table {
2219 compatible = "operating-points-v2";
2221 opp-200000000 {
2222 opp-hz = /bits/ 64 <200000000>;
2223 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2228 gpucc: clock-controller@2c90000 {
2229 compatible = "qcom,sm8150-gpucc";
2234 clock-names = "bi_tcxo",
2237 #clock-cells = <1>;
2238 #reset-cells = <1>;
2239 #power-domain-cells = <1>;
2243 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500";
2245 #iommu-cells = <2>;
2246 #global-interrupts = <1>;
2259 clock-names = "ahb", "bus", "iface";
2261 power-domains = <&gpucc GPU_CX_GDSC>;
2265 compatible = "qcom,sm8150-pinctrl";
2270 reg-names = "west", "east", "north", "south";
2272 gpio-ranges = <&tlmm 0 0 176>;
2273 gpio-controller;
2274 #gpio-cells = <2>;
2275 interrupt-controller;
2276 #interrupt-cells = <2>;
2277 wakeup-parent = <&pdc>;
2279 qup_i2c0_default: qup-i2c0-default {
2287 drive-strength = <0x02>;
2288 bias-disable;
2292 qup_spi0_default: qup-spi0-default {
2295 drive-strength = <6>;
2296 bias-disable;
2299 qup_i2c1_default: qup-i2c1-default {
2307 drive-strength = <0x02>;
2308 bias-disable;
2312 qup_spi1_default: qup-spi1-default {
2315 drive-strength = <6>;
2316 bias-disable;
2319 qup_i2c2_default: qup-i2c2-default {
2327 drive-strength = <0x02>;
2328 bias-disable;
2332 qup_spi2_default: qup-spi2-default {
2335 drive-strength = <6>;
2336 bias-disable;
2339 qup_i2c3_default: qup-i2c3-default {
2347 drive-strength = <0x02>;
2348 bias-disable;
2352 qup_spi3_default: qup-spi3-default {
2355 drive-strength = <6>;
2356 bias-disable;
2359 qup_i2c4_default: qup-i2c4-default {
2367 drive-strength = <0x02>;
2368 bias-disable;
2372 qup_spi4_default: qup-spi4-default {
2375 drive-strength = <6>;
2376 bias-disable;
2379 qup_i2c5_default: qup-i2c5-default {
2387 drive-strength = <0x02>;
2388 bias-disable;
2392 qup_spi5_default: qup-spi5-default {
2395 drive-strength = <6>;
2396 bias-disable;
2399 qup_i2c6_default: qup-i2c6-default {
2407 drive-strength = <0x02>;
2408 bias-disable;
2412 qup_spi6_default: qup-spi6_default {
2415 drive-strength = <6>;
2416 bias-disable;
2419 qup_i2c7_default: qup-i2c7-default {
2427 drive-strength = <0x02>;
2428 bias-disable;
2432 qup_spi7_default: qup-spi7_default {
2435 drive-strength = <6>;
2436 bias-disable;
2439 qup_i2c8_default: qup-i2c8-default {
2447 drive-strength = <0x02>;
2448 bias-disable;
2452 qup_spi8_default: qup-spi8-default {
2455 drive-strength = <6>;
2456 bias-disable;
2459 qup_i2c9_default: qup-i2c9-default {
2467 drive-strength = <0x02>;
2468 bias-disable;
2472 qup_spi9_default: qup-spi9-default {
2475 drive-strength = <6>;
2476 bias-disable;
2479 qup_i2c10_default: qup-i2c10-default {
2487 drive-strength = <0x02>;
2488 bias-disable;
2492 qup_spi10_default: qup-spi10-default {
2495 drive-strength = <6>;
2496 bias-disable;
2499 qup_i2c11_default: qup-i2c11-default {
2507 drive-strength = <0x02>;
2508 bias-disable;
2512 qup_spi11_default: qup-spi11-default {
2515 drive-strength = <6>;
2516 bias-disable;
2519 qup_i2c12_default: qup-i2c12-default {
2527 drive-strength = <0x02>;
2528 bias-disable;
2532 qup_spi12_default: qup-spi12-default {
2535 drive-strength = <6>;
2536 bias-disable;
2539 qup_i2c13_default: qup-i2c13-default {
2547 drive-strength = <0x02>;
2548 bias-disable;
2552 qup_spi13_default: qup-spi13-default {
2555 drive-strength = <6>;
2556 bias-disable;
2559 qup_i2c14_default: qup-i2c14-default {
2567 drive-strength = <0x02>;
2568 bias-disable;
2572 qup_spi14_default: qup-spi14-default {
2575 drive-strength = <6>;
2576 bias-disable;
2579 qup_i2c15_default: qup-i2c15-default {
2587 drive-strength = <0x02>;
2588 bias-disable;
2592 qup_spi15_default: qup-spi15-default {
2595 drive-strength = <6>;
2596 bias-disable;
2599 qup_i2c16_default: qup-i2c16-default {
2607 drive-strength = <0x02>;
2608 bias-disable;
2612 qup_spi16_default: qup-spi16-default {
2615 drive-strength = <6>;
2616 bias-disable;
2619 qup_i2c17_default: qup-i2c17-default {
2627 drive-strength = <0x02>;
2628 bias-disable;
2632 qup_spi17_default: qup-spi17-default {
2635 drive-strength = <6>;
2636 bias-disable;
2639 qup_i2c18_default: qup-i2c18-default {
2647 drive-strength = <0x02>;
2648 bias-disable;
2652 qup_spi18_default: qup-spi18-default {
2655 drive-strength = <6>;
2656 bias-disable;
2659 qup_i2c19_default: qup-i2c19-default {
2667 drive-strength = <0x02>;
2668 bias-disable;
2672 qup_spi19_default: qup-spi19-default {
2675 drive-strength = <6>;
2676 bias-disable;
2679 pcie0_default_state: pcie0-default {
2683 drive-strength = <2>;
2684 bias-pull-down;
2690 drive-strength = <2>;
2691 bias-pull-up;
2697 drive-strength = <2>;
2698 bias-pull-up;
2702 pcie1_default_state: pcie1-default {
2706 drive-strength = <2>;
2707 bias-pull-down;
2713 drive-strength = <2>;
2714 bias-pull-up;
2720 drive-strength = <2>;
2721 bias-pull-up;
2727 compatible = "qcom,sm8150-mpss-pas";
2730 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2736 interrupt-names = "wdog", "fatal", "ready", "handover",
2737 "stop-ack", "shutdown-ack";
2740 clock-names = "xo";
2742 power-domains = <&rpmhpd 7>,
2744 power-domain-names = "cx", "mss";
2746 memory-region = <&mpss_mem>;
2750 qcom,smem-states = <&modem_smp2p_out 0>;
2751 qcom,smem-state-names = "stop";
2755 glink-edge {
2758 qcom,remote-pid = <1>;
2764 compatible = "arm,coresight-stm", "arm,primecell";
2767 reg-names = "stm-base", "stm-stimulus-base";
2770 clock-names = "apb_pclk";
2772 out-ports {
2775 remote-endpoint = <&funnel0_in7>;
2782 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2786 clock-names = "apb_pclk";
2788 out-ports {
2791 remote-endpoint = <&merge_funnel_in0>;
2796 in-ports {
2797 #address-cells = <1>;
2798 #size-cells = <0>;
2803 remote-endpoint = <&stm_out>;
2810 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2814 clock-names = "apb_pclk";
2816 out-ports {
2819 remote-endpoint = <&merge_funnel_in1>;
2824 in-ports {
2825 #address-cells = <1>;
2826 #size-cells = <0>;
2831 remote-endpoint = <&swao_replicator_out>;
2838 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2842 clock-names = "apb_pclk";
2844 out-ports {
2847 remote-endpoint = <&merge_funnel_in2>;
2852 in-ports {
2853 #address-cells = <1>;
2854 #size-cells = <0>;
2859 remote-endpoint = <&apss_merge_funnel_out>;
2866 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2870 clock-names = "apb_pclk";
2872 out-ports {
2875 remote-endpoint = <&etf_in>;
2880 in-ports {
2881 #address-cells = <1>;
2882 #size-cells = <0>;
2887 remote-endpoint = <&funnel0_out>;
2894 remote-endpoint = <&funnel1_out>;
2901 remote-endpoint = <&funnel2_out>;
2908 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2912 clock-names = "apb_pclk";
2914 out-ports {
2915 #address-cells = <1>;
2916 #size-cells = <0>;
2921 remote-endpoint = <&etr_in>;
2928 remote-endpoint = <&replicator1_in>;
2933 in-ports {
2936 remote-endpoint = <&etf_out>;
2943 compatible = "arm,coresight-tmc", "arm,primecell";
2947 clock-names = "apb_pclk";
2949 out-ports {
2952 remote-endpoint = <&replicator_in0>;
2957 in-ports {
2960 remote-endpoint = <&merge_funnel_out>;
2967 compatible = "arm,coresight-tmc", "arm,primecell";
2972 clock-names = "apb_pclk";
2973 arm,scatter-gather;
2975 in-ports {
2978 remote-endpoint = <&replicator_out0>;
2985 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2989 clock-names = "apb_pclk";
2991 out-ports {
2992 #address-cells = <1>;
2993 #size-cells = <0>;
2998 remote-endpoint = <&swao_funnel_in>;
3003 in-ports {
3004 #address-cells = <1>;
3005 #size-cells = <0>;
3010 remote-endpoint = <&replicator_out1>;
3017 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3021 clock-names = "apb_pclk";
3023 out-ports {
3026 remote-endpoint = <&swao_etf_in>;
3031 in-ports {
3032 #address-cells = <1>;
3033 #size-cells = <0>;
3038 remote-endpoint = <&replicator1_out>;
3045 compatible = "arm,coresight-tmc", "arm,primecell";
3049 clock-names = "apb_pclk";
3051 out-ports {
3054 remote-endpoint = <&swao_replicator_in>;
3059 in-ports {
3062 remote-endpoint = <&swao_funnel_out>;
3069 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3073 clock-names = "apb_pclk";
3074 qcom,replicator-loses-context;
3076 out-ports {
3079 remote-endpoint = <&funnel1_in4>;
3084 in-ports {
3087 remote-endpoint = <&swao_etf_out>;
3094 compatible = "arm,coresight-etm4x", "arm,primecell";
3100 clock-names = "apb_pclk";
3101 arm,coresight-loses-context-with-cpu;
3102 qcom,skip-power-up;
3104 out-ports {
3107 remote-endpoint = <&apss_funnel_in0>;
3114 compatible = "arm,coresight-etm4x", "arm,primecell";
3120 clock-names = "apb_pclk";
3121 arm,coresight-loses-context-with-cpu;
3122 qcom,skip-power-up;
3124 out-ports {
3127 remote-endpoint = <&apss_funnel_in1>;
3134 compatible = "arm,coresight-etm4x", "arm,primecell";
3140 clock-names = "apb_pclk";
3141 arm,coresight-loses-context-with-cpu;
3142 qcom,skip-power-up;
3144 out-ports {
3147 remote-endpoint = <&apss_funnel_in2>;
3154 compatible = "arm,coresight-etm4x", "arm,primecell";
3160 clock-names = "apb_pclk";
3161 arm,coresight-loses-context-with-cpu;
3162 qcom,skip-power-up;
3164 out-ports {
3167 remote-endpoint = <&apss_funnel_in3>;
3174 compatible = "arm,coresight-etm4x", "arm,primecell";
3180 clock-names = "apb_pclk";
3181 arm,coresight-loses-context-with-cpu;
3182 qcom,skip-power-up;
3184 out-ports {
3187 remote-endpoint = <&apss_funnel_in4>;
3194 compatible = "arm,coresight-etm4x", "arm,primecell";
3200 clock-names = "apb_pclk";
3201 arm,coresight-loses-context-with-cpu;
3202 qcom,skip-power-up;
3204 out-ports {
3207 remote-endpoint = <&apss_funnel_in5>;
3214 compatible = "arm,coresight-etm4x", "arm,primecell";
3220 clock-names = "apb_pclk";
3221 arm,coresight-loses-context-with-cpu;
3222 qcom,skip-power-up;
3224 out-ports {
3227 remote-endpoint = <&apss_funnel_in6>;
3234 compatible = "arm,coresight-etm4x", "arm,primecell";
3240 clock-names = "apb_pclk";
3241 arm,coresight-loses-context-with-cpu;
3242 qcom,skip-power-up;
3244 out-ports {
3247 remote-endpoint = <&apss_funnel_in7>;
3254 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3258 clock-names = "apb_pclk";
3260 out-ports {
3263 remote-endpoint = <&apss_merge_funnel_in>;
3268 in-ports {
3269 #address-cells = <1>;
3270 #size-cells = <0>;
3275 remote-endpoint = <&etm0_out>;
3282 remote-endpoint = <&etm1_out>;
3289 remote-endpoint = <&etm2_out>;
3296 remote-endpoint = <&etm3_out>;
3303 remote-endpoint = <&etm4_out>;
3310 remote-endpoint = <&etm5_out>;
3317 remote-endpoint = <&etm6_out>;
3324 remote-endpoint = <&etm7_out>;
3331 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3335 clock-names = "apb_pclk";
3337 out-ports {
3340 remote-endpoint = <&funnel2_in2>;
3345 in-ports {
3348 remote-endpoint = <&apss_funnel_out>;
3355 compatible = "qcom,sm8150-cdsp-pas";
3358 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3363 interrupt-names = "wdog", "fatal", "ready",
3364 "handover", "stop-ack";
3367 clock-names = "xo";
3369 power-domains = <&rpmhpd 7>;
3371 memory-region = <&cdsp_mem>;
3375 qcom,smem-states = <&cdsp_smp2p_out 0>;
3376 qcom,smem-state-names = "stop";
3380 glink-edge {
3383 qcom,remote-pid = <5>;
3388 qcom,glink-channels = "fastrpcglink-apps-dsp";
3390 qcom,non-secure-domain;
3391 #address-cells = <1>;
3392 #size-cells = <0>;
3394 compute-cb@1 {
3395 compatible = "qcom,fastrpc-compute-cb";
3400 compute-cb@2 {
3401 compatible = "qcom,fastrpc-compute-cb";
3406 compute-cb@3 {
3407 compatible = "qcom,fastrpc-compute-cb";
3412 compute-cb@4 {
3413 compatible = "qcom,fastrpc-compute-cb";
3418 compute-cb@5 {
3419 compatible = "qcom,fastrpc-compute-cb";
3424 compute-cb@6 {
3425 compatible = "qcom,fastrpc-compute-cb";
3430 compute-cb@7 {
3431 compatible = "qcom,fastrpc-compute-cb";
3436 compute-cb@8 {
3437 compatible = "qcom,fastrpc-compute-cb";
3448 compatible = "qcom,sm8150-usb-hs-phy",
3449 "qcom,usb-snps-hs-7nm-phy";
3452 #phy-cells = <0>;
3455 clock-names = "ref";
3461 compatible = "qcom,sm8150-usb-hs-phy",
3462 "qcom,usb-snps-hs-7nm-phy";
3465 #phy-cells = <0>;
3468 clock-names = "ref";
3474 compatible = "qcom,sm8150-qmp-usb3-phy";
3478 #address-cells = <2>;
3479 #size-cells = <2>;
3486 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3490 reset-names = "phy", "common";
3499 #clock-cells = <0>;
3500 #phy-cells = <0>;
3502 clock-names = "pipe0";
3503 clock-output-names = "usb3_phy_pipe_clk_src";
3508 compatible = "qcom,sm8150-qmp-usb3-uni-phy";
3511 #address-cells = <2>;
3512 #size-cells = <2>;
3519 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3523 reset-names = "phy", "common";
3530 #clock-cells = <0>;
3531 #phy-cells = <0>;
3533 clock-names = "pipe0";
3534 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3539 compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5";
3544 interrupt-names = "hc_irq", "pwr_irq";
3549 clock-names = "iface", "core", "xo";
3551 qcom,dll-config = <0x0007642c>;
3552 qcom,ddr-config = <0x80040868>;
3553 power-domains = <&rpmhpd 0>;
3554 operating-points-v2 = <&sdhc2_opp_table>;
3558 sdhc2_opp_table: opp-table {
3559 compatible = "operating-points-v2";
3561 opp-19200000 {
3562 opp-hz = /bits/ 64 <19200000>;
3563 required-opps = <&rpmhpd_opp_min_svs>;
3566 opp-50000000 {
3567 opp-hz = /bits/ 64 <50000000>;
3568 required-opps = <&rpmhpd_opp_low_svs>;
3571 opp-100000000 {
3572 opp-hz = /bits/ 64 <100000000>;
3573 required-opps = <&rpmhpd_opp_svs>;
3576 opp-202000000 {
3577 opp-hz = /bits/ 64 <202000000>;
3578 required-opps = <&rpmhpd_opp_svs_l1>;
3584 compatible = "qcom,sm8150-dc-noc";
3586 #interconnect-cells = <1>;
3587 qcom,bcm-voters = <&apps_bcm_voter>;
3591 compatible = "qcom,sm8150-gem-noc";
3593 #interconnect-cells = <1>;
3594 qcom,bcm-voters = <&apps_bcm_voter>;
3598 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3601 #address-cells = <2>;
3602 #size-cells = <2>;
3604 dma-ranges;
3612 clock-names = "cfg_noc",
3619 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3621 assigned-clock-rates = <19200000>, <200000000>;
3627 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3630 power-domains = <&gcc USB30_PRIM_GDSC>;
3642 phy-names = "usb2-phy", "usb3-phy";
3647 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3650 #address-cells = <2>;
3651 #size-cells = <2>;
3653 dma-ranges;
3661 clock-names = "cfg_noc",
3668 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3670 assigned-clock-rates = <19200000>, <200000000>;
3676 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3679 power-domains = <&gcc USB30_SEC_GDSC>;
3691 phy-names = "usb2-phy", "usb3-phy";
3696 compatible = "qcom,sm8150-camnoc-virt";
3698 #interconnect-cells = <1>;
3699 qcom,bcm-voters = <&apps_bcm_voter>;
3702 pdc: interrupt-controller@b220000 {
3703 compatible = "qcom,sm8150-pdc", "qcom,pdc";
3705 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
3707 #interrupt-cells = <2>;
3708 interrupt-parent = <&intc>;
3709 interrupt-controller;
3712 aoss_qmp: power-controller@c300000 {
3713 compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp";
3718 #clock-cells = <0>;
3722 compatible = "qcom,rpmh-stats";
3726 tsens0: thermal-sensor@c263000 {
3727 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
3733 interrupt-names = "uplow", "critical";
3734 #thermal-sensor-cells = <1>;
3737 tsens1: thermal-sensor@c265000 {
3738 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
3744 interrupt-names = "uplow", "critical";
3745 #thermal-sensor-cells = <1>;
3749 compatible = "qcom,spmi-pmic-arb";
3755 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3756 interrupt-names = "periph_irq";
3760 #address-cells = <2>;
3761 #size-cells = <0>;
3762 interrupt-controller;
3763 #interrupt-cells = <4>;
3764 cell-index = <0>;
3768 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500";
3770 #iommu-cells = <2>;
3771 #global-interrupts = <1>;
3856 compatible = "qcom,sm8150-adsp-pas";
3859 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3864 interrupt-names = "wdog", "fatal", "ready",
3865 "handover", "stop-ack";
3868 clock-names = "xo";
3870 power-domains = <&rpmhpd 7>;
3872 memory-region = <&adsp_mem>;
3876 qcom,smem-states = <&adsp_smp2p_out 0>;
3877 qcom,smem-state-names = "stop";
3881 glink-edge {
3884 qcom,remote-pid = <2>;
3889 qcom,glink-channels = "fastrpcglink-apps-dsp";
3891 qcom,non-secure-domain;
3892 #address-cells = <1>;
3893 #size-cells = <0>;
3895 compute-cb@3 {
3896 compatible = "qcom,fastrpc-compute-cb";
3901 compute-cb@4 {
3902 compatible = "qcom,fastrpc-compute-cb";
3907 compute-cb@5 {
3908 compatible = "qcom,fastrpc-compute-cb";
3916 intc: interrupt-controller@17a00000 {
3917 compatible = "arm,gic-v3";
3918 interrupt-controller;
3919 #interrupt-cells = <3>;
3926 compatible = "qcom,sm8150-apss-shared";
3928 #mbox-cells = <1>;
3932 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
3939 #address-cells = <1>;
3940 #size-cells = <1>;
3942 compatible = "arm,armv7-timer-mem";
3944 clock-frequency = <19200000>;
3947 frame-number = <0>;
3955 frame-number = <1>;
3962 frame-number = <2>;
3969 frame-number = <3>;
3976 frame-number = <4>;
3983 frame-number = <5>;
3990 frame-number = <6>;
3999 compatible = "qcom,rpmh-rsc";
4003 reg-names = "drv-0", "drv-1", "drv-2";
4007 qcom,tcs-offset = <0xd00>;
4008 qcom,drv-id = <2>;
4009 qcom,tcs-config = <ACTIVE_TCS 2>,
4014 rpmhcc: clock-controller {
4015 compatible = "qcom,sm8150-rpmh-clk";
4016 #clock-cells = <1>;
4017 clock-names = "xo";
4021 rpmhpd: power-controller {
4022 compatible = "qcom,sm8150-rpmhpd";
4023 #power-domain-cells = <1>;
4024 operating-points-v2 = <&rpmhpd_opp_table>;
4026 rpmhpd_opp_table: opp-table {
4027 compatible = "operating-points-v2";
4030 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4034 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4038 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4042 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4046 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4050 opp-level = <224>;
4054 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4058 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4062 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4066 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4070 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4075 apps_bcm_voter: bcm-voter {
4076 compatible = "qcom,bcm-voter";
4081 compatible = "qcom,sm8150-osm-l3";
4085 clock-names = "xo", "alternate";
4087 #interconnect-cells = <1>;
4091 compatible = "qcom,cpufreq-hw";
4094 reg-names = "freq-domain0", "freq-domain1",
4095 "freq-domain2";
4098 clock-names = "xo", "alternate";
4100 #freq-domain-cells = <1>;
4104 compatible = "qcom,sm8150-lmh";
4108 qcom,lmh-temp-arm-millicelsius = <60000>;
4109 qcom,lmh-temp-low-millicelsius = <84500>;
4110 qcom,lmh-temp-high-millicelsius = <85000>;
4111 interrupt-controller;
4112 #interrupt-cells = <1>;
4116 compatible = "qcom,sm8150-lmh";
4120 qcom,lmh-temp-arm-millicelsius = <60000>;
4121 qcom,lmh-temp-low-millicelsius = <84500>;
4122 qcom,lmh-temp-high-millicelsius = <85000>;
4123 interrupt-controller;
4124 #interrupt-cells = <1>;
4128 compatible = "qcom,wcn3990-wifi";
4130 reg-names = "membase";
4131 memory-region = <&wlan_mem>;
4132 clock-names = "cxo_ref_clk_pin", "qdss";
4152 compatible = "arm,armv8-timer";
4159 thermal-zones {
4160 cpu0-thermal {
4161 polling-delay-passive = <250>;
4162 polling-delay = <1000>;
4164 thermal-sensors = <&tsens0 1>;
4167 cpu0_alert0: trip-point0 {
4173 cpu0_alert1: trip-point1 {
4186 cooling-maps {
4189 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4196 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4204 cpu1-thermal {
4205 polling-delay-passive = <250>;
4206 polling-delay = <1000>;
4208 thermal-sensors = <&tsens0 2>;
4211 cpu1_alert0: trip-point0 {
4217 cpu1_alert1: trip-point1 {
4230 cooling-maps {
4233 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4240 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4248 cpu2-thermal {
4249 polling-delay-passive = <250>;
4250 polling-delay = <1000>;
4252 thermal-sensors = <&tsens0 3>;
4255 cpu2_alert0: trip-point0 {
4261 cpu2_alert1: trip-point1 {
4274 cooling-maps {
4277 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4284 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4292 cpu3-thermal {
4293 polling-delay-passive = <250>;
4294 polling-delay = <1000>;
4296 thermal-sensors = <&tsens0 4>;
4299 cpu3_alert0: trip-point0 {
4305 cpu3_alert1: trip-point1 {
4318 cooling-maps {
4321 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4328 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4336 cpu4-top-thermal {
4337 polling-delay-passive = <250>;
4338 polling-delay = <1000>;
4340 thermal-sensors = <&tsens0 7>;
4343 cpu4_top_alert0: trip-point0 {
4349 cpu4_top_alert1: trip-point1 {
4362 cooling-maps {
4365 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4372 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4380 cpu5-top-thermal {
4381 polling-delay-passive = <250>;
4382 polling-delay = <1000>;
4384 thermal-sensors = <&tsens0 8>;
4387 cpu5_top_alert0: trip-point0 {
4393 cpu5_top_alert1: trip-point1 {
4406 cooling-maps {
4409 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4416 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4424 cpu6-top-thermal {
4425 polling-delay-passive = <250>;
4426 polling-delay = <1000>;
4428 thermal-sensors = <&tsens0 9>;
4431 cpu6_top_alert0: trip-point0 {
4437 cpu6_top_alert1: trip-point1 {
4450 cooling-maps {
4453 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4460 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4468 cpu7-top-thermal {
4469 polling-delay-passive = <250>;
4470 polling-delay = <1000>;
4472 thermal-sensors = <&tsens0 10>;
4475 cpu7_top_alert0: trip-point0 {
4481 cpu7_top_alert1: trip-point1 {
4494 cooling-maps {
4497 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4504 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4512 cpu4-bottom-thermal {
4513 polling-delay-passive = <250>;
4514 polling-delay = <1000>;
4516 thermal-sensors = <&tsens0 11>;
4519 cpu4_bottom_alert0: trip-point0 {
4525 cpu4_bottom_alert1: trip-point1 {
4538 cooling-maps {
4541 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4548 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4556 cpu5-bottom-thermal {
4557 polling-delay-passive = <250>;
4558 polling-delay = <1000>;
4560 thermal-sensors = <&tsens0 12>;
4563 cpu5_bottom_alert0: trip-point0 {
4569 cpu5_bottom_alert1: trip-point1 {
4582 cooling-maps {
4585 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4592 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4600 cpu6-bottom-thermal {
4601 polling-delay-passive = <250>;
4602 polling-delay = <1000>;
4604 thermal-sensors = <&tsens0 13>;
4607 cpu6_bottom_alert0: trip-point0 {
4613 cpu6_bottom_alert1: trip-point1 {
4626 cooling-maps {
4629 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4636 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4644 cpu7-bottom-thermal {
4645 polling-delay-passive = <250>;
4646 polling-delay = <1000>;
4648 thermal-sensors = <&tsens0 14>;
4651 cpu7_bottom_alert0: trip-point0 {
4657 cpu7_bottom_alert1: trip-point1 {
4670 cooling-maps {
4673 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4680 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4688 aoss0-thermal {
4689 polling-delay-passive = <250>;
4690 polling-delay = <1000>;
4692 thermal-sensors = <&tsens0 0>;
4695 aoss0_alert0: trip-point0 {
4703 cluster0-thermal {
4704 polling-delay-passive = <250>;
4705 polling-delay = <1000>;
4707 thermal-sensors = <&tsens0 5>;
4710 cluster0_alert0: trip-point0 {
4723 cluster1-thermal {
4724 polling-delay-passive = <250>;
4725 polling-delay = <1000>;
4727 thermal-sensors = <&tsens0 6>;
4730 cluster1_alert0: trip-point0 {
4743 gpu-top-thermal {
4744 polling-delay-passive = <250>;
4745 polling-delay = <1000>;
4747 thermal-sensors = <&tsens0 15>;
4750 gpu1_alert0: trip-point0 {
4758 aoss1-thermal {
4759 polling-delay-passive = <250>;
4760 polling-delay = <1000>;
4762 thermal-sensors = <&tsens1 0>;
4765 aoss1_alert0: trip-point0 {
4773 wlan-thermal {
4774 polling-delay-passive = <250>;
4775 polling-delay = <1000>;
4777 thermal-sensors = <&tsens1 1>;
4780 wlan_alert0: trip-point0 {
4788 video-thermal {
4789 polling-delay-passive = <250>;
4790 polling-delay = <1000>;
4792 thermal-sensors = <&tsens1 2>;
4795 video_alert0: trip-point0 {
4803 mem-thermal {
4804 polling-delay-passive = <250>;
4805 polling-delay = <1000>;
4807 thermal-sensors = <&tsens1 3>;
4810 mem_alert0: trip-point0 {
4818 q6-hvx-thermal {
4819 polling-delay-passive = <250>;
4820 polling-delay = <1000>;
4822 thermal-sensors = <&tsens1 4>;
4825 q6_hvx_alert0: trip-point0 {
4833 camera-thermal {
4834 polling-delay-passive = <250>;
4835 polling-delay = <1000>;
4837 thermal-sensors = <&tsens1 5>;
4840 camera_alert0: trip-point0 {
4848 compute-thermal {
4849 polling-delay-passive = <250>;
4850 polling-delay = <1000>;
4852 thermal-sensors = <&tsens1 6>;
4855 compute_alert0: trip-point0 {
4863 modem-thermal {
4864 polling-delay-passive = <250>;
4865 polling-delay = <1000>;
4867 thermal-sensors = <&tsens1 7>;
4870 modem_alert0: trip-point0 {
4878 npu-thermal {
4879 polling-delay-passive = <250>;
4880 polling-delay = <1000>;
4882 thermal-sensors = <&tsens1 8>;
4885 npu_alert0: trip-point0 {
4893 modem-vec-thermal {
4894 polling-delay-passive = <250>;
4895 polling-delay = <1000>;
4897 thermal-sensors = <&tsens1 9>;
4900 modem_vec_alert0: trip-point0 {
4908 modem-scl-thermal {
4909 polling-delay-passive = <250>;
4910 polling-delay = <1000>;
4912 thermal-sensors = <&tsens1 10>;
4915 modem_scl_alert0: trip-point0 {
4923 gpu-bottom-thermal {
4924 polling-delay-passive = <250>;
4925 polling-delay = <1000>;
4927 thermal-sensors = <&tsens1 11>;
4930 gpu2_alert0: trip-point0 {