Lines Matching +full:0 +full:x3900000
29 #clock-cells = <0>;
36 #clock-cells = <0>;
44 #size-cells = <0>;
46 CPU0: cpu@0 {
49 reg = <0x0 0x0>;
54 qcom,freq-domain = <&cpufreq_hw 0>;
73 reg = <0x0 0x100>;
78 qcom,freq-domain = <&cpufreq_hw 0>;
95 reg = <0x0 0x200>;
100 qcom,freq-domain = <&cpufreq_hw 0>;
116 reg = <0x0 0x300>;
121 qcom,freq-domain = <&cpufreq_hw 0>;
137 reg = <0x0 0x400>;
158 reg = <0x0 0x500>;
179 reg = <0x0 0x600>;
200 reg = <0x0 0x700>;
257 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
260 arm,psci-suspend-param = <0x40000004>;
267 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
270 arm,psci-suspend-param = <0x40000004>;
279 CLUSTER_SLEEP_0: cluster-sleep-0 {
282 arm,psci-suspend-param = <0x4100c244>;
591 reg = <0x0 0x80000000 0x0 0x0>;
604 #power-domain-cells = <0>;
610 #power-domain-cells = <0>;
616 #power-domain-cells = <0>;
622 #power-domain-cells = <0>;
628 #power-domain-cells = <0>;
634 #power-domain-cells = <0>;
640 #power-domain-cells = <0>;
646 #power-domain-cells = <0>;
652 #power-domain-cells = <0>;
663 reg = <0x0 0x85700000 0x0 0x600000>;
668 reg = <0x0 0x85d00000 0x0 0x140000>;
673 reg = <0x0 0x85f00000 0x0 0x20000>;
679 reg = <0x0 0x85f20000 0x0 0x20000>;
684 reg = <0x0 0x86000000 0x0 0x200000>;
689 reg = <0x0 0x86200000 0x0 0x3900000>;
695 reg = <0x0 0x89b00000 0x0 0x200000>;
703 reg = <0x0 0x8b700000 0x0 0x500000>;
708 reg = <0x0 0x8bc00000 0x0 0x180000>;
713 reg = <0x0 0x8bd80000 0x0 0x80000>;
718 reg = <0x0 0x8be00000 0x0 0x1a00000>;
723 reg = <0x0 0x8d800000 0x0 0x9600000>;
728 reg = <0x0 0x96e00000 0x0 0x500000>;
733 reg = <0x0 0x97300000 0x0 0x1400000>;
738 reg = <0x0 0x98700000 0x0 0x10000>;
743 reg = <0x0 0x98710000 0x0 0x5000>;
748 reg = <0x0 0x98715000 0x0 0x2000>;
753 reg = <0x0 0x98800000 0x0 0x100000>;
758 reg = <0x0 0x98900000 0x0 0x1400000>;
763 reg = <0x0 0x9e400000 0x0 0x1400000>;
782 qcom,local-pid = <0>;
806 qcom,local-pid = <0>;
830 qcom,local-pid = <0>;
854 qcom,local-pid = <0>;
870 soc: soc@0 {
873 ranges = <0 0 0 0 0x10 0>;
874 dma-ranges = <0 0 0 0 0x10 0>;
879 reg = <0x0 0x00100000 0x0 0x1f0000>;
891 reg = <0 0x800000 0 0x60000>;
906 dma-channel-mask = <0xfa>;
907 iommus = <&apps_smmu 0x00d6 0x0>;
914 reg = <0x0 0x00020000 0x0 0x10000>,
915 <0x0 0x00036000 0x0 0x100>;
929 iommus = <&apps_smmu 0x3C0 0x0>;
941 reg = <0x0 0x008c0000 0x0 0x6000>;
945 iommus = <&apps_smmu 0xc3 0x0>;
953 reg = <0 0x00880000 0 0x4000>;
956 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
957 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
960 pinctrl-0 = <&qup_i2c0_default>;
963 #size-cells = <0>;
969 reg = <0 0x880000 0 0x4000>;
973 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
974 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
977 pinctrl-0 = <&qup_spi0_default>;
981 #size-cells = <0>;
987 reg = <0 0x00884000 0 0x4000>;
990 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
994 pinctrl-0 = <&qup_i2c1_default>;
997 #size-cells = <0>;
1003 reg = <0 0x884000 0 0x4000>;
1007 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1011 pinctrl-0 = <&qup_spi1_default>;
1015 #size-cells = <0>;
1021 reg = <0 0x00888000 0 0x4000>;
1024 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1028 pinctrl-0 = <&qup_i2c2_default>;
1031 #size-cells = <0>;
1037 reg = <0 0x888000 0 0x4000>;
1041 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1045 pinctrl-0 = <&qup_spi2_default>;
1049 #size-cells = <0>;
1055 reg = <0 0x0088c000 0 0x4000>;
1058 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1062 pinctrl-0 = <&qup_i2c3_default>;
1065 #size-cells = <0>;
1071 reg = <0 0x88c000 0 0x4000>;
1075 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1079 pinctrl-0 = <&qup_spi3_default>;
1083 #size-cells = <0>;
1089 reg = <0 0x00890000 0 0x4000>;
1092 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1096 pinctrl-0 = <&qup_i2c4_default>;
1099 #size-cells = <0>;
1105 reg = <0 0x890000 0 0x4000>;
1109 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1113 pinctrl-0 = <&qup_spi4_default>;
1117 #size-cells = <0>;
1123 reg = <0 0x00894000 0 0x4000>;
1126 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1130 pinctrl-0 = <&qup_i2c5_default>;
1133 #size-cells = <0>;
1139 reg = <0 0x894000 0 0x4000>;
1143 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1147 pinctrl-0 = <&qup_spi5_default>;
1151 #size-cells = <0>;
1157 reg = <0 0x00898000 0 0x4000>;
1160 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1164 pinctrl-0 = <&qup_i2c6_default>;
1167 #size-cells = <0>;
1173 reg = <0 0x898000 0 0x4000>;
1177 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1181 pinctrl-0 = <&qup_spi6_default>;
1185 #size-cells = <0>;
1191 reg = <0 0x0089c000 0 0x4000>;
1194 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1198 pinctrl-0 = <&qup_i2c7_default>;
1201 #size-cells = <0>;
1207 reg = <0 0x89c000 0 0x4000>;
1211 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1215 pinctrl-0 = <&qup_spi7_default>;
1219 #size-cells = <0>;
1226 reg = <0 0xa00000 0 0x60000>;
1241 dma-channel-mask = <0xfa>;
1242 iommus = <&apps_smmu 0x0616 0x0>;
1249 reg = <0x0 0x00ac0000 0x0 0x6000>;
1253 iommus = <&apps_smmu 0x603 0x0>;
1261 reg = <0 0x00a80000 0 0x4000>;
1264 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1265 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1268 pinctrl-0 = <&qup_i2c8_default>;
1271 #size-cells = <0>;
1277 reg = <0 0xa80000 0 0x4000>;
1281 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1282 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1285 pinctrl-0 = <&qup_spi8_default>;
1289 #size-cells = <0>;
1295 reg = <0 0x00a84000 0 0x4000>;
1298 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1302 pinctrl-0 = <&qup_i2c9_default>;
1305 #size-cells = <0>;
1311 reg = <0 0xa84000 0 0x4000>;
1315 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1319 pinctrl-0 = <&qup_spi9_default>;
1323 #size-cells = <0>;
1329 reg = <0 0x00a88000 0 0x4000>;
1332 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1336 pinctrl-0 = <&qup_i2c10_default>;
1339 #size-cells = <0>;
1345 reg = <0 0xa88000 0 0x4000>;
1349 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1353 pinctrl-0 = <&qup_spi10_default>;
1357 #size-cells = <0>;
1363 reg = <0 0x00a8c000 0 0x4000>;
1366 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1370 pinctrl-0 = <&qup_i2c11_default>;
1373 #size-cells = <0>;
1379 reg = <0 0xa8c000 0 0x4000>;
1383 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1387 pinctrl-0 = <&qup_spi11_default>;
1391 #size-cells = <0>;
1397 reg = <0x0 0x00a90000 0x0 0x4000>;
1406 reg = <0 0x00a90000 0 0x4000>;
1409 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1413 pinctrl-0 = <&qup_i2c12_default>;
1416 #size-cells = <0>;
1422 reg = <0 0xa90000 0 0x4000>;
1426 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1430 pinctrl-0 = <&qup_spi12_default>;
1434 #size-cells = <0>;
1440 reg = <0 0x0094000 0 0x4000>;
1443 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1447 pinctrl-0 = <&qup_i2c16_default>;
1450 #size-cells = <0>;
1456 reg = <0 0xa94000 0 0x4000>;
1460 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1464 pinctrl-0 = <&qup_spi16_default>;
1468 #size-cells = <0>;
1475 reg = <0 0xc00000 0 0x60000>;
1490 dma-channel-mask = <0xfa>;
1491 iommus = <&apps_smmu 0x07b6 0x0>;
1498 reg = <0x0 0x00cc0000 0x0 0x6000>;
1503 iommus = <&apps_smmu 0x7a3 0x0>;
1511 reg = <0 0x00c80000 0 0x4000>;
1514 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1515 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1518 pinctrl-0 = <&qup_i2c17_default>;
1521 #size-cells = <0>;
1527 reg = <0 0xc80000 0 0x4000>;
1531 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1532 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1535 pinctrl-0 = <&qup_spi17_default>;
1539 #size-cells = <0>;
1545 reg = <0 0x00c84000 0 0x4000>;
1548 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1552 pinctrl-0 = <&qup_i2c18_default>;
1555 #size-cells = <0>;
1561 reg = <0 0xc84000 0 0x4000>;
1565 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1569 pinctrl-0 = <&qup_spi18_default>;
1573 #size-cells = <0>;
1579 reg = <0 0x00c88000 0 0x4000>;
1582 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1586 pinctrl-0 = <&qup_i2c19_default>;
1589 #size-cells = <0>;
1595 reg = <0 0xc88000 0 0x4000>;
1599 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1603 pinctrl-0 = <&qup_spi19_default>;
1607 #size-cells = <0>;
1613 reg = <0 0x00c8c000 0 0x4000>;
1616 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1620 pinctrl-0 = <&qup_i2c13_default>;
1623 #size-cells = <0>;
1629 reg = <0 0xc8c000 0 0x4000>;
1633 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1637 pinctrl-0 = <&qup_spi13_default>;
1641 #size-cells = <0>;
1647 reg = <0 0x00c90000 0 0x4000>;
1650 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1654 pinctrl-0 = <&qup_i2c14_default>;
1657 #size-cells = <0>;
1663 reg = <0 0xc90000 0 0x4000>;
1667 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1671 pinctrl-0 = <&qup_spi14_default>;
1675 #size-cells = <0>;
1681 reg = <0 0x00c94000 0 0x4000>;
1684 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1688 pinctrl-0 = <&qup_i2c15_default>;
1691 #size-cells = <0>;
1697 reg = <0 0xc94000 0 0x4000>;
1701 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1705 pinctrl-0 = <&qup_spi15_default>;
1709 #size-cells = <0>;
1716 reg = <0 0x01500000 0 0x7400>;
1723 reg = <0 0x01620000 0 0x19400>;
1730 reg = <0 0x0163a000 0 0x1000>;
1737 reg = <0 0x016e0000 0 0xd080>;
1744 reg = <0 0x01700000 0 0x20000>;
1751 reg = <0 0x01720000 0 0x7000>;
1758 reg = <0 0x01740000 0 0x1c100>;
1765 reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>;
1772 reg = <0 0x01c00000 0 0x3000>,
1773 <0 0x60000000 0 0xf1d>,
1774 <0 0x60000f20 0 0xa8>,
1775 <0 0x60001000 0 0x1000>,
1776 <0 0x60100000 0 0x100000>;
1779 linux,pci-domain = <0>;
1780 bus-range = <0x00 0xff>;
1786 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
1787 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
1792 interrupt-map-mask = <0 0 0 0x7>;
1793 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1794 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1795 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1796 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1813 iommus = <&apps_smmu 0x1d80 0x7f>;
1814 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
1815 <0x100 &apps_smmu 0x1d81 0x1>;
1829 pinctrl-0 = <&pcie0_default_state>;
1836 reg = <0 0x01c06000 0 0x1c0>;
1854 reg = <0 0x1c06200 0 0x170>, /* tx */
1855 <0 0x1c06400 0 0x200>, /* rx */
1856 <0 0x1c06800 0 0x1f0>, /* pcs */
1857 <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */
1861 #phy-cells = <0>;
1868 reg = <0 0x01c08000 0 0x3000>,
1869 <0 0x40000000 0 0xf1d>,
1870 <0 0x40000f20 0 0xa8>,
1871 <0 0x40001000 0 0x1000>,
1872 <0 0x40100000 0 0x100000>;
1876 bus-range = <0x00 0xff>;
1882 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
1883 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1888 interrupt-map-mask = <0 0 0 0x7>;
1889 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1890 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1891 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1892 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1912 iommus = <&apps_smmu 0x1e00 0x7f>;
1913 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
1914 <0x100 &apps_smmu 0x1e01 0x1>;
1928 pinctrl-0 = <&pcie1_default_state>;
1935 reg = <0 0x01c0e000 0 0x1c0>;
1953 reg = <0 0x1c0e200 0 0x170>, /* tx0 */
1954 <0 0x1c0e400 0 0x200>, /* rx0 */
1955 <0 0x1c0ea00 0 0x1f0>, /* pcs */
1956 <0 0x1c0e600 0 0x170>, /* tx1 */
1957 <0 0x1c0e800 0 0x200>, /* rx1 */
1958 <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
1962 #phy-cells = <0>;
1970 reg = <0 0x01d84000 0 0x2500>,
1971 <0 0x01d90000 0 0x8000>;
1981 iommus = <&apps_smmu 0x300 0>;
2005 <0 0>,
2006 <0 0>,
2008 <0 0>,
2009 <0 0>,
2010 <0 0>,
2011 <0 0>,
2012 <0 300000000>;
2019 reg = <0 0x01d87000 0 0x1c0>;
2030 resets = <&ufs_mem_hc 0>;
2035 reg = <0 0x01d87400 0 0x108>,
2036 <0 0x01d87600 0 0x1e0>,
2037 <0 0x01d87c00 0 0x1dc>,
2038 <0 0x01d87800 0 0x108>,
2039 <0 0x01d87a00 0 0x1e0>;
2040 #phy-cells = <0>;
2046 reg = <0 0x01e00000 0 0x1000>;
2053 reg = <0x0 0x01f40000 0x0 0x20000>;
2059 reg = <0x0 0x01f60000 0x0 0x20000>;
2064 reg = <0x0 0x02400000 0x0 0x4040>;
2067 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2085 qcom,smem-states = <&slpi_smp2p_out 0>;
2102 #size-cells = <0>;
2107 iommus = <&apps_smmu 0x05a1 0x0>;
2113 iommus = <&apps_smmu 0x05a2 0x0>;
2119 iommus = <&apps_smmu 0x05a3 0x0>;
2136 reg = <0 0x02c00000 0 0x40000>;
2141 iommus = <&adreno_smmu 0 0x401>;
2192 reg = <0 0x02c6a000 0 0x30000>,
2193 <0 0x0b290000 0 0x10000>,
2194 <0 0x0b490000 0 0x10000>;
2212 iommus = <&adreno_smmu 5 0x400>;
2230 reg = <0 0x02c90000 0 0x9000>;
2244 reg = <0 0x02ca0000 0 0x10000>;
2266 reg = <0x0 0x03100000 0x0 0x300000>,
2267 <0x0 0x03500000 0x0 0x300000>,
2268 <0x0 0x03900000 0x0 0x300000>,
2269 <0x0 0x03D00000 0x0 0x300000>;
2272 gpio-ranges = <&tlmm 0 0 176>;
2287 drive-strength = <0x02>;
2307 drive-strength = <0x02>;
2327 drive-strength = <0x02>;
2347 drive-strength = <0x02>;
2367 drive-strength = <0x02>;
2387 drive-strength = <0x02>;
2407 drive-strength = <0x02>;
2427 drive-strength = <0x02>;
2447 drive-strength = <0x02>;
2467 drive-strength = <0x02>;
2487 drive-strength = <0x02>;
2507 drive-strength = <0x02>;
2527 drive-strength = <0x02>;
2547 drive-strength = <0x02>;
2567 drive-strength = <0x02>;
2587 drive-strength = <0x02>;
2607 drive-strength = <0x02>;
2627 drive-strength = <0x02>;
2647 drive-strength = <0x02>;
2667 drive-strength = <0x02>;
2728 reg = <0x0 0x04080000 0x0 0x4040>;
2731 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2743 <&rpmhpd 0>;
2750 qcom,smem-states = <&modem_smp2p_out 0>;
2765 reg = <0 0x06002000 0 0x1000>,
2766 <0 0x16280000 0 0x180000>;
2783 reg = <0 0x06041000 0 0x1000>;
2798 #size-cells = <0>;
2811 reg = <0 0x06042000 0 0x1000>;
2826 #size-cells = <0>;
2839 reg = <0 0x06043000 0 0x1000>;
2854 #size-cells = <0>;
2867 reg = <0 0x06045000 0 0x1000>;
2882 #size-cells = <0>;
2884 port@0 {
2885 reg = <0>;
2909 reg = <0 0x06046000 0 0x1000>;
2916 #size-cells = <0>;
2918 port@0 {
2919 reg = <0>;
2944 reg = <0 0x06047000 0 0x1000>;
2968 reg = <0 0x06048000 0 0x1000>;
2969 iommus = <&apps_smmu 0x05e0 0x0>;
2986 reg = <0 0x0604a000 0 0x1000>;
2993 #size-cells = <0>;
3005 #size-cells = <0>;
3018 reg = <0 0x06b08000 0 0x1000>;
3033 #size-cells = <0>;
3046 reg = <0 0x06b09000 0 0x1000>;
3070 reg = <0 0x06b0a000 0 0x1000>;
3095 reg = <0 0x07040000 0 0x1000>;
3115 reg = <0 0x07140000 0 0x1000>;
3135 reg = <0 0x07240000 0 0x1000>;
3155 reg = <0 0x07340000 0 0x1000>;
3175 reg = <0 0x07440000 0 0x1000>;
3195 reg = <0 0x07540000 0 0x1000>;
3215 reg = <0 0x07640000 0 0x1000>;
3235 reg = <0 0x07740000 0 0x1000>;
3255 reg = <0 0x07800000 0 0x1000>;
3270 #size-cells = <0>;
3272 port@0 {
3273 reg = <0>;
3332 reg = <0 0x07810000 0 0x1000>;
3356 reg = <0x0 0x08300000 0x0 0x4040>;
3359 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3375 qcom,smem-states = <&cdsp_smp2p_out 0>;
3392 #size-cells = <0>;
3397 iommus = <&apps_smmu 0x1001 0x0460>;
3403 iommus = <&apps_smmu 0x1002 0x0460>;
3409 iommus = <&apps_smmu 0x1003 0x0460>;
3415 iommus = <&apps_smmu 0x1004 0x0460>;
3421 iommus = <&apps_smmu 0x1005 0x0460>;
3427 iommus = <&apps_smmu 0x1006 0x0460>;
3433 iommus = <&apps_smmu 0x1007 0x0460>;
3439 iommus = <&apps_smmu 0x1008 0x0460>;
3450 reg = <0 0x088e2000 0 0x400>;
3452 #phy-cells = <0>;
3463 reg = <0 0x088e3000 0 0x400>;
3465 #phy-cells = <0>;
3475 reg = <0 0x088e9000 0 0x18c>,
3476 <0 0x088e8000 0 0x10>;
3493 reg = <0 0x088e9200 0 0x200>,
3494 <0 0x088e9400 0 0x200>,
3495 <0 0x088e9c00 0 0x218>,
3496 <0 0x088e9600 0 0x200>,
3497 <0 0x088e9800 0 0x200>,
3498 <0 0x088e9a00 0 0x100>;
3499 #clock-cells = <0>;
3500 #phy-cells = <0>;
3509 reg = <0 0x088eb000 0 0x200>;
3526 reg = <0 0x088eb200 0 0x200>,
3527 <0 0x088eb400 0 0x200>,
3528 <0 0x088eb800 0 0x800>,
3529 <0 0x088eb600 0 0x200>;
3530 #clock-cells = <0>;
3531 #phy-cells = <0>;
3540 reg = <0 0x08804000 0 0x1000>;
3550 iommus = <&apps_smmu 0x6a0 0x0>;
3551 qcom,dll-config = <0x0007642c>;
3552 qcom,ddr-config = <0x80040868>;
3553 power-domains = <&rpmhpd 0>;
3585 reg = <0 0x09160000 0 0x3200>;
3592 reg = <0 0x09680000 0 0x3e200>;
3599 reg = <0 0x0a6f8800 0 0x400>;
3636 reg = <0 0x0a600000 0 0xcd00>;
3638 iommus = <&apps_smmu 0x140 0>;
3648 reg = <0 0x0a8f8800 0 0x400>;
3685 reg = <0 0x0a800000 0 0xcd00>;
3687 iommus = <&apps_smmu 0x160 0>;
3697 reg = <0 0x0ac00000 0 0x1000>;
3704 reg = <0 0x0b220000 0 0x400>;
3705 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
3714 reg = <0x0 0x0c300000 0x0 0x400>;
3716 mboxes = <&apss_shared 0>;
3718 #clock-cells = <0>;
3723 reg = <0 0x0c3f0000 0 0x400>;
3728 reg = <0 0x0c263000 0 0x1ff>, /* TM */
3729 <0 0x0c222000 0 0x1ff>; /* SROT */
3739 reg = <0 0x0c265000 0 0x1ff>, /* TM */
3740 <0 0x0c223000 0 0x1ff>; /* SROT */
3750 reg = <0x0 0x0c440000 0x0 0x0001100>,
3751 <0x0 0x0c600000 0x0 0x2000000>,
3752 <0x0 0x0e600000 0x0 0x0100000>,
3753 <0x0 0x0e700000 0x0 0x00a0000>,
3754 <0x0 0x0c40a000 0x0 0x0026000>;
3758 qcom,ee = <0>;
3759 qcom,channel = <0>;
3761 #size-cells = <0>;
3764 cell-index = <0>;
3769 reg = <0 0x15000000 0 0x100000>;
3857 reg = <0x0 0x17300000 0x0 0x4040>;
3860 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3876 qcom,smem-states = <&adsp_smp2p_out 0>;
3893 #size-cells = <0>;
3898 iommus = <&apps_smmu 0x1b23 0x0>;
3904 iommus = <&apps_smmu 0x1b24 0x0>;
3910 iommus = <&apps_smmu 0x1b25 0x0>;
3920 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
3921 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
3927 reg = <0x0 0x17c00000 0x0 0x1000>;
3933 reg = <0 0x17c10000 0 0x1000>;
3935 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
3941 ranges = <0 0 0 0x20000000>;
3943 reg = <0x0 0x17c20000 0x0 0x1000>;
3947 frame-number = <0>;
3950 reg = <0x17c21000 0x1000>,
3951 <0x17c22000 0x1000>;
3957 reg = <0x17c23000 0x1000>;
3964 reg = <0x17c25000 0x1000>;
3971 reg = <0x17c26000 0x1000>;
3978 reg = <0x17c29000 0x1000>;
3985 reg = <0x17c2b000 0x1000>;
3992 reg = <0x17c2d000 0x1000>;
4000 reg = <0x0 0x18200000 0x0 0x10000>,
4001 <0x0 0x18210000 0x0 0x10000>,
4002 <0x0 0x18220000 0x0 0x10000>;
4003 reg-names = "drv-0", "drv-1", "drv-2";
4007 qcom,tcs-offset = <0xd00>;
4082 reg = <0 0x18321000 0 0x1400>;
4092 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>,
4093 <0 0x18327800 0 0x1400>;
4105 reg = <0 0x18350800 0 0x400>;
4117 reg = <0 0x18358800 0 0x400>;
4129 reg = <0 0x18800000 0 0x800000>;
4146 iommus = <&apps_smmu 0x0640 0x1>;
4156 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
4692 thermal-sensors = <&tsens0 0>;
4762 thermal-sensors = <&tsens1 0>;