Lines Matching +full:interrupts +full:- +full:extended
1 // SPDX-License-Identifier: BSD-3-Clause
7 #include <dt-bindings/clock/qcom,gcc-sm6350.h>
8 #include <dt-bindings/clock/qcom,rpmh.h>
9 #include <dt-bindings/dma/qcom-gpi.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interconnect/qcom,sm6350.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/mailbox/qcom-ipcc.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
15 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
18 interrupt-parent = <&intc>;
19 #address-cells = <2>;
20 #size-cells = <2>;
23 xo_board: xo-board {
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-frequency = <76800000>;
27 clock-output-names = "xo_board";
30 sleep_clk: sleep-clk {
31 compatible = "fixed-clock";
32 clock-frequency = <32764>;
33 #clock-cells = <0>;
38 #address-cells = <2>;
39 #size-cells = <0>;
45 enable-method = "psci";
46 capacity-dmips-mhz = <1024>;
47 dynamic-power-coefficient = <100>;
48 next-level-cache = <&L2_0>;
49 qcom,freq-domain = <&cpufreq_hw 0>;
50 #cooling-cells = <2>;
51 L2_0: l2-cache {
53 next-level-cache = <&L3_0>;
54 L3_0: l3-cache {
64 enable-method = "psci";
65 capacity-dmips-mhz = <1024>;
66 dynamic-power-coefficient = <100>;
67 next-level-cache = <&L2_100>;
68 qcom,freq-domain = <&cpufreq_hw 0>;
69 #cooling-cells = <2>;
70 L2_100: l2-cache {
72 next-level-cache = <&L3_0>;
80 enable-method = "psci";
81 capacity-dmips-mhz = <1024>;
82 dynamic-power-coefficient = <100>;
83 next-level-cache = <&L2_200>;
84 qcom,freq-domain = <&cpufreq_hw 0>;
85 #cooling-cells = <2>;
86 L2_200: l2-cache {
88 next-level-cache = <&L3_0>;
96 enable-method = "psci";
97 capacity-dmips-mhz = <1024>;
98 dynamic-power-coefficient = <100>;
99 next-level-cache = <&L2_300>;
100 qcom,freq-domain = <&cpufreq_hw 0>;
101 #cooling-cells = <2>;
102 L2_300: l2-cache {
104 next-level-cache = <&L3_0>;
112 enable-method = "psci";
113 capacity-dmips-mhz = <1024>;
114 dynamic-power-coefficient = <100>;
115 next-level-cache = <&L2_400>;
116 qcom,freq-domain = <&cpufreq_hw 0>;
117 #cooling-cells = <2>;
118 L2_400: l2-cache {
120 next-level-cache = <&L3_0>;
128 enable-method = "psci";
129 capacity-dmips-mhz = <1024>;
130 dynamic-power-coefficient = <100>;
131 next-level-cache = <&L2_500>;
132 qcom,freq-domain = <&cpufreq_hw 0>;
133 #cooling-cells = <2>;
134 L2_500: l2-cache {
136 next-level-cache = <&L3_0>;
145 enable-method = "psci";
146 capacity-dmips-mhz = <1894>;
147 dynamic-power-coefficient = <703>;
148 next-level-cache = <&L2_600>;
149 qcom,freq-domain = <&cpufreq_hw 1>;
150 #cooling-cells = <2>;
151 L2_600: l2-cache {
153 next-level-cache = <&L3_0>;
161 enable-method = "psci";
162 capacity-dmips-mhz = <1894>;
163 dynamic-power-coefficient = <703>;
164 next-level-cache = <&L2_700>;
165 qcom,freq-domain = <&cpufreq_hw 1>;
166 #cooling-cells = <2>;
167 L2_700: l2-cache {
169 next-level-cache = <&L3_0>;
173 cpu-map {
212 compatible = "qcom,scm-sm6350", "qcom,scm";
213 #reset-cells = <1>;
224 compatible = "arm,armv8-pmuv3";
225 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW>;
229 compatible = "arm,psci-1.0";
233 reserved_memory: reserved-memory {
234 #address-cells = <2>;
235 #size-cells = <2>;
240 no-map;
245 no-map;
249 compatible = "qcom,cmd-db";
251 no-map;
256 no-map;
261 no-map;
266 no-map;
271 no-map;
276 no-map;
281 no-map;
286 no-map;
291 no-map;
296 no-map;
301 no-map;
306 no-map;
311 no-map;
316 no-map;
321 no-map;
326 no-map;
331 no-map;
336 no-map;
341 no-map;
345 compatible = "removed-dma-pool", "ramoops";
347 record-size = <0x1000>;
348 console-size = <0x40000>;
349 ftrace-size = <0x0>;
350 msg-size = <0x20000 0x20000>;
351 cc-size = <0x0>;
352 no-map;
357 no-map;
363 memory-region = <&smem_mem>;
367 smp2p-adsp {
370 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
376 qcom,local-pid = <0>;
377 qcom,remote-pid = <2>;
379 smp2p_adsp_out: master-kernel {
380 qcom,entry-name = "master-kernel";
381 #qcom,smem-state-cells = <1>;
384 smp2p_adsp_in: slave-kernel {
385 qcom,entry-name = "slave-kernel";
386 interrupt-controller;
387 #interrupt-cells = <2>;
391 smp2p-cdsp {
394 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
400 qcom,local-pid = <0>;
401 qcom,remote-pid = <5>;
403 smp2p_cdsp_out: master-kernel {
404 qcom,entry-name = "master-kernel";
405 #qcom,smem-state-cells = <1>;
408 smp2p_cdsp_in: slave-kernel {
409 qcom,entry-name = "slave-kernel";
410 interrupt-controller;
411 #interrupt-cells = <2>;
415 smp2p-mpss {
419 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
425 qcom,local-pid = <0>;
426 qcom,remote-pid = <1>;
428 modem_smp2p_out: master-kernel {
429 qcom,entry-name = "master-kernel";
430 #qcom,smem-state-cells = <1>;
433 modem_smp2p_in: slave-kernel {
434 qcom,entry-name = "slave-kernel";
436 interrupt-controller;
437 #interrupt-cells = <2>;
442 #address-cells = <2>;
443 #size-cells = <2>;
445 dma-ranges = <0 0 0 0 0x10 0>;
446 compatible = "simple-bus";
448 gcc: clock-controller@100000 {
449 compatible = "qcom,gcc-sm6350";
451 #clock-cells = <1>;
452 #reset-cells = <1>;
453 #power-domain-cells = <1>;
454 clock-names = "bi_tcxo",
463 compatible = "qcom,sm6350-ipcc", "qcom,ipcc";
465 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
466 interrupt-controller;
467 #interrupt-cells = <3>;
468 #mbox-cells = <2>;
472 compatible = "qcom,prng-ee";
475 clock-names = "core";
479 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5";
483 reg-names = "hc", "cqhci", "ice";
485 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
487 interrupt-names = "hc_irq", "pwr_irq";
492 clock-names = "iface", "core", "xo";
493 qcom,dll-config = <0x000f642c>;
494 qcom,ddr-config = <0x80040868>;
495 power-domains = <&rpmhpd SM6350_CX>;
496 operating-points-v2 = <&sdhc1_opp_table>;
497 bus-width = <8>;
498 non-removable;
499 supports-cqe;
503 sdhc1_opp_table: opp-table {
504 compatible = "operating-points-v2";
506 opp-19200000 {
507 opp-hz = /bits/ 64 <19200000>;
508 required-opps = <&rpmhpd_opp_min_svs>;
511 opp-100000000 {
512 opp-hz = /bits/ 64 <100000000>;
513 required-opps = <&rpmhpd_opp_low_svs>;
516 opp-384000000 {
517 opp-hz = /bits/ 64 <384000000>;
518 required-opps = <&rpmhpd_opp_svs_l1>;
523 gpi_dma0: dma-controller@800000 {
524 compatible = "qcom,sm6350-gpi-dma";
526 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
536 dma-channels = <10>;
537 dma-channel-mask = <0x1f>;
539 #dma-cells = <3>;
544 compatible = "qcom,geni-se-qup";
546 clock-names = "m-ahb", "s-ahb";
549 #address-cells = <2>;
550 #size-cells = <2>;
556 compatible = "qcom,geni-i2c";
558 clock-names = "se";
560 pinctrl-names = "default";
561 pinctrl-0 = <&qup_i2c0_default>;
562 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
565 dma-names = "tx", "rx";
566 #address-cells = <1>;
567 #size-cells = <0>;
571 interconnect-names = "qup-core", "qup-config", "qup-memory";
576 compatible = "qcom,geni-i2c";
578 clock-names = "se";
580 pinctrl-names = "default";
581 pinctrl-0 = <&qup_i2c2_default>;
582 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
585 dma-names = "tx", "rx";
586 #address-cells = <1>;
587 #size-cells = <0>;
591 interconnect-names = "qup-core", "qup-config", "qup-memory";
596 gpi_dma1: dma-controller@900000 {
597 compatible = "qcom,sm6350-gpi-dma";
599 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH>,
609 dma-channels = <10>;
610 dma-channel-mask = <0x3f>;
612 #dma-cells = <3>;
617 compatible = "qcom,geni-se-qup";
619 clock-names = "m-ahb", "s-ahb";
622 #address-cells = <2>;
623 #size-cells = <2>;
629 compatible = "qcom,geni-i2c";
631 clock-names = "se";
633 pinctrl-names = "default";
634 pinctrl-0 = <&qup_i2c6_default>;
635 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
638 dma-names = "tx", "rx";
639 #address-cells = <1>;
640 #size-cells = <0>;
644 interconnect-names = "qup-core", "qup-config", "qup-memory";
649 compatible = "qcom,geni-i2c";
651 clock-names = "se";
653 pinctrl-names = "default";
654 pinctrl-0 = <&qup_i2c7_default>;
655 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
658 dma-names = "tx", "rx";
659 #address-cells = <1>;
660 #size-cells = <0>;
664 interconnect-names = "qup-core", "qup-config", "qup-memory";
669 compatible = "qcom,geni-i2c";
671 clock-names = "se";
673 pinctrl-names = "default";
674 pinctrl-0 = <&qup_i2c8_default>;
675 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
678 dma-names = "tx", "rx";
679 #address-cells = <1>;
680 #size-cells = <0>;
684 interconnect-names = "qup-core", "qup-config", "qup-memory";
689 compatible = "qcom,geni-debug-uart";
691 clock-names = "se";
693 pinctrl-names = "default";
694 pinctrl-0 = <&qup_uart9_default>;
695 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
698 interconnect-names = "qup-core", "qup-config";
703 compatible = "qcom,geni-i2c";
705 clock-names = "se";
707 pinctrl-names = "default";
708 pinctrl-0 = <&qup_i2c10_default>;
709 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
712 dma-names = "tx", "rx";
713 #address-cells = <1>;
714 #size-cells = <0>;
718 interconnect-names = "qup-core", "qup-config", "qup-memory";
725 compatible = "qcom,sm6350-config-noc";
727 #interconnect-cells = <2>;
728 qcom,bcm-voters = <&apps_bcm_voter>;
732 compatible = "qcom,sm6350-system-noc";
734 #interconnect-cells = <2>;
735 qcom,bcm-voters = <&apps_bcm_voter>;
737 clk_virt: interconnect-clk-virt {
738 compatible = "qcom,sm6350-clk-virt";
739 #interconnect-cells = <2>;
740 qcom,bcm-voters = <&apps_bcm_voter>;
745 compatible = "qcom,sm6350-aggre1-noc";
747 #interconnect-cells = <2>;
748 qcom,bcm-voters = <&apps_bcm_voter>;
752 compatible = "qcom,sm6350-aggre2-noc";
754 #interconnect-cells = <2>;
755 qcom,bcm-voters = <&apps_bcm_voter>;
757 compute_noc: interconnect-compute-noc {
758 compatible = "qcom,sm6350-compute-noc";
759 #interconnect-cells = <2>;
760 qcom,bcm-voters = <&apps_bcm_voter>;
765 compatible = "qcom,sm6350-mmss-noc";
767 #interconnect-cells = <2>;
768 qcom,bcm-voters = <&apps_bcm_voter>;
772 compatible = "qcom,sm6350-ufshc", "qcom,ufshc",
773 "jedec,ufs-2.0";
776 reg-names = "std", "ice";
777 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
779 phy-names = "ufsphy";
780 lanes-per-direction = <2>;
781 #reset-cells = <1>;
783 reset-names = "rst";
785 power-domains = <&gcc UFS_PHY_GDSC>;
789 clock-names = "core_clk",
807 freq-table-hz =
822 compatible = "qcom,sm6350-qmp-ufs-phy";
824 #address-cells = <2>;
825 #size-cells = <2>;
828 clock-names = "ref",
834 reset-names = "ufsphy";
844 #phy-cells = <0>;
849 compatible = "qcom,tcsr-mutex";
851 #hwlock-cells = <1>;
855 compatible = "qcom,sm6350-adsp-pas";
858 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
863 interrupt-names = "wdog", "fatal", "ready",
864 "handover", "stop-ack";
867 clock-names = "xo";
869 power-domains = <&rpmhpd SM6350_LCX>,
871 power-domain-names = "lcx", "lmx";
873 memory-region = <&pil_adsp_mem>;
877 qcom,smem-states = <&smp2p_adsp_out 0>;
878 qcom,smem-state-names = "stop";
882 glink-edge {
883 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
890 qcom,remote-pid = <2>;
894 qcom,glink-channels = "fastrpcglink-apps-dsp";
896 #address-cells = <1>;
897 #size-cells = <0>;
899 compute-cb@3 {
900 compatible = "qcom,fastrpc-compute-cb";
905 compute-cb@4 {
906 compatible = "qcom,fastrpc-compute-cb";
911 compute-cb@5 {
912 compatible = "qcom,fastrpc-compute-cb";
922 compatible = "qcom,sm6350-mpss-pas";
925 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
931 interrupt-names = "wdog", "fatal", "ready", "handover",
932 "stop-ack", "shutdown-ack";
935 clock-names = "xo";
937 power-domains = <&rpmhpd SM6350_CX>,
939 power-domain-names = "cx", "mss";
941 memory-region = <&pil_modem_mem>;
945 qcom,smem-states = <&modem_smp2p_out 0>;
946 qcom,smem-state-names = "stop";
950 glink-edge {
951 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
957 qcom,remote-pid = <1>;
962 compatible = "qcom,sm6350-cdsp-pas";
965 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
970 interrupt-names = "wdog", "fatal", "ready",
971 "handover", "stop-ack";
974 clock-names = "xo";
976 power-domains = <&rpmhpd SM6350_CX>,
978 power-domain-names = "cx", "mx";
980 memory-region = <&pil_cdsp_mem>;
984 qcom,smem-states = <&smp2p_cdsp_out 0>;
985 qcom,smem-state-names = "stop";
989 glink-edge {
990 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
997 qcom,remote-pid = <5>;
1001 qcom,glink-channels = "fastrpcglink-apps-dsp";
1003 #address-cells = <1>;
1004 #size-cells = <0>;
1006 compute-cb@1 {
1007 compatible = "qcom,fastrpc-compute-cb";
1012 compute-cb@2 {
1013 compatible = "qcom,fastrpc-compute-cb";
1018 compute-cb@3 {
1019 compatible = "qcom,fastrpc-compute-cb";
1024 compute-cb@4 {
1025 compatible = "qcom,fastrpc-compute-cb";
1030 compute-cb@5 {
1031 compatible = "qcom,fastrpc-compute-cb";
1036 compute-cb@6 {
1037 compatible = "qcom,fastrpc-compute-cb";
1042 compute-cb@7 {
1043 compatible = "qcom,fastrpc-compute-cb";
1048 compute-cb@8 {
1049 compatible = "qcom,fastrpc-compute-cb";
1060 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5";
1063 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
1065 interrupt-names = "hc_irq", "pwr_irq";
1070 clock-names = "iface", "core", "xo";
1073 interconnect-names = "sdhc-ddr", "cpu-sdhc";
1075 qcom,dll-config = <0x0007642c>;
1076 qcom,ddr-config = <0x80040868>;
1077 power-domains = <&rpmhpd SM6350_CX>;
1078 operating-points-v2 = <&sdhc2_opp_table>;
1079 bus-width = <4>;
1083 sdhc2_opp_table: opp-table {
1084 compatible = "operating-points-v2";
1086 opp-100000000 {
1087 opp-hz = /bits/ 64 <100000000>;
1088 required-opps = <&rpmhpd_opp_svs_l1>;
1089 opp-peak-kBps = <790000 131000>;
1090 opp-avg-kBps = <50000 50000>;
1093 opp-202000000 {
1094 opp-hz = /bits/ 64 <202000000>;
1095 required-opps = <&rpmhpd_opp_nom>;
1096 opp-peak-kBps = <3190000 294000>;
1097 opp-avg-kBps = <261438 300000>;
1103 compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy";
1106 #phy-cells = <0>;
1109 clock-names = "cfg_ahb", "ref";
1115 compatible = "qcom,sc7180-qmp-usb3-dp-phy";
1120 #address-cells = <2>;
1121 #size-cells = <2>;
1128 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
1132 reset-names = "phy", "common";
1134 usb_1_ssphy: usb3-phy@88e9200 {
1141 #clock-cells = <0>;
1142 #phy-cells = <0>;
1144 clock-names = "pipe0";
1145 clock-output-names = "usb3_phy_pipe_clk_src";
1148 dp_phy: dp-phy@88ea200 {
1155 #phy-cells = <0>;
1156 #clock-cells = <1>;
1158 clock-names = "pipe0";
1159 clock-output-names = "usb3_phy_pipe_clk_src";
1164 compatible = "qcom,sm6350-dc-noc";
1166 #interconnect-cells = <2>;
1167 qcom,bcm-voters = <&apps_bcm_voter>;
1170 system-cache-controller@9200000 {
1171 compatible = "qcom,sm6350-llcc";
1173 reg-names = "llcc_base", "llcc_broadcast_base";
1177 compatible = "qcom,sm6350-gem-noc";
1179 #interconnect-cells = <2>;
1180 qcom,bcm-voters = <&apps_bcm_voter>;
1184 compatible = "qcom,sm6350-npu-noc";
1186 #interconnect-cells = <2>;
1187 qcom,bcm-voters = <&apps_bcm_voter>;
1191 compatible = "qcom,sm6350-dwc3", "qcom,dwc3";
1194 #address-cells = <2>;
1195 #size-cells = <2>;
1203 clock-names = "cfg_noc",
1209 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
1214 interrupt-names = "hs_phy_irq", "ss_phy_irq",
1217 power-domains = <&gcc USB30_PRIM_GDSC>;
1223 interconnect-names = "usb-ddr", "apps-usb";
1228 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
1232 snps,has-lpm-erratum;
1233 snps,hird-threshold = /bits/ 8 <0x10>;
1235 phy-names = "usb2-phy", "usb3-phy";
1239 pdc: interrupt-controller@b220000 {
1240 compatible = "qcom,sm6350-pdc", "qcom,pdc";
1242 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
1244 #interrupt-cells = <2>;
1245 interrupt-parent = <&intc>;
1246 interrupt-controller;
1249 tsens0: thermal-sensor@c263000 {
1250 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2";
1254 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
1256 interrupt-names = "uplow", "critical";
1257 #thermal-sensor-cells = <1>;
1260 tsens1: thermal-sensor@c265000 {
1261 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2";
1265 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
1267 interrupt-names = "uplow", "critical";
1268 #thermal-sensor-cells = <1>;
1271 aoss_qmp: power-controller@c300000 {
1272 compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp";
1274 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
1278 #clock-cells = <0>;
1282 compatible = "qcom,spmi-pmic-arb";
1288 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1289 interrupt-names = "periph_irq";
1290 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
1293 #address-cells = <2>;
1294 #size-cells = <0>;
1295 interrupt-controller;
1296 #interrupt-cells = <4>;
1300 compatible = "qcom,sm6350-tlmm";
1302 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
1311 gpio-controller;
1312 #gpio-cells = <2>;
1313 interrupt-controller;
1314 #interrupt-cells = <2>;
1315 gpio-ranges = <&tlmm 0 0 157>;
1317 qup_uart9_default: qup-uart9-default-state {
1320 drive-strength = <2>;
1321 bias-disable;
1324 qup_i2c0_default: qup-i2c0-default-state {
1327 drive-strength = <2>;
1328 bias-pull-up;
1331 qup_i2c2_default: qup-i2c2-default-state {
1334 drive-strength = <2>;
1335 bias-pull-up;
1338 qup_i2c6_default: qup-i2c6-default-state {
1341 drive-strength = <2>;
1342 bias-pull-up;
1345 qup_i2c7_default: qup-i2c7-default-state {
1348 drive-strength = <2>;
1349 bias-pull-up;
1352 qup_i2c8_default: qup-i2c8-default-state {
1355 drive-strength = <2>;
1356 bias-pull-up;
1359 qup_i2c10_default: qup-i2c10-default-state {
1362 drive-strength = <2>;
1363 bias-pull-up;
1368 compatible = "qcom,sm6350-smmu-500", "arm,mmu-500";
1370 #iommu-cells = <2>;
1371 #global-interrupts = <1>;
1372 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1455 intc: interrupt-controller@17a00000 {
1456 compatible = "arm,gic-v3";
1457 #interrupt-cells = <3>;
1458 interrupt-controller;
1461 interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>;
1465 compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt";
1468 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
1472 compatible = "arm,armv7-timer-mem";
1474 clock-frequency = <19200000>;
1475 #address-cells = <1>;
1476 #size-cells = <1>;
1480 frame-number = <0>;
1481 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1488 frame-number = <1>;
1489 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1495 frame-number = <2>;
1496 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1502 frame-number = <3>;
1503 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1509 frame-number = <4>;
1510 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1516 frame-number = <5>;
1517 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1523 frame-number = <6>;
1524 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1531 compatible = "qcom,wcn3990-wifi";
1533 reg-names = "membase";
1534 memory-region = <&wlan_fw_mem>;
1535 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
1548 qcom,msa-fixed-perm;
1553 compatible = "qcom,rpmh-rsc";
1558 reg-names = "drv-0", "drv-1", "drv-2";
1559 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
1562 qcom,tcs-offset = <0xd00>;
1563 qcom,drv-id = <2>;
1564 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
1567 rpmhcc: clock-controller {
1568 compatible = "qcom,sm6350-rpmh-clk";
1569 #clock-cells = <1>;
1570 clock-names = "xo";
1574 rpmhpd: power-controller {
1575 compatible = "qcom,sm6350-rpmhpd";
1576 #power-domain-cells = <1>;
1577 operating-points-v2 = <&rpmhpd_opp_table>;
1579 rpmhpd_opp_table: opp-table {
1580 compatible = "operating-points-v2";
1583 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1587 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1591 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1595 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1599 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1603 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1607 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1611 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
1615 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1619 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1624 apps_bcm_voter: bcm-voter {
1625 compatible = "qcom,bcm-voter";
1630 compatible = "qcom,cpufreq-hw";
1632 reg-names = "freq-domain0", "freq-domain1";
1634 clock-names = "xo", "alternate";
1636 #freq-domain-cells = <1>;
1641 compatible = "arm,armv8-timer";
1642 clock-frequency = <19200000>;
1643 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,