Lines Matching +full:0 +full:x00880000
25 #clock-cells = <0>;
33 #clock-cells = <0>;
39 #size-cells = <0>;
41 CPU0: cpu@0 {
44 reg = <0x0 0x0>;
49 qcom,freq-domain = <&cpufreq_hw 0>;
63 reg = <0x0 0x100>;
68 qcom,freq-domain = <&cpufreq_hw 0>;
79 reg = <0x0 0x200>;
84 qcom,freq-domain = <&cpufreq_hw 0>;
95 reg = <0x0 0x300>;
100 qcom,freq-domain = <&cpufreq_hw 0>;
111 reg = <0x0 0x400>;
116 qcom,freq-domain = <&cpufreq_hw 0>;
127 reg = <0x0 0x500>;
132 qcom,freq-domain = <&cpufreq_hw 0>;
144 reg = <0x0 0x600>;
160 reg = <0x0 0x700>;
220 reg = <0x0 0x80000000 0x0 0x0>;
239 reg = <0 0x80000000 0 0x600000>;
244 reg = <0 0x80700000 0 0x160000>;
250 reg = <0 0x80860000 0 0x20000>;
255 reg = <0 0x808ff000 0 0x1000>;
260 reg = <0 0x80900000 0 0x200000>;
265 reg = <0 0x80b00000 0 0x1e00000>;
270 reg = <0 0x86000000 0 0x500000>;
275 reg = <0 0x86500000 0 0x500000>;
280 reg = <0 0x86a00000 0 0x500000>;
285 reg = <0 0x86f00000 0 0x1e00000>;
290 reg = <0 0x88d00000 0 0x2800000>;
295 reg = <0 0x8b500000 0 0x200000>;
300 reg = <0 0x8b700000 0 0x10000>;
305 reg = <0 0x8b710000 0 0x5400>;
310 reg = <0 0x8b715400 0 0x2000>;
315 reg = <0 0x8b800000 0 0xf800000>;
320 reg = <0 0xa0000000 0 0x2300000>;
325 reg = <0 0xa2300000 0 0x100000>;
330 reg = <0 0xc0000000 0 0x3900000>;
335 reg = <0 0xffb00000 0 0xc0000>;
340 reg = <0 0xffbc0000 0 0x40000>;
346 reg = <0 0xffc00000 0 0x00100000>;
347 record-size = <0x1000>;
348 console-size = <0x40000>;
349 ftrace-size = <0x0>;
350 msg-size = <0x20000 0x20000>;
351 cc-size = <0x0>;
356 reg = <0 0xffd00000 0 0x1000>;
376 qcom,local-pid = <0>;
400 qcom,local-pid = <0>;
425 qcom,local-pid = <0>;
441 soc: soc@0 {
444 ranges = <0 0 0 0 0x10 0>;
445 dma-ranges = <0 0 0 0 0x10 0>;
450 reg = <0 0x00100000 0 0x1f0000>;
464 reg = <0 0x00408000 0 0x1000>;
473 reg = <0 0x00793000 0 0x1000>;
480 reg = <0 0x007c4000 0 0x1000>,
481 <0 0x007c5000 0 0x1000>,
482 <0 0x007c8000 0 0x8000>;
493 qcom,dll-config = <0x000f642c>;
494 qcom,ddr-config = <0x80040868>;
525 reg = <0 0x00800000 0 0x60000>;
537 dma-channel-mask = <0x1f>;
538 iommus = <&apps_smmu 0x56 0x0>;
545 reg = <0x0 0x8c0000 0x0 0x2000>;
551 iommus = <&apps_smmu 0x43 0x0>;
557 reg = <0 0x00880000 0 0x4000>;
561 pinctrl-0 = <&qup_i2c0_default>;
563 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
564 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
567 #size-cells = <0>;
568 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
569 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
570 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>;
577 reg = <0 0x00888000 0 0x4000>;
581 pinctrl-0 = <&qup_i2c2_default>;
583 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
587 #size-cells = <0>;
588 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
589 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
590 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>;
598 reg = <0 0x00900000 0 0x60000>;
610 dma-channel-mask = <0x3f>;
611 iommus = <&apps_smmu 0x4d6 0x0>;
618 reg = <0x0 0x9c0000 0x0 0x2000>;
624 iommus = <&apps_smmu 0x4c3 0x0>;
630 reg = <0 0x00980000 0 0x4000>;
634 pinctrl-0 = <&qup_i2c6_default>;
636 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
637 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
640 #size-cells = <0>;
641 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
642 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
643 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
650 reg = <0 0x00984000 0 0x4000>;
654 pinctrl-0 = <&qup_i2c7_default>;
656 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
660 #size-cells = <0>;
661 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
662 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
663 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
670 reg = <0 0x00988000 0 0x4000>;
674 pinctrl-0 = <&qup_i2c8_default>;
676 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
680 #size-cells = <0>;
681 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
682 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
683 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
690 reg = <0 0x98c000 0 0x4000>;
694 pinctrl-0 = <&qup_uart9_default>;
696 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
697 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
704 reg = <0 0x00990000 0 0x4000>;
708 pinctrl-0 = <&qup_i2c10_default>;
710 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
714 #size-cells = <0>;
715 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
716 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
717 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
726 reg = <0 0x01500000 0 0x28000>;
733 reg = <0 0x01620000 0 0x17080>;
746 reg = <0 0x016e0000 0 0x15080>;
753 reg = <0 0x01700000 0 0x1f880>;
766 reg = <0 0x01740000 0 0x1c100>;
774 reg = <0 0x01d84000 0 0x3000>,
775 <0 0x01d90000 0 0x8000>;
787 iommus = <&apps_smmu 0x80 0x0>;
809 <0 0>,
810 <0 0>,
813 <0 0>,
814 <0 0>,
815 <0 0>,
816 <0 0>;
823 reg = <0 0x01d87000 0 0x18c>;
833 resets = <&ufs_mem_hc 0>;
839 reg = <0 0x01d87400 0 0x128>,
840 <0 0x01d87600 0 0x1fc>,
841 <0 0x01d87c00 0 0x1dc>,
842 <0 0x01d87800 0 0x128>,
843 <0 0x01d87a00 0 0x1fc>;
844 #phy-cells = <0>;
850 reg = <0x0 0x01f40000 0x0 0x40000>;
856 reg = <0 0x03000000 0 0x100>;
859 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
877 qcom,smem-states = <&smp2p_adsp_out 0>;
897 #size-cells = <0>;
902 iommus = <&apps_smmu 0x1003 0x0>;
908 iommus = <&apps_smmu 0x1004 0x0>;
914 iommus = <&apps_smmu 0x1005 0x0>;
923 reg = <0x0 0x04080000 0x0 0x4040>;
926 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
945 qcom,smem-states = <&modem_smp2p_out 0>;
963 reg = <0 0x08300000 0 0x10000>;
966 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
984 qcom,smem-states = <&smp2p_cdsp_out 0>;
1004 #size-cells = <0>;
1009 iommus = <&apps_smmu 0x1401 0x20>;
1015 iommus = <&apps_smmu 0x1402 0x20>;
1021 iommus = <&apps_smmu 0x1403 0x20>;
1027 iommus = <&apps_smmu 0x1404 0x20>;
1033 iommus = <&apps_smmu 0x1405 0x20>;
1039 iommus = <&apps_smmu 0x1406 0x20>;
1045 iommus = <&apps_smmu 0x1407 0x20>;
1051 iommus = <&apps_smmu 0x1408 0x20>;
1061 reg = <0 0x08804000 0 0x1000>;
1071 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &clk_virt SLAVE_EBI_CH0 0>,
1072 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>;
1075 qcom,dll-config = <0x0007642c>;
1076 qcom,ddr-config = <0x80040868>;
1104 reg = <0 0x088e3000 0 0x400>;
1106 #phy-cells = <0>;
1116 reg = <0 0x088e9000 0 0x200>,
1117 <0 0x088e8000 0 0x40>,
1118 <0 0x088ea000 0 0x200>;
1135 reg = <0 0x088e9200 0 0x200>,
1136 <0 0x088e9400 0 0x200>,
1137 <0 0x088e9c00 0 0x400>,
1138 <0 0x088e9600 0 0x200>,
1139 <0 0x088e9800 0 0x200>,
1140 <0 0x088e9a00 0 0x100>;
1141 #clock-cells = <0>;
1142 #phy-cells = <0>;
1149 reg = <0 0x088ea200 0 0x200>,
1150 <0 0x088ea400 0 0x200>,
1151 <0 0x088eac00 0 0x400>,
1152 <0 0x088ea600 0 0x200>,
1153 <0 0x088ea800 0 0x200>,
1154 <0 0x088eaa00 0 0x100>;
1155 #phy-cells = <0>;
1165 reg = <0 0x09160000 0 0x3200>;
1172 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
1178 reg = <0 0x09680000 0 0x3e200>;
1185 reg = <0 0x09990000 0 0x1600>;
1192 reg = <0 0x0a6f8800 0 0x400>;
1221 interconnects = <&aggre2_noc MASTER_USB3 0 &clk_virt SLAVE_EBI_CH0 0>,
1222 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
1227 reg = <0 0x0a600000 0 0xcd00>;
1229 iommus = <&apps_smmu 0x540 0x0>;
1233 snps,hird-threshold = /bits/ 8 <0x10>;
1241 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>;
1242 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
1251 reg = <0 0x0c263000 0 0x1ff>, /* TM */
1252 <0 0x0c222000 0 0x8>; /* SROT */
1262 reg = <0 0x0c265000 0 0x1ff>, /* TM */
1263 <0 0x0c223000 0 0x8>; /* SROT */
1273 reg = <0 0x0c300000 0 0x1000>;
1278 #clock-cells = <0>;
1283 reg = <0 0xc440000 0 0x1100>,
1284 <0 0xc600000 0 0x2000000>,
1285 <0 0xe600000 0 0x100000>,
1286 <0 0xe700000 0 0xa0000>,
1287 <0 0xc40a000 0 0x26000>;
1291 qcom,ee = <0>;
1292 qcom,channel = <0>;
1294 #size-cells = <0>;
1301 reg = <0 0x0f100000 0 0x300000>;
1315 gpio-ranges = <&tlmm 0 0 157>;
1369 reg = <0 0x15000000 0 0x100000>;
1459 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
1460 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
1466 reg = <0 0x17c10000 0 0x1000>;
1468 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
1473 reg = <0x0 0x17c20000 0x0 0x1000>;
1477 ranges = <0 0 0 0x20000000>;
1480 frame-number = <0>;
1483 reg = <0x17c21000 0x1000>,
1484 <0x17c22000 0x1000>;
1490 reg = <0x17c23000 0x1000>;
1497 reg = <0x17c25000 0x1000>;
1504 reg = <0x17c27000 0x1000>;
1511 reg = <0x17c29000 0x1000>;
1518 reg = <0x17c2b000 0x1000>;
1525 reg = <0x17c2d000 0x1000>;
1532 reg = <0 0x18800000 0 0x800000>;
1547 iommus = <&apps_smmu 0x20 0x1>;
1555 reg = <0x0 0x18200000 0x0 0x10000>,
1556 <0x0 0x18210000 0x0 0x10000>,
1557 <0x0 0x18220000 0x0 0x10000>;
1558 reg-names = "drv-0", "drv-1", "drv-2";
1562 qcom,tcs-offset = <0xd00>;
1631 reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>;
1646 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;