Lines Matching +full:spmi +full:- +full:pmic +full:- +full:arb
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,gcc-sm6125.h>
7 #include <dt-bindings/clock/qcom,rpmcc.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/qcom-rpmpd.h>
13 interrupt-parent = <&intc>;
14 #address-cells = <2>;
15 #size-cells = <2>;
20 xo_board: xo-board {
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
23 clock-frequency = <19200000>;
24 clock-output-names = "xo_board";
27 sleep_clk: sleep-clk {
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <32000>;
31 clock-output-names = "sleep_clk";
36 #address-cells = <2>;
37 #size-cells = <0>;
43 enable-method = "psci";
44 capacity-dmips-mhz = <1024>;
45 next-level-cache = <&L2_0>;
46 L2_0: l2-cache {
55 enable-method = "psci";
56 capacity-dmips-mhz = <1024>;
57 next-level-cache = <&L2_0>;
64 enable-method = "psci";
65 capacity-dmips-mhz = <1024>;
66 next-level-cache = <&L2_0>;
73 enable-method = "psci";
74 capacity-dmips-mhz = <1024>;
75 next-level-cache = <&L2_0>;
82 enable-method = "psci";
83 capacity-dmips-mhz = <1638>;
84 next-level-cache = <&L2_1>;
85 L2_1: l2-cache {
94 enable-method = "psci";
95 capacity-dmips-mhz = <1638>;
96 next-level-cache = <&L2_1>;
103 enable-method = "psci";
104 capacity-dmips-mhz = <1638>;
105 next-level-cache = <&L2_1>;
112 enable-method = "psci";
113 capacity-dmips-mhz = <1638>;
114 next-level-cache = <&L2_1>;
117 cpu-map {
158 compatible = "qcom,scm-sm6125", "qcom,scm";
159 #reset-cells = <1>;
170 compatible = "arm,armv8-pmuv3";
175 compatible = "arm,psci-1.0";
179 reserved_memory: reserved-memory {
180 #address-cells = <2>;
181 #size-cells = <2>;
186 no-map;
191 no-map;
196 no-map;
201 no-map;
206 no-map;
211 no-map;
216 no-map;
221 no-map;
226 no-map;
231 no-map;
236 no-map;
241 no-map;
246 no-map;
251 no-map;
256 no-map;
261 no-map;
266 no-map;
271 no-map;
276 no-map;
281 no-map;
286 no-map;
290 rpm-glink {
291 compatible = "qcom,glink-rpm";
294 qcom,rpm-msg-ram = <&rpm_msg_ram>;
297 rpm_requests: rpm-requests {
298 compatible = "qcom,rpm-sm6125";
299 qcom,glink-channels = "rpm_requests";
301 rpmcc: clock-controller {
302 compatible = "qcom,rpmcc-sm6125", "qcom,rpmcc";
303 #clock-cells = <1>;
306 rpmpd: power-controller {
307 compatible = "qcom,sm6125-rpmpd";
308 #power-domain-cells = <1>;
309 operating-points-v2 = <&rpmpd_opp_table>;
311 rpmpd_opp_table: opp-table {
312 compatible = "operating-points-v2";
315 opp-level = <RPM_SMD_LEVEL_RETENTION>;
319 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
323 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
327 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
331 opp-level = <RPM_SMD_LEVEL_SVS>;
335 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
339 opp-level = <RPM_SMD_LEVEL_NOM>;
343 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
347 opp-level = <RPM_SMD_LEVEL_TURBO>;
351 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
360 memory-region = <&smem_mem>;
365 #address-cells = <1>;
366 #size-cells = <1>;
368 compatible = "simple-bus";
371 compatible = "qcom,tcsr-mutex";
373 #hwlock-cells = <1>;
377 compatible = "qcom,sm6125-tlmm";
381 reg-names = "west", "south", "east";
383 gpio-controller;
384 gpio-ranges = <&tlmm 0 0 134>;
385 #gpio-cells = <2>;
386 interrupt-controller;
387 #interrupt-cells = <2>;
389 sdc2_off_state: sdc2-off-state {
390 clk-pins {
392 drive-strength = <2>;
393 bias-disable;
396 cmd-pins {
398 drive-strength = <2>;
399 bias-pull-up;
402 data-pins {
404 drive-strength = <2>;
405 bias-pull-up;
409 sdc2_on_state: sdc2-on-state {
412 drive-strength = <16>;
413 bias-disable;
416 cmd-pins-pins {
418 drive-strength = <10>;
419 bias-pull-up;
422 data-pins {
424 drive-strength = <10>;
425 bias-pull-up;
430 gcc: clock-controller@1400000 {
431 compatible = "qcom,gcc-sm6125";
433 #clock-cells = <1>;
434 #reset-cells = <1>;
435 #power-domain-cells = <1>;
436 clock-names = "bi_tcxo", "sleep_clk";
441 compatible = "qcom,msm8996-qusb2-phy";
443 #phy-cells = <0>;
447 clock-names = "ref", "cfg_ahb";
454 compatible = "qcom,rpm-msg-ram";
459 compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
461 reg-names = "hc", "core";
465 interrupt-names = "hc_irq", "pwr_irq";
470 clock-names = "iface", "core", "xo";
472 power-domains = <&rpmpd SM6125_VDDCX>;
474 qcom,dll-config = <0x000f642c>;
475 qcom,ddr-config = <0x80040873>;
477 bus-width = <8>;
478 non-removable;
483 compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
485 reg-names = "hc";
489 interrupt-names = "hc_irq", "pwr_irq";
494 clock-names = "iface", "core", "xo";
496 pinctrl-0 = <&sdc2_on_state>;
497 pinctrl-1 = <&sdc2_off_state>;
498 pinctrl-names = "default", "sleep";
500 power-domains = <&rpmpd SM6125_VDDCX>;
502 qcom,dll-config = <0x0007642c>;
503 qcom,ddr-config = <0x80040873>;
505 bus-width = <4>;
510 compatible = "qcom,sm6125-dwc3", "qcom,dwc3";
512 #address-cells = <1>;
513 #size-cells = <1>;
522 clock-names = "cfg_noc",
529 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
531 assigned-clock-rates = <19200000>, <66666667>;
533 power-domains = <&gcc USB30_PRIM_GDSC>;
534 qcom,select-utmi-as-pipe-clk;
542 phy-names = "usb2-phy";
545 maximum-speed = "high-speed";
551 compatible = "qcom,rpm-stats";
555 spmi_bus: spmi@1c40000 {
556 compatible = "qcom,spmi-pmic-arb";
562 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
563 interrupt-names = "periph_irq";
567 #address-cells = <2>;
568 #size-cells = <0>;
569 interrupt-controller;
570 #interrupt-cells = <4>;
571 cell-index = <0>;
575 compatible = "qcom,sm6125-apcs-hmss-global";
578 #mbox-cells = <1>;
582 compatible = "arm,armv7-timer-mem";
583 #address-cells = <1>;
584 #size-cells = <1>;
587 clock-frequency = <19200000>;
590 frame-number = <0>;
598 frame-number = <1>;
605 frame-number = <2>;
612 frame-number = <3>;
619 frame-number = <4>;
626 frame-number = <5>;
633 frame-number = <6>;
640 intc: interrupt-controller@f200000 {
641 compatible = "arm,gic-v3";
644 #interrupt-cells = <3>;
645 interrupt-controller;
651 compatible = "arm,armv8-timer";
656 clock-frequency = <19200000>;