Lines Matching +full:apr +full:- +full:v2
1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
12 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
15 #include <dt-bindings/dma/qcom-gpi.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interconnect/qcom,osm-l3.h>
18 #include <dt-bindings/interconnect/qcom,sdm845.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 #include <dt-bindings/phy/phy-qcom-qusb2.h>
21 #include <dt-bindings/power/qcom-rpmpd.h>
22 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
23 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
24 #include <dt-bindings/soc/qcom,apr.h>
25 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
26 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
27 #include <dt-bindings/thermal/thermal.h>
30 interrupt-parent = <&intc>;
32 #address-cells = <2>;
33 #size-cells = <2>;
78 reserved-memory {
79 #address-cells = <2>;
80 #size-cells = <2>;
83 hyp_mem: hyp-mem@85700000 {
85 no-map;
88 xbl_mem: xbl-mem@85e00000 {
90 no-map;
93 aop_mem: aop-mem@85fc0000 {
95 no-map;
98 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 {
99 compatible = "qcom,cmd-db";
101 no-map;
107 no-map;
113 no-map;
117 compatible = "qcom,rmtfs-mem";
119 no-map;
121 qcom,client-id = <1>;
127 no-map;
130 camera_mem: camera-mem@8bf00000 {
132 no-map;
135 ipa_fw_mem: ipa-fw@8c400000 {
137 no-map;
140 ipa_gsi_mem: ipa-gsi@8c410000 {
142 no-map;
147 no-map;
152 no-map;
155 wlan_msa_mem: wlan-msa@8df00000 {
157 no-map;
162 no-map;
167 no-map;
172 no-map;
177 no-map;
182 no-map;
187 no-map;
192 #address-cells = <2>;
193 #size-cells = <0>;
199 enable-method = "psci";
200 capacity-dmips-mhz = <611>;
201 dynamic-power-coefficient = <290>;
202 qcom,freq-domain = <&cpufreq_hw 0>;
203 operating-points-v2 = <&cpu0_opp_table>;
206 power-domains = <&CPU_PD0>;
207 power-domain-names = "psci";
208 #cooling-cells = <2>;
209 next-level-cache = <&L2_0>;
210 L2_0: l2-cache {
212 next-level-cache = <&L3_0>;
213 L3_0: l3-cache {
223 enable-method = "psci";
224 capacity-dmips-mhz = <611>;
225 dynamic-power-coefficient = <290>;
226 qcom,freq-domain = <&cpufreq_hw 0>;
227 operating-points-v2 = <&cpu0_opp_table>;
230 power-domains = <&CPU_PD1>;
231 power-domain-names = "psci";
232 #cooling-cells = <2>;
233 next-level-cache = <&L2_100>;
234 L2_100: l2-cache {
236 next-level-cache = <&L3_0>;
244 enable-method = "psci";
245 capacity-dmips-mhz = <611>;
246 dynamic-power-coefficient = <290>;
247 qcom,freq-domain = <&cpufreq_hw 0>;
248 operating-points-v2 = <&cpu0_opp_table>;
251 power-domains = <&CPU_PD2>;
252 power-domain-names = "psci";
253 #cooling-cells = <2>;
254 next-level-cache = <&L2_200>;
255 L2_200: l2-cache {
257 next-level-cache = <&L3_0>;
265 enable-method = "psci";
266 capacity-dmips-mhz = <611>;
267 dynamic-power-coefficient = <290>;
268 qcom,freq-domain = <&cpufreq_hw 0>;
269 operating-points-v2 = <&cpu0_opp_table>;
272 #cooling-cells = <2>;
273 power-domains = <&CPU_PD3>;
274 power-domain-names = "psci";
275 next-level-cache = <&L2_300>;
276 L2_300: l2-cache {
278 next-level-cache = <&L3_0>;
286 enable-method = "psci";
287 capacity-dmips-mhz = <1024>;
288 dynamic-power-coefficient = <442>;
289 qcom,freq-domain = <&cpufreq_hw 1>;
290 operating-points-v2 = <&cpu4_opp_table>;
293 power-domains = <&CPU_PD4>;
294 power-domain-names = "psci";
295 #cooling-cells = <2>;
296 next-level-cache = <&L2_400>;
297 L2_400: l2-cache {
299 next-level-cache = <&L3_0>;
307 enable-method = "psci";
308 capacity-dmips-mhz = <1024>;
309 dynamic-power-coefficient = <442>;
310 qcom,freq-domain = <&cpufreq_hw 1>;
311 operating-points-v2 = <&cpu4_opp_table>;
314 power-domains = <&CPU_PD5>;
315 power-domain-names = "psci";
316 #cooling-cells = <2>;
317 next-level-cache = <&L2_500>;
318 L2_500: l2-cache {
320 next-level-cache = <&L3_0>;
328 enable-method = "psci";
329 capacity-dmips-mhz = <1024>;
330 dynamic-power-coefficient = <442>;
331 qcom,freq-domain = <&cpufreq_hw 1>;
332 operating-points-v2 = <&cpu4_opp_table>;
335 power-domains = <&CPU_PD6>;
336 power-domain-names = "psci";
337 #cooling-cells = <2>;
338 next-level-cache = <&L2_600>;
339 L2_600: l2-cache {
341 next-level-cache = <&L3_0>;
349 enable-method = "psci";
350 capacity-dmips-mhz = <1024>;
351 dynamic-power-coefficient = <442>;
352 qcom,freq-domain = <&cpufreq_hw 1>;
353 operating-points-v2 = <&cpu4_opp_table>;
356 power-domains = <&CPU_PD7>;
357 power-domain-names = "psci";
358 #cooling-cells = <2>;
359 next-level-cache = <&L2_700>;
360 L2_700: l2-cache {
362 next-level-cache = <&L3_0>;
366 cpu-map {
402 cpu_idle_states: idle-states {
403 entry-method = "psci";
405 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
406 compatible = "arm,idle-state";
407 idle-state-name = "little-rail-power-collapse";
408 arm,psci-suspend-param = <0x40000004>;
409 entry-latency-us = <350>;
410 exit-latency-us = <461>;
411 min-residency-us = <1890>;
412 local-timer-stop;
415 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
416 compatible = "arm,idle-state";
417 idle-state-name = "big-rail-power-collapse";
418 arm,psci-suspend-param = <0x40000004>;
419 entry-latency-us = <264>;
420 exit-latency-us = <621>;
421 min-residency-us = <952>;
422 local-timer-stop;
426 domain-idle-states {
427 CLUSTER_SLEEP_0: cluster-sleep-0 {
428 compatible = "domain-idle-state";
429 idle-state-name = "cluster-power-collapse";
430 arm,psci-suspend-param = <0x4100c244>;
431 entry-latency-us = <3263>;
432 exit-latency-us = <6562>;
433 min-residency-us = <9987>;
434 local-timer-stop;
439 cpu0_opp_table: opp-table-cpu0 {
440 compatible = "operating-points-v2";
441 opp-shared;
443 cpu0_opp1: opp-300000000 {
444 opp-hz = /bits/ 64 <300000000>;
445 opp-peak-kBps = <800000 4800000>;
448 cpu0_opp2: opp-403200000 {
449 opp-hz = /bits/ 64 <403200000>;
450 opp-peak-kBps = <800000 4800000>;
453 cpu0_opp3: opp-480000000 {
454 opp-hz = /bits/ 64 <480000000>;
455 opp-peak-kBps = <800000 6451200>;
458 cpu0_opp4: opp-576000000 {
459 opp-hz = /bits/ 64 <576000000>;
460 opp-peak-kBps = <800000 6451200>;
463 cpu0_opp5: opp-652800000 {
464 opp-hz = /bits/ 64 <652800000>;
465 opp-peak-kBps = <800000 7680000>;
468 cpu0_opp6: opp-748800000 {
469 opp-hz = /bits/ 64 <748800000>;
470 opp-peak-kBps = <1804000 9216000>;
473 cpu0_opp7: opp-825600000 {
474 opp-hz = /bits/ 64 <825600000>;
475 opp-peak-kBps = <1804000 9216000>;
478 cpu0_opp8: opp-902400000 {
479 opp-hz = /bits/ 64 <902400000>;
480 opp-peak-kBps = <1804000 10444800>;
483 cpu0_opp9: opp-979200000 {
484 opp-hz = /bits/ 64 <979200000>;
485 opp-peak-kBps = <1804000 11980800>;
488 cpu0_opp10: opp-1056000000 {
489 opp-hz = /bits/ 64 <1056000000>;
490 opp-peak-kBps = <1804000 11980800>;
493 cpu0_opp11: opp-1132800000 {
494 opp-hz = /bits/ 64 <1132800000>;
495 opp-peak-kBps = <2188000 13516800>;
498 cpu0_opp12: opp-1228800000 {
499 opp-hz = /bits/ 64 <1228800000>;
500 opp-peak-kBps = <2188000 15052800>;
503 cpu0_opp13: opp-1324800000 {
504 opp-hz = /bits/ 64 <1324800000>;
505 opp-peak-kBps = <2188000 16588800>;
508 cpu0_opp14: opp-1420800000 {
509 opp-hz = /bits/ 64 <1420800000>;
510 opp-peak-kBps = <3072000 18124800>;
513 cpu0_opp15: opp-1516800000 {
514 opp-hz = /bits/ 64 <1516800000>;
515 opp-peak-kBps = <3072000 19353600>;
518 cpu0_opp16: opp-1612800000 {
519 opp-hz = /bits/ 64 <1612800000>;
520 opp-peak-kBps = <4068000 19353600>;
523 cpu0_opp17: opp-1689600000 {
524 opp-hz = /bits/ 64 <1689600000>;
525 opp-peak-kBps = <4068000 20889600>;
528 cpu0_opp18: opp-1766400000 {
529 opp-hz = /bits/ 64 <1766400000>;
530 opp-peak-kBps = <4068000 22425600>;
534 cpu4_opp_table: opp-table-cpu4 {
535 compatible = "operating-points-v2";
536 opp-shared;
538 cpu4_opp1: opp-300000000 {
539 opp-hz = /bits/ 64 <300000000>;
540 opp-peak-kBps = <800000 4800000>;
543 cpu4_opp2: opp-403200000 {
544 opp-hz = /bits/ 64 <403200000>;
545 opp-peak-kBps = <800000 4800000>;
548 cpu4_opp3: opp-480000000 {
549 opp-hz = /bits/ 64 <480000000>;
550 opp-peak-kBps = <1804000 4800000>;
553 cpu4_opp4: opp-576000000 {
554 opp-hz = /bits/ 64 <576000000>;
555 opp-peak-kBps = <1804000 4800000>;
558 cpu4_opp5: opp-652800000 {
559 opp-hz = /bits/ 64 <652800000>;
560 opp-peak-kBps = <1804000 4800000>;
563 cpu4_opp6: opp-748800000 {
564 opp-hz = /bits/ 64 <748800000>;
565 opp-peak-kBps = <1804000 4800000>;
568 cpu4_opp7: opp-825600000 {
569 opp-hz = /bits/ 64 <825600000>;
570 opp-peak-kBps = <2188000 9216000>;
573 cpu4_opp8: opp-902400000 {
574 opp-hz = /bits/ 64 <902400000>;
575 opp-peak-kBps = <2188000 9216000>;
578 cpu4_opp9: opp-979200000 {
579 opp-hz = /bits/ 64 <979200000>;
580 opp-peak-kBps = <2188000 9216000>;
583 cpu4_opp10: opp-1056000000 {
584 opp-hz = /bits/ 64 <1056000000>;
585 opp-peak-kBps = <3072000 9216000>;
588 cpu4_opp11: opp-1132800000 {
589 opp-hz = /bits/ 64 <1132800000>;
590 opp-peak-kBps = <3072000 11980800>;
593 cpu4_opp12: opp-1209600000 {
594 opp-hz = /bits/ 64 <1209600000>;
595 opp-peak-kBps = <4068000 11980800>;
598 cpu4_opp13: opp-1286400000 {
599 opp-hz = /bits/ 64 <1286400000>;
600 opp-peak-kBps = <4068000 11980800>;
603 cpu4_opp14: opp-1363200000 {
604 opp-hz = /bits/ 64 <1363200000>;
605 opp-peak-kBps = <4068000 15052800>;
608 cpu4_opp15: opp-1459200000 {
609 opp-hz = /bits/ 64 <1459200000>;
610 opp-peak-kBps = <4068000 15052800>;
613 cpu4_opp16: opp-1536000000 {
614 opp-hz = /bits/ 64 <1536000000>;
615 opp-peak-kBps = <5412000 15052800>;
618 cpu4_opp17: opp-1612800000 {
619 opp-hz = /bits/ 64 <1612800000>;
620 opp-peak-kBps = <5412000 15052800>;
623 cpu4_opp18: opp-1689600000 {
624 opp-hz = /bits/ 64 <1689600000>;
625 opp-peak-kBps = <5412000 19353600>;
628 cpu4_opp19: opp-1766400000 {
629 opp-hz = /bits/ 64 <1766400000>;
630 opp-peak-kBps = <6220000 19353600>;
633 cpu4_opp20: opp-1843200000 {
634 opp-hz = /bits/ 64 <1843200000>;
635 opp-peak-kBps = <6220000 19353600>;
638 cpu4_opp21: opp-1920000000 {
639 opp-hz = /bits/ 64 <1920000000>;
640 opp-peak-kBps = <7216000 19353600>;
643 cpu4_opp22: opp-1996800000 {
644 opp-hz = /bits/ 64 <1996800000>;
645 opp-peak-kBps = <7216000 20889600>;
648 cpu4_opp23: opp-2092800000 {
649 opp-hz = /bits/ 64 <2092800000>;
650 opp-peak-kBps = <7216000 20889600>;
653 cpu4_opp24: opp-2169600000 {
654 opp-hz = /bits/ 64 <2169600000>;
655 opp-peak-kBps = <7216000 20889600>;
658 cpu4_opp25: opp-2246400000 {
659 opp-hz = /bits/ 64 <2246400000>;
660 opp-peak-kBps = <7216000 20889600>;
663 cpu4_opp26: opp-2323200000 {
664 opp-hz = /bits/ 64 <2323200000>;
665 opp-peak-kBps = <7216000 20889600>;
668 cpu4_opp27: opp-2400000000 {
669 opp-hz = /bits/ 64 <2400000000>;
670 opp-peak-kBps = <7216000 22425600>;
673 cpu4_opp28: opp-2476800000 {
674 opp-hz = /bits/ 64 <2476800000>;
675 opp-peak-kBps = <7216000 22425600>;
678 cpu4_opp29: opp-2553600000 {
679 opp-hz = /bits/ 64 <2553600000>;
680 opp-peak-kBps = <7216000 22425600>;
683 cpu4_opp30: opp-2649600000 {
684 opp-hz = /bits/ 64 <2649600000>;
685 opp-peak-kBps = <7216000 22425600>;
688 cpu4_opp31: opp-2745600000 {
689 opp-hz = /bits/ 64 <2745600000>;
690 opp-peak-kBps = <7216000 25497600>;
693 cpu4_opp32: opp-2803200000 {
694 opp-hz = /bits/ 64 <2803200000>;
695 opp-peak-kBps = <7216000 25497600>;
700 compatible = "arm,armv8-pmuv3";
705 compatible = "arm,armv8-timer";
713 xo_board: xo-board {
714 compatible = "fixed-clock";
715 #clock-cells = <0>;
716 clock-frequency = <38400000>;
717 clock-output-names = "xo_board";
720 sleep_clk: sleep-clk {
721 compatible = "fixed-clock";
722 #clock-cells = <0>;
723 clock-frequency = <32764>;
729 compatible = "qcom,scm-sdm845", "qcom,scm";
733 adsp_pas: remoteproc-adsp {
734 compatible = "qcom,sdm845-adsp-pas";
736 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
741 interrupt-names = "wdog", "fatal", "ready",
742 "handover", "stop-ack";
745 clock-names = "xo";
747 memory-region = <&adsp_mem>;
751 qcom,smem-states = <&adsp_smp2p_out 0>;
752 qcom,smem-state-names = "stop";
756 glink-edge {
759 qcom,remote-pid = <2>;
762 apr {
763 compatible = "qcom,apr-v2";
764 qcom,glink-channels = "apr_audio_svc";
766 #address-cells = <1>;
767 #size-cells = <0>;
770 apr-service@3 {
773 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
776 q6afe: apr-service@4 {
779 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
781 compatible = "qcom,q6afe-dais";
782 #address-cells = <1>;
783 #size-cells = <0>;
784 #sound-dai-cells = <1>;
788 q6asm: apr-service@7 {
791 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
793 compatible = "qcom,q6asm-dais";
794 #address-cells = <1>;
795 #size-cells = <0>;
796 #sound-dai-cells = <1>;
801 q6adm: apr-service@8 {
804 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
806 compatible = "qcom,q6adm-routing";
807 #sound-dai-cells = <0>;
814 qcom,glink-channels = "fastrpcglink-apps-dsp";
816 qcom,non-secure-domain;
817 #address-cells = <1>;
818 #size-cells = <0>;
820 compute-cb@3 {
821 compatible = "qcom,fastrpc-compute-cb";
826 compute-cb@4 {
827 compatible = "qcom,fastrpc-compute-cb";
835 cdsp_pas: remoteproc-cdsp {
836 compatible = "qcom,sdm845-cdsp-pas";
838 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
843 interrupt-names = "wdog", "fatal", "ready",
844 "handover", "stop-ack";
847 clock-names = "xo";
849 memory-region = <&cdsp_mem>;
853 qcom,smem-states = <&cdsp_smp2p_out 0>;
854 qcom,smem-state-names = "stop";
858 glink-edge {
861 qcom,remote-pid = <5>;
865 qcom,glink-channels = "fastrpcglink-apps-dsp";
867 qcom,non-secure-domain;
868 #address-cells = <1>;
869 #size-cells = <0>;
871 compute-cb@1 {
872 compatible = "qcom,fastrpc-compute-cb";
877 compute-cb@2 {
878 compatible = "qcom,fastrpc-compute-cb";
883 compute-cb@3 {
884 compatible = "qcom,fastrpc-compute-cb";
889 compute-cb@4 {
890 compatible = "qcom,fastrpc-compute-cb";
895 compute-cb@5 {
896 compatible = "qcom,fastrpc-compute-cb";
901 compute-cb@6 {
902 compatible = "qcom,fastrpc-compute-cb";
907 compute-cb@7 {
908 compatible = "qcom,fastrpc-compute-cb";
913 compute-cb@8 {
914 compatible = "qcom,fastrpc-compute-cb";
922 smp2p-cdsp {
930 qcom,local-pid = <0>;
931 qcom,remote-pid = <5>;
933 cdsp_smp2p_out: master-kernel {
934 qcom,entry-name = "master-kernel";
935 #qcom,smem-state-cells = <1>;
938 cdsp_smp2p_in: slave-kernel {
939 qcom,entry-name = "slave-kernel";
941 interrupt-controller;
942 #interrupt-cells = <2>;
946 smp2p-lpass {
954 qcom,local-pid = <0>;
955 qcom,remote-pid = <2>;
957 adsp_smp2p_out: master-kernel {
958 qcom,entry-name = "master-kernel";
959 #qcom,smem-state-cells = <1>;
962 adsp_smp2p_in: slave-kernel {
963 qcom,entry-name = "slave-kernel";
965 interrupt-controller;
966 #interrupt-cells = <2>;
970 smp2p-mpss {
975 qcom,local-pid = <0>;
976 qcom,remote-pid = <1>;
978 modem_smp2p_out: master-kernel {
979 qcom,entry-name = "master-kernel";
980 #qcom,smem-state-cells = <1>;
983 modem_smp2p_in: slave-kernel {
984 qcom,entry-name = "slave-kernel";
985 interrupt-controller;
986 #interrupt-cells = <2>;
989 ipa_smp2p_out: ipa-ap-to-modem {
990 qcom,entry-name = "ipa";
991 #qcom,smem-state-cells = <1>;
994 ipa_smp2p_in: ipa-modem-to-ap {
995 qcom,entry-name = "ipa";
996 interrupt-controller;
997 #interrupt-cells = <2>;
1001 smp2p-slpi {
1006 qcom,local-pid = <0>;
1007 qcom,remote-pid = <3>;
1009 slpi_smp2p_out: master-kernel {
1010 qcom,entry-name = "master-kernel";
1011 #qcom,smem-state-cells = <1>;
1014 slpi_smp2p_in: slave-kernel {
1015 qcom,entry-name = "slave-kernel";
1016 interrupt-controller;
1017 #interrupt-cells = <2>;
1022 compatible = "arm,psci-1.0";
1025 CPU_PD0: power-domain-cpu0 {
1026 #power-domain-cells = <0>;
1027 power-domains = <&CLUSTER_PD>;
1028 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
1031 CPU_PD1: power-domain-cpu1 {
1032 #power-domain-cells = <0>;
1033 power-domains = <&CLUSTER_PD>;
1034 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
1037 CPU_PD2: power-domain-cpu2 {
1038 #power-domain-cells = <0>;
1039 power-domains = <&CLUSTER_PD>;
1040 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
1043 CPU_PD3: power-domain-cpu3 {
1044 #power-domain-cells = <0>;
1045 power-domains = <&CLUSTER_PD>;
1046 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
1049 CPU_PD4: power-domain-cpu4 {
1050 #power-domain-cells = <0>;
1051 power-domains = <&CLUSTER_PD>;
1052 domain-idle-states = <&BIG_CPU_SLEEP_0>;
1055 CPU_PD5: power-domain-cpu5 {
1056 #power-domain-cells = <0>;
1057 power-domains = <&CLUSTER_PD>;
1058 domain-idle-states = <&BIG_CPU_SLEEP_0>;
1061 CPU_PD6: power-domain-cpu6 {
1062 #power-domain-cells = <0>;
1063 power-domains = <&CLUSTER_PD>;
1064 domain-idle-states = <&BIG_CPU_SLEEP_0>;
1067 CPU_PD7: power-domain-cpu7 {
1068 #power-domain-cells = <0>;
1069 power-domains = <&CLUSTER_PD>;
1070 domain-idle-states = <&BIG_CPU_SLEEP_0>;
1073 CLUSTER_PD: power-domain-cluster {
1074 #power-domain-cells = <0>;
1075 domain-idle-states = <&CLUSTER_SLEEP_0>;
1080 #address-cells = <2>;
1081 #size-cells = <2>;
1083 dma-ranges = <0 0 0 0 0x10 0>;
1084 compatible = "simple-bus";
1086 gcc: clock-controller@100000 {
1087 compatible = "qcom,gcc-sdm845";
1094 clock-names = "bi_tcxo",
1099 #clock-cells = <1>;
1100 #reset-cells = <1>;
1101 #power-domain-cells = <1>;
1105 compatible = "qcom,sdm845-qfprom", "qcom,qfprom";
1107 #address-cells = <1>;
1108 #size-cells = <1>;
1110 qusb2p_hstx_trim: hstx-trim-primary@1eb {
1115 qusb2s_hstx_trim: hstx-trim-secondary@1eb {
1122 compatible = "qcom,prng-ee";
1125 clock-names = "core";
1128 qup_opp_table: opp-table-qup {
1129 compatible = "operating-points-v2";
1131 opp-50000000 {
1132 opp-hz = /bits/ 64 <50000000>;
1133 required-opps = <&rpmhpd_opp_min_svs>;
1136 opp-75000000 {
1137 opp-hz = /bits/ 64 <75000000>;
1138 required-opps = <&rpmhpd_opp_low_svs>;
1141 opp-100000000 {
1142 opp-hz = /bits/ 64 <100000000>;
1143 required-opps = <&rpmhpd_opp_svs>;
1146 opp-128000000 {
1147 opp-hz = /bits/ 64 <128000000>;
1148 required-opps = <&rpmhpd_opp_nom>;
1152 gpi_dma0: dma-controller@800000 {
1153 #dma-cells = <3>;
1154 compatible = "qcom,sdm845-gpi-dma";
1169 dma-channels = <13>;
1170 dma-channel-mask = <0xfa>;
1176 compatible = "qcom,geni-se-qup";
1178 clock-names = "m-ahb", "s-ahb";
1182 #address-cells = <2>;
1183 #size-cells = <2>;
1186 interconnect-names = "qup-core";
1190 compatible = "qcom,geni-i2c";
1192 clock-names = "se";
1194 pinctrl-names = "default";
1195 pinctrl-0 = <&qup_i2c0_default>;
1197 #address-cells = <1>;
1198 #size-cells = <0>;
1199 power-domains = <&rpmhpd SDM845_CX>;
1200 operating-points-v2 = <&qup_opp_table>;
1204 interconnect-names = "qup-core", "qup-config", "qup-memory";
1207 dma-names = "tx", "rx";
1212 compatible = "qcom,geni-spi";
1214 clock-names = "se";
1216 pinctrl-names = "default";
1217 pinctrl-0 = <&qup_spi0_default>;
1219 #address-cells = <1>;
1220 #size-cells = <0>;
1223 interconnect-names = "qup-core", "qup-config";
1226 dma-names = "tx", "rx";
1231 compatible = "qcom,geni-uart";
1233 clock-names = "se";
1235 pinctrl-names = "default";
1236 pinctrl-0 = <&qup_uart0_default>;
1238 power-domains = <&rpmhpd SDM845_CX>;
1239 operating-points-v2 = <&qup_opp_table>;
1242 interconnect-names = "qup-core", "qup-config";
1247 compatible = "qcom,geni-i2c";
1249 clock-names = "se";
1251 pinctrl-names = "default";
1252 pinctrl-0 = <&qup_i2c1_default>;
1254 #address-cells = <1>;
1255 #size-cells = <0>;
1256 power-domains = <&rpmhpd SDM845_CX>;
1257 operating-points-v2 = <&qup_opp_table>;
1261 interconnect-names = "qup-core", "qup-config", "qup-memory";
1264 dma-names = "tx", "rx";
1269 compatible = "qcom,geni-spi";
1271 clock-names = "se";
1273 pinctrl-names = "default";
1274 pinctrl-0 = <&qup_spi1_default>;
1276 #address-cells = <1>;
1277 #size-cells = <0>;
1280 interconnect-names = "qup-core", "qup-config";
1283 dma-names = "tx", "rx";
1288 compatible = "qcom,geni-uart";
1290 clock-names = "se";
1292 pinctrl-names = "default";
1293 pinctrl-0 = <&qup_uart1_default>;
1295 power-domains = <&rpmhpd SDM845_CX>;
1296 operating-points-v2 = <&qup_opp_table>;
1299 interconnect-names = "qup-core", "qup-config";
1304 compatible = "qcom,geni-i2c";
1306 clock-names = "se";
1308 pinctrl-names = "default";
1309 pinctrl-0 = <&qup_i2c2_default>;
1311 #address-cells = <1>;
1312 #size-cells = <0>;
1313 power-domains = <&rpmhpd SDM845_CX>;
1314 operating-points-v2 = <&qup_opp_table>;
1318 interconnect-names = "qup-core", "qup-config", "qup-memory";
1321 dma-names = "tx", "rx";
1326 compatible = "qcom,geni-spi";
1328 clock-names = "se";
1330 pinctrl-names = "default";
1331 pinctrl-0 = <&qup_spi2_default>;
1333 #address-cells = <1>;
1334 #size-cells = <0>;
1337 interconnect-names = "qup-core", "qup-config";
1340 dma-names = "tx", "rx";
1345 compatible = "qcom,geni-uart";
1347 clock-names = "se";
1349 pinctrl-names = "default";
1350 pinctrl-0 = <&qup_uart2_default>;
1352 power-domains = <&rpmhpd SDM845_CX>;
1353 operating-points-v2 = <&qup_opp_table>;
1356 interconnect-names = "qup-core", "qup-config";
1361 compatible = "qcom,geni-i2c";
1363 clock-names = "se";
1365 pinctrl-names = "default";
1366 pinctrl-0 = <&qup_i2c3_default>;
1368 #address-cells = <1>;
1369 #size-cells = <0>;
1370 power-domains = <&rpmhpd SDM845_CX>;
1371 operating-points-v2 = <&qup_opp_table>;
1375 interconnect-names = "qup-core", "qup-config", "qup-memory";
1378 dma-names = "tx", "rx";
1383 compatible = "qcom,geni-spi";
1385 clock-names = "se";
1387 pinctrl-names = "default";
1388 pinctrl-0 = <&qup_spi3_default>;
1390 #address-cells = <1>;
1391 #size-cells = <0>;
1394 interconnect-names = "qup-core", "qup-config";
1397 dma-names = "tx", "rx";
1402 compatible = "qcom,geni-uart";
1404 clock-names = "se";
1406 pinctrl-names = "default";
1407 pinctrl-0 = <&qup_uart3_default>;
1409 power-domains = <&rpmhpd SDM845_CX>;
1410 operating-points-v2 = <&qup_opp_table>;
1413 interconnect-names = "qup-core", "qup-config";
1418 compatible = "qcom,geni-i2c";
1420 clock-names = "se";
1422 pinctrl-names = "default";
1423 pinctrl-0 = <&qup_i2c4_default>;
1425 #address-cells = <1>;
1426 #size-cells = <0>;
1427 power-domains = <&rpmhpd SDM845_CX>;
1428 operating-points-v2 = <&qup_opp_table>;
1432 interconnect-names = "qup-core", "qup-config", "qup-memory";
1435 dma-names = "tx", "rx";
1440 compatible = "qcom,geni-spi";
1442 clock-names = "se";
1444 pinctrl-names = "default";
1445 pinctrl-0 = <&qup_spi4_default>;
1447 #address-cells = <1>;
1448 #size-cells = <0>;
1451 interconnect-names = "qup-core", "qup-config";
1454 dma-names = "tx", "rx";
1459 compatible = "qcom,geni-uart";
1461 clock-names = "se";
1463 pinctrl-names = "default";
1464 pinctrl-0 = <&qup_uart4_default>;
1466 power-domains = <&rpmhpd SDM845_CX>;
1467 operating-points-v2 = <&qup_opp_table>;
1470 interconnect-names = "qup-core", "qup-config";
1475 compatible = "qcom,geni-i2c";
1477 clock-names = "se";
1479 pinctrl-names = "default";
1480 pinctrl-0 = <&qup_i2c5_default>;
1482 #address-cells = <1>;
1483 #size-cells = <0>;
1484 power-domains = <&rpmhpd SDM845_CX>;
1485 operating-points-v2 = <&qup_opp_table>;
1489 interconnect-names = "qup-core", "qup-config", "qup-memory";
1492 dma-names = "tx", "rx";
1497 compatible = "qcom,geni-spi";
1499 clock-names = "se";
1501 pinctrl-names = "default";
1502 pinctrl-0 = <&qup_spi5_default>;
1504 #address-cells = <1>;
1505 #size-cells = <0>;
1508 interconnect-names = "qup-core", "qup-config";
1511 dma-names = "tx", "rx";
1516 compatible = "qcom,geni-uart";
1518 clock-names = "se";
1520 pinctrl-names = "default";
1521 pinctrl-0 = <&qup_uart5_default>;
1523 power-domains = <&rpmhpd SDM845_CX>;
1524 operating-points-v2 = <&qup_opp_table>;
1527 interconnect-names = "qup-core", "qup-config";
1532 compatible = "qcom,geni-i2c";
1534 clock-names = "se";
1536 pinctrl-names = "default";
1537 pinctrl-0 = <&qup_i2c6_default>;
1539 #address-cells = <1>;
1540 #size-cells = <0>;
1541 power-domains = <&rpmhpd SDM845_CX>;
1542 operating-points-v2 = <&qup_opp_table>;
1546 interconnect-names = "qup-core", "qup-config", "qup-memory";
1549 dma-names = "tx", "rx";
1554 compatible = "qcom,geni-spi";
1556 clock-names = "se";
1558 pinctrl-names = "default";
1559 pinctrl-0 = <&qup_spi6_default>;
1561 #address-cells = <1>;
1562 #size-cells = <0>;
1565 interconnect-names = "qup-core", "qup-config";
1568 dma-names = "tx", "rx";
1573 compatible = "qcom,geni-uart";
1575 clock-names = "se";
1577 pinctrl-names = "default";
1578 pinctrl-0 = <&qup_uart6_default>;
1580 power-domains = <&rpmhpd SDM845_CX>;
1581 operating-points-v2 = <&qup_opp_table>;
1584 interconnect-names = "qup-core", "qup-config";
1589 compatible = "qcom,geni-i2c";
1591 clock-names = "se";
1593 pinctrl-names = "default";
1594 pinctrl-0 = <&qup_i2c7_default>;
1596 #address-cells = <1>;
1597 #size-cells = <0>;
1598 power-domains = <&rpmhpd SDM845_CX>;
1599 operating-points-v2 = <&qup_opp_table>;
1604 compatible = "qcom,geni-spi";
1606 clock-names = "se";
1608 pinctrl-names = "default";
1609 pinctrl-0 = <&qup_spi7_default>;
1611 #address-cells = <1>;
1612 #size-cells = <0>;
1615 interconnect-names = "qup-core", "qup-config";
1618 dma-names = "tx", "rx";
1623 compatible = "qcom,geni-uart";
1625 clock-names = "se";
1627 pinctrl-names = "default";
1628 pinctrl-0 = <&qup_uart7_default>;
1630 power-domains = <&rpmhpd SDM845_CX>;
1631 operating-points-v2 = <&qup_opp_table>;
1634 interconnect-names = "qup-core", "qup-config";
1639 gpi_dma1: dma-controller@0xa00000 {
1640 #dma-cells = <3>;
1641 compatible = "qcom,sdm845-gpi-dma";
1656 dma-channels = <13>;
1657 dma-channel-mask = <0xfa>;
1663 compatible = "qcom,geni-se-qup";
1665 clock-names = "m-ahb", "s-ahb";
1669 #address-cells = <2>;
1670 #size-cells = <2>;
1673 interconnect-names = "qup-core";
1677 compatible = "qcom,geni-i2c";
1679 clock-names = "se";
1681 pinctrl-names = "default";
1682 pinctrl-0 = <&qup_i2c8_default>;
1684 #address-cells = <1>;
1685 #size-cells = <0>;
1686 power-domains = <&rpmhpd SDM845_CX>;
1687 operating-points-v2 = <&qup_opp_table>;
1691 interconnect-names = "qup-core", "qup-config", "qup-memory";
1694 dma-names = "tx", "rx";
1699 compatible = "qcom,geni-spi";
1701 clock-names = "se";
1703 pinctrl-names = "default";
1704 pinctrl-0 = <&qup_spi8_default>;
1706 #address-cells = <1>;
1707 #size-cells = <0>;
1710 interconnect-names = "qup-core", "qup-config";
1713 dma-names = "tx", "rx";
1718 compatible = "qcom,geni-uart";
1720 clock-names = "se";
1722 pinctrl-names = "default";
1723 pinctrl-0 = <&qup_uart8_default>;
1725 power-domains = <&rpmhpd SDM845_CX>;
1726 operating-points-v2 = <&qup_opp_table>;
1729 interconnect-names = "qup-core", "qup-config";
1734 compatible = "qcom,geni-i2c";
1736 clock-names = "se";
1738 pinctrl-names = "default";
1739 pinctrl-0 = <&qup_i2c9_default>;
1741 #address-cells = <1>;
1742 #size-cells = <0>;
1743 power-domains = <&rpmhpd SDM845_CX>;
1744 operating-points-v2 = <&qup_opp_table>;
1748 interconnect-names = "qup-core", "qup-config", "qup-memory";
1751 dma-names = "tx", "rx";
1756 compatible = "qcom,geni-spi";
1758 clock-names = "se";
1760 pinctrl-names = "default";
1761 pinctrl-0 = <&qup_spi9_default>;
1763 #address-cells = <1>;
1764 #size-cells = <0>;
1767 interconnect-names = "qup-core", "qup-config";
1770 dma-names = "tx", "rx";
1775 compatible = "qcom,geni-debug-uart";
1777 clock-names = "se";
1779 pinctrl-names = "default";
1780 pinctrl-0 = <&qup_uart9_default>;
1782 power-domains = <&rpmhpd SDM845_CX>;
1783 operating-points-v2 = <&qup_opp_table>;
1786 interconnect-names = "qup-core", "qup-config";
1791 compatible = "qcom,geni-i2c";
1793 clock-names = "se";
1795 pinctrl-names = "default";
1796 pinctrl-0 = <&qup_i2c10_default>;
1798 #address-cells = <1>;
1799 #size-cells = <0>;
1800 power-domains = <&rpmhpd SDM845_CX>;
1801 operating-points-v2 = <&qup_opp_table>;
1805 interconnect-names = "qup-core", "qup-config", "qup-memory";
1808 dma-names = "tx", "rx";
1813 compatible = "qcom,geni-spi";
1815 clock-names = "se";
1817 pinctrl-names = "default";
1818 pinctrl-0 = <&qup_spi10_default>;
1820 #address-cells = <1>;
1821 #size-cells = <0>;
1824 interconnect-names = "qup-core", "qup-config";
1827 dma-names = "tx", "rx";
1832 compatible = "qcom,geni-uart";
1834 clock-names = "se";
1836 pinctrl-names = "default";
1837 pinctrl-0 = <&qup_uart10_default>;
1839 power-domains = <&rpmhpd SDM845_CX>;
1840 operating-points-v2 = <&qup_opp_table>;
1843 interconnect-names = "qup-core", "qup-config";
1848 compatible = "qcom,geni-i2c";
1850 clock-names = "se";
1852 pinctrl-names = "default";
1853 pinctrl-0 = <&qup_i2c11_default>;
1855 #address-cells = <1>;
1856 #size-cells = <0>;
1857 power-domains = <&rpmhpd SDM845_CX>;
1858 operating-points-v2 = <&qup_opp_table>;
1862 interconnect-names = "qup-core", "qup-config", "qup-memory";
1865 dma-names = "tx", "rx";
1870 compatible = "qcom,geni-spi";
1872 clock-names = "se";
1874 pinctrl-names = "default";
1875 pinctrl-0 = <&qup_spi11_default>;
1877 #address-cells = <1>;
1878 #size-cells = <0>;
1881 interconnect-names = "qup-core", "qup-config";
1884 dma-names = "tx", "rx";
1889 compatible = "qcom,geni-uart";
1891 clock-names = "se";
1893 pinctrl-names = "default";
1894 pinctrl-0 = <&qup_uart11_default>;
1896 power-domains = <&rpmhpd SDM845_CX>;
1897 operating-points-v2 = <&qup_opp_table>;
1900 interconnect-names = "qup-core", "qup-config";
1905 compatible = "qcom,geni-i2c";
1907 clock-names = "se";
1909 pinctrl-names = "default";
1910 pinctrl-0 = <&qup_i2c12_default>;
1912 #address-cells = <1>;
1913 #size-cells = <0>;
1914 power-domains = <&rpmhpd SDM845_CX>;
1915 operating-points-v2 = <&qup_opp_table>;
1919 interconnect-names = "qup-core", "qup-config", "qup-memory";
1922 dma-names = "tx", "rx";
1927 compatible = "qcom,geni-spi";
1929 clock-names = "se";
1931 pinctrl-names = "default";
1932 pinctrl-0 = <&qup_spi12_default>;
1934 #address-cells = <1>;
1935 #size-cells = <0>;
1938 interconnect-names = "qup-core", "qup-config";
1941 dma-names = "tx", "rx";
1946 compatible = "qcom,geni-uart";
1948 clock-names = "se";
1950 pinctrl-names = "default";
1951 pinctrl-0 = <&qup_uart12_default>;
1953 power-domains = <&rpmhpd SDM845_CX>;
1954 operating-points-v2 = <&qup_opp_table>;
1957 interconnect-names = "qup-core", "qup-config";
1962 compatible = "qcom,geni-i2c";
1964 clock-names = "se";
1966 pinctrl-names = "default";
1967 pinctrl-0 = <&qup_i2c13_default>;
1969 #address-cells = <1>;
1970 #size-cells = <0>;
1971 power-domains = <&rpmhpd SDM845_CX>;
1972 operating-points-v2 = <&qup_opp_table>;
1976 interconnect-names = "qup-core", "qup-config", "qup-memory";
1979 dma-names = "tx", "rx";
1984 compatible = "qcom,geni-spi";
1986 clock-names = "se";
1988 pinctrl-names = "default";
1989 pinctrl-0 = <&qup_spi13_default>;
1991 #address-cells = <1>;
1992 #size-cells = <0>;
1995 interconnect-names = "qup-core", "qup-config";
1998 dma-names = "tx", "rx";
2003 compatible = "qcom,geni-uart";
2005 clock-names = "se";
2007 pinctrl-names = "default";
2008 pinctrl-0 = <&qup_uart13_default>;
2010 power-domains = <&rpmhpd SDM845_CX>;
2011 operating-points-v2 = <&qup_opp_table>;
2014 interconnect-names = "qup-core", "qup-config";
2019 compatible = "qcom,geni-i2c";
2021 clock-names = "se";
2023 pinctrl-names = "default";
2024 pinctrl-0 = <&qup_i2c14_default>;
2026 #address-cells = <1>;
2027 #size-cells = <0>;
2028 power-domains = <&rpmhpd SDM845_CX>;
2029 operating-points-v2 = <&qup_opp_table>;
2033 interconnect-names = "qup-core", "qup-config", "qup-memory";
2036 dma-names = "tx", "rx";
2041 compatible = "qcom,geni-spi";
2043 clock-names = "se";
2045 pinctrl-names = "default";
2046 pinctrl-0 = <&qup_spi14_default>;
2048 #address-cells = <1>;
2049 #size-cells = <0>;
2052 interconnect-names = "qup-core", "qup-config";
2055 dma-names = "tx", "rx";
2060 compatible = "qcom,geni-uart";
2062 clock-names = "se";
2064 pinctrl-names = "default";
2065 pinctrl-0 = <&qup_uart14_default>;
2067 power-domains = <&rpmhpd SDM845_CX>;
2068 operating-points-v2 = <&qup_opp_table>;
2071 interconnect-names = "qup-core", "qup-config";
2076 compatible = "qcom,geni-i2c";
2078 clock-names = "se";
2080 pinctrl-names = "default";
2081 pinctrl-0 = <&qup_i2c15_default>;
2083 #address-cells = <1>;
2084 #size-cells = <0>;
2085 power-domains = <&rpmhpd SDM845_CX>;
2086 operating-points-v2 = <&qup_opp_table>;
2091 interconnect-names = "qup-core", "qup-config", "qup-memory";
2094 dma-names = "tx", "rx";
2098 compatible = "qcom,geni-spi";
2100 clock-names = "se";
2102 pinctrl-names = "default";
2103 pinctrl-0 = <&qup_spi15_default>;
2105 #address-cells = <1>;
2106 #size-cells = <0>;
2109 interconnect-names = "qup-core", "qup-config";
2112 dma-names = "tx", "rx";
2117 compatible = "qcom,geni-uart";
2119 clock-names = "se";
2121 pinctrl-names = "default";
2122 pinctrl-0 = <&qup_uart15_default>;
2124 power-domains = <&rpmhpd SDM845_CX>;
2125 operating-points-v2 = <&qup_opp_table>;
2128 interconnect-names = "qup-core", "qup-config";
2133 llcc: system-cache-controller@1100000 {
2134 compatible = "qcom,sdm845-llcc";
2136 reg-names = "llcc_base", "llcc_broadcast_base";
2141 compatible = "qcom,sdm845-llcc-bwmon";
2146 operating-points-v2 = <&llcc_bwmon_opp_table>;
2148 llcc_bwmon_opp_table: opp-table {
2149 compatible = "operating-points-v2";
2153 * cpu4_opp_table bandwidth for gladiator_noc-mem_noc
2155 * bandwidth table of qcom,llccbw (qcom,bw-tbl,
2156 * bus width: 4 bytes) from msm-4.9 downstream
2159 opp-0 {
2160 opp-peak-kBps = <800000>;
2162 opp-1 {
2163 opp-peak-kBps = <1804000>;
2165 opp-2 {
2166 opp-peak-kBps = <3072000>;
2168 opp-3 {
2169 opp-peak-kBps = <5412000>;
2171 opp-4 {
2172 opp-peak-kBps = <7216000>;
2178 compatible = "qcom,sdm845-bwmon", "qcom,msm8998-bwmon";
2183 operating-points-v2 = <&cpu_bwmon_opp_table>;
2185 cpu_bwmon_opp_table: opp-table {
2186 compatible = "operating-points-v2";
2192 * from bandwidth table of qcom,cpu4-l3lat-mon
2193 * (qcom,core-dev-table, bus width: 16 bytes)
2194 * from msm-4.9 downstream kernel.
2196 opp-0 {
2197 opp-peak-kBps = <4800000>;
2199 opp-1 {
2200 opp-peak-kBps = <9216000>;
2202 opp-2 {
2203 opp-peak-kBps = <15052800>;
2205 opp-3 {
2206 opp-peak-kBps = <20889600>;
2208 opp-4 {
2209 opp-peak-kBps = <25497600>;
2215 compatible = "qcom,pcie-sdm845";
2220 reg-names = "parf", "dbi", "elbi", "config";
2222 linux,pci-domain = <0>;
2223 bus-range = <0x00 0xff>;
2224 num-lanes = <1>;
2226 #address-cells = <3>;
2227 #size-cells = <2>;
2233 interrupt-names = "msi";
2234 #interrupt-cells = <1>;
2235 interrupt-map-mask = <0 0 0 0x7>;
2236 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2248 clock-names = "pipe",
2257 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
2275 reset-names = "pci";
2277 power-domains = <&gcc PCIE_0_GDSC>;
2280 phy-names = "pciephy";
2286 compatible = "qcom,sdm845-qmp-pcie-phy";
2288 #address-cells = <2>;
2289 #size-cells = <2>;
2295 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2298 reset-names = "phy";
2300 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2301 assigned-clock-rates = <100000000>;
2311 clock-names = "pipe0";
2313 #clock-cells = <0>;
2314 #phy-cells = <0>;
2315 clock-output-names = "pcie_0_pipe_clk";
2320 compatible = "qcom,pcie-sdm845";
2325 reg-names = "parf", "dbi", "elbi", "config";
2327 linux,pci-domain = <1>;
2328 bus-range = <0x00 0xff>;
2329 num-lanes = <1>;
2331 #address-cells = <3>;
2332 #size-cells = <2>;
2338 interrupt-names = "msi";
2339 #interrupt-cells = <1>;
2340 interrupt-map-mask = <0 0 0 0x7>;
2341 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2354 clock-names = "pipe",
2363 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2364 assigned-clock-rates = <19200000>;
2367 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2385 reset-names = "pci";
2387 power-domains = <&gcc PCIE_1_GDSC>;
2390 phy-names = "pciephy";
2396 compatible = "qcom,sdm845-qhp-pcie-phy";
2398 #address-cells = <2>;
2399 #size-cells = <2>;
2405 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2408 reset-names = "phy";
2410 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2411 assigned-clock-rates = <100000000>;
2420 clock-names = "pipe0";
2422 #clock-cells = <0>;
2423 #phy-cells = <0>;
2424 clock-output-names = "pcie_1_pipe_clk";
2429 compatible = "qcom,sdm845-mem-noc";
2431 #interconnect-cells = <2>;
2432 qcom,bcm-voters = <&apps_bcm_voter>;
2436 compatible = "qcom,sdm845-dc-noc";
2438 #interconnect-cells = <2>;
2439 qcom,bcm-voters = <&apps_bcm_voter>;
2443 compatible = "qcom,sdm845-config-noc";
2445 #interconnect-cells = <2>;
2446 qcom,bcm-voters = <&apps_bcm_voter>;
2450 compatible = "qcom,sdm845-system-noc";
2452 #interconnect-cells = <2>;
2453 qcom,bcm-voters = <&apps_bcm_voter>;
2457 compatible = "qcom,sdm845-aggre1-noc";
2459 #interconnect-cells = <2>;
2460 qcom,bcm-voters = <&apps_bcm_voter>;
2464 compatible = "qcom,sdm845-aggre2-noc";
2466 #interconnect-cells = <2>;
2467 qcom,bcm-voters = <&apps_bcm_voter>;
2471 compatible = "qcom,sdm845-mmss-noc";
2473 #interconnect-cells = <2>;
2474 qcom,bcm-voters = <&apps_bcm_voter>;
2478 compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
2479 "jedec,ufs-2.0";
2482 reg-names = "std", "ice";
2485 phy-names = "ufsphy";
2486 lanes-per-direction = <2>;
2487 power-domains = <&gcc UFS_PHY_GDSC>;
2488 #reset-cells = <1>;
2490 reset-names = "rst";
2494 clock-names =
2514 freq-table-hz =
2529 compatible = "qcom,sdm845-qmp-ufs-phy";
2531 #address-cells = <2>;
2532 #size-cells = <2>;
2534 clock-names = "ref",
2540 reset-names = "ufsphy";
2549 #phy-cells = <0>;
2553 cryptobam: dma-controller@1dc4000 {
2554 compatible = "qcom,bam-v1.7.0";
2558 clock-names = "bam_clk";
2559 #dma-cells = <1>;
2561 qcom,controlled-remotely;
2569 compatible = "qcom,crypto-v5.4";
2574 clock-names = "iface", "bus", "core";
2576 dma-names = "rx", "tx";
2584 compatible = "qcom,sdm845-ipa";
2591 reg-names = "ipa-reg",
2592 "ipa-shared",
2595 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
2599 interrupt-names = "ipa",
2601 "ipa-clock-query",
2602 "ipa-setup-ready";
2605 clock-names = "core";
2610 interconnect-names = "memory",
2614 qcom,smem-states = <&ipa_smp2p_out 0>,
2616 qcom,smem-state-names = "ipa-clock-enabled-valid",
2617 "ipa-clock-enabled";
2623 compatible = "qcom,tcsr-mutex";
2625 #hwlock-cells = <1>;
2629 compatible = "qcom,sdm845-tcsr", "syscon";
2634 compatible = "qcom,sdm845-pinctrl";
2637 gpio-controller;
2638 #gpio-cells = <2>;
2639 interrupt-controller;
2640 #interrupt-cells = <2>;
2641 gpio-ranges = <&tlmm 0 0 151>;
2642 wakeup-parent = <&pdc_intc>;
2644 cci0_default: cci0-default {
2649 bias-pull-up;
2650 drive-strength = <2>; /* 2 mA */
2653 cci0_sleep: cci0-sleep {
2658 drive-strength = <2>; /* 2 mA */
2659 bias-pull-down;
2662 cci1_default: cci1-default {
2667 bias-pull-up;
2668 drive-strength = <2>; /* 2 mA */
2671 cci1_sleep: cci1-sleep {
2676 drive-strength = <2>; /* 2 mA */
2677 bias-pull-down;
2680 qspi_clk: qspi-clk {
2687 qspi_cs0: qspi-cs0 {
2694 qspi_cs1: qspi-cs1 {
2701 qspi_data01: qspi-data01 {
2702 pinmux-data {
2708 qspi_data12: qspi-data12 {
2709 pinmux-data {
2715 qup_i2c0_default: qup-i2c0-default {
2722 qup_i2c1_default: qup-i2c1-default {
2729 qup_i2c2_default: qup-i2c2-default {
2736 qup_i2c3_default: qup-i2c3-default {
2743 qup_i2c4_default: qup-i2c4-default {
2750 qup_i2c5_default: qup-i2c5-default {
2757 qup_i2c6_default: qup-i2c6-default {
2764 qup_i2c7_default: qup-i2c7-default {
2771 qup_i2c8_default: qup-i2c8-default {
2778 qup_i2c9_default: qup-i2c9-default {
2785 qup_i2c10_default: qup-i2c10-default {
2792 qup_i2c11_default: qup-i2c11-default {
2799 qup_i2c12_default: qup-i2c12-default {
2806 qup_i2c13_default: qup-i2c13-default {
2813 qup_i2c14_default: qup-i2c14-default {
2820 qup_i2c15_default: qup-i2c15-default {
2827 qup_spi0_default: qup-spi0-default {
2837 drive-strength = <6>;
2838 bias-disable;
2842 qup_spi1_default: qup-spi1-default {
2850 qup_spi2_default: qup-spi2-default {
2858 qup_spi3_default: qup-spi3-default {
2866 qup_spi4_default: qup-spi4-default {
2874 qup_spi5_default: qup-spi5-default {
2882 qup_spi6_default: qup-spi6-default {
2890 qup_spi7_default: qup-spi7-default {
2898 qup_spi8_default: qup-spi8-default {
2906 qup_spi9_default: qup-spi9-default {
2914 qup_spi10_default: qup-spi10-default {
2922 qup_spi11_default: qup-spi11-default {
2930 qup_spi12_default: qup-spi12-default {
2938 qup_spi13_default: qup-spi13-default {
2946 qup_spi14_default: qup-spi14-default {
2954 qup_spi15_default: qup-spi15-default {
2962 qup_uart0_default: qup-uart0-default {
2969 qup_uart1_default: qup-uart1-default {
2976 qup_uart2_default: qup-uart2-default {
2983 qup_uart3_default: qup-uart3-default {
2990 qup_uart4_default: qup-uart4-default {
2997 qup_uart5_default: qup-uart5-default {
3004 qup_uart6_default: qup-uart6-default {
3011 qup_uart7_default: qup-uart7-default {
3018 qup_uart8_default: qup-uart8-default {
3025 qup_uart9_default: qup-uart9-default {
3032 qup_uart10_default: qup-uart10-default {
3039 qup_uart11_default: qup-uart11-default {
3046 qup_uart12_default: qup-uart12-default {
3053 qup_uart13_default: qup-uart13-default {
3060 qup_uart14_default: qup-uart14-default {
3067 qup_uart15_default: qup-uart15-default {
3082 drive-strength = <2>;
3083 bias-pull-down;
3084 input-enable;
3096 drive-strength = <8>;
3097 bias-disable;
3098 output-high;
3110 drive-strength = <2>;
3111 bias-pull-down;
3112 input-enable;
3124 drive-strength = <8>;
3125 bias-disable;
3137 drive-strength = <2>;
3138 bias-pull-down;
3139 input-enable;
3151 drive-strength = <8>;
3152 bias-disable;
3164 drive-strength = <2>;
3165 bias-pull-down;
3166 input-enable;
3178 drive-strength = <8>;
3179 bias-disable;
3191 drive-strength = <2>;
3192 bias-pull-down;
3193 input-enable;
3205 drive-strength = <8>;
3206 bias-disable;
3212 compatible = "qcom,sdm845-mss-pil";
3214 reg-names = "qdsp6", "rmb";
3216 interrupts-extended =
3223 interrupt-names = "wdog", "fatal", "ready",
3224 "handover", "stop-ack",
3225 "shutdown-ack";
3235 clock-names = "iface", "bus", "mem", "gpll0_mss",
3240 qcom,smem-states = <&modem_smp2p_out 0>;
3241 qcom,smem-state-names = "stop";
3245 reset-names = "mss_restart", "pdc_reset";
3247 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
3249 power-domains = <&rpmhpd SDM845_CX>,
3252 power-domain-names = "cx", "mx", "mss";
3257 memory-region = <&mba_region>;
3261 memory-region = <&mpss_region>;
3264 glink-edge {
3267 qcom,remote-pid = <1>;
3272 gpucc: clock-controller@5090000 {
3273 compatible = "qcom,sdm845-gpucc";
3275 #clock-cells = <1>;
3276 #reset-cells = <1>;
3277 #power-domain-cells = <1>;
3281 clock-names = "bi_tcxo",
3287 compatible = "arm,coresight-stm", "arm,primecell";
3290 reg-names = "stm-base", "stm-stimulus-base";
3293 clock-names = "apb_pclk";
3295 out-ports {
3298 remote-endpoint =
3306 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3310 clock-names = "apb_pclk";
3312 out-ports {
3315 remote-endpoint =
3321 in-ports {
3322 #address-cells = <1>;
3323 #size-cells = <0>;
3328 remote-endpoint = <&stm_out>;
3335 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3339 clock-names = "apb_pclk";
3341 out-ports {
3344 remote-endpoint =
3350 in-ports {
3351 #address-cells = <1>;
3352 #size-cells = <0>;
3357 remote-endpoint =
3365 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3369 clock-names = "apb_pclk";
3371 out-ports {
3374 remote-endpoint = <&etf_in>;
3379 in-ports {
3380 #address-cells = <1>;
3381 #size-cells = <0>;
3386 remote-endpoint =
3394 remote-endpoint =
3402 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3406 clock-names = "apb_pclk";
3408 out-ports {
3411 remote-endpoint = <&etr_in>;
3416 in-ports {
3419 remote-endpoint = <&etf_out>;
3426 compatible = "arm,coresight-tmc", "arm,primecell";
3430 clock-names = "apb_pclk";
3432 out-ports {
3435 remote-endpoint =
3441 in-ports {
3442 #address-cells = <1>;
3443 #size-cells = <0>;
3448 remote-endpoint =
3456 compatible = "arm,coresight-tmc", "arm,primecell";
3460 clock-names = "apb_pclk";
3461 arm,scatter-gather;
3463 in-ports {
3466 remote-endpoint =
3474 compatible = "arm,coresight-etm4x", "arm,primecell";
3480 clock-names = "apb_pclk";
3481 arm,coresight-loses-context-with-cpu;
3483 out-ports {
3486 remote-endpoint =
3494 compatible = "arm,coresight-etm4x", "arm,primecell";
3500 clock-names = "apb_pclk";
3501 arm,coresight-loses-context-with-cpu;
3503 out-ports {
3506 remote-endpoint =
3514 compatible = "arm,coresight-etm4x", "arm,primecell";
3520 clock-names = "apb_pclk";
3521 arm,coresight-loses-context-with-cpu;
3523 out-ports {
3526 remote-endpoint =
3534 compatible = "arm,coresight-etm4x", "arm,primecell";
3540 clock-names = "apb_pclk";
3541 arm,coresight-loses-context-with-cpu;
3543 out-ports {
3546 remote-endpoint =
3554 compatible = "arm,coresight-etm4x", "arm,primecell";
3560 clock-names = "apb_pclk";
3561 arm,coresight-loses-context-with-cpu;
3563 out-ports {
3566 remote-endpoint =
3574 compatible = "arm,coresight-etm4x", "arm,primecell";
3580 clock-names = "apb_pclk";
3581 arm,coresight-loses-context-with-cpu;
3583 out-ports {
3586 remote-endpoint =
3594 compatible = "arm,coresight-etm4x", "arm,primecell";
3600 clock-names = "apb_pclk";
3601 arm,coresight-loses-context-with-cpu;
3603 out-ports {
3606 remote-endpoint =
3614 compatible = "arm,coresight-etm4x", "arm,primecell";
3620 clock-names = "apb_pclk";
3621 arm,coresight-loses-context-with-cpu;
3623 out-ports {
3626 remote-endpoint =
3634 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3638 clock-names = "apb_pclk";
3640 out-ports {
3643 remote-endpoint =
3649 in-ports {
3650 #address-cells = <1>;
3651 #size-cells = <0>;
3656 remote-endpoint =
3664 remote-endpoint =
3672 remote-endpoint =
3680 remote-endpoint =
3688 remote-endpoint =
3696 remote-endpoint =
3704 remote-endpoint =
3712 remote-endpoint =
3720 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3724 clock-names = "apb_pclk";
3726 out-ports {
3729 remote-endpoint =
3735 in-ports {
3738 remote-endpoint =
3746 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
3751 interrupt-names = "hc_irq", "pwr_irq";
3756 clock-names = "iface", "core", "xo";
3758 power-domains = <&rpmhpd SDM845_CX>;
3759 operating-points-v2 = <&sdhc2_opp_table>;
3763 sdhc2_opp_table: opp-table {
3764 compatible = "operating-points-v2";
3766 opp-9600000 {
3767 opp-hz = /bits/ 64 <9600000>;
3768 required-opps = <&rpmhpd_opp_min_svs>;
3771 opp-19200000 {
3772 opp-hz = /bits/ 64 <19200000>;
3773 required-opps = <&rpmhpd_opp_low_svs>;
3776 opp-100000000 {
3777 opp-hz = /bits/ 64 <100000000>;
3778 required-opps = <&rpmhpd_opp_svs>;
3781 opp-201500000 {
3782 opp-hz = /bits/ 64 <201500000>;
3783 required-opps = <&rpmhpd_opp_svs_l1>;
3788 qspi_opp_table: opp-table-qspi {
3789 compatible = "operating-points-v2";
3791 opp-19200000 {
3792 opp-hz = /bits/ 64 <19200000>;
3793 required-opps = <&rpmhpd_opp_min_svs>;
3796 opp-100000000 {
3797 opp-hz = /bits/ 64 <100000000>;
3798 required-opps = <&rpmhpd_opp_low_svs>;
3801 opp-150000000 {
3802 opp-hz = /bits/ 64 <150000000>;
3803 required-opps = <&rpmhpd_opp_svs>;
3806 opp-300000000 {
3807 opp-hz = /bits/ 64 <300000000>;
3808 required-opps = <&rpmhpd_opp_nom>;
3813 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
3815 #address-cells = <1>;
3816 #size-cells = <0>;
3820 clock-names = "iface", "core";
3821 power-domains = <&rpmhpd SDM845_CX>;
3822 operating-points-v2 = <&qspi_opp_table>;
3827 compatible = "qcom,slim-ngd-v2.1.0";
3831 qcom,apps-ch-pipes = <0x780000>;
3832 qcom,ea-pc = <0x270>;
3836 dma-names = "rx", "tx", "tx2", "rx2";
3839 #address-cells = <1>;
3840 #size-cells = <0>;
3844 #address-cells = <2>;
3845 #size-cells = <0>;
3855 slim-ifc-dev = <&wcd9340_ifd>;
3857 #sound-dai-cells = <1>;
3859 interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>;
3860 interrupt-controller;
3861 #interrupt-cells = <1>;
3863 #clock-cells = <0>;
3864 clock-frequency = <9600000>;
3865 clock-output-names = "mclk";
3866 qcom,micbias1-microvolt = <1800000>;
3867 qcom,micbias2-microvolt = <1800000>;
3868 qcom,micbias3-microvolt = <1800000>;
3869 qcom,micbias4-microvolt = <1800000>;
3871 #address-cells = <1>;
3872 #size-cells = <1>;
3874 wcdgpio: gpio-controller@42 {
3875 compatible = "qcom,wcd9340-gpio";
3876 gpio-controller;
3877 #gpio-cells = <2>;
3882 compatible = "qcom,soundwire-v1.3.0";
3884 interrupts-extended = <&wcd9340 20>;
3886 qcom,dout-ports = <6>;
3887 qcom,din-ports = <2>;
3888 qcom,ports-sinterval-low =/bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>;
3889 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >;
3890 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>;
3892 #sound-dai-cells = <1>;
3894 clock-names = "iface";
3895 #address-cells = <2>;
3896 #size-cells = <0>;
3905 compatible = "qcom,sdm845-lmh";
3909 qcom,lmh-temp-arm-millicelsius = <65000>;
3910 qcom,lmh-temp-low-millicelsius = <94500>;
3911 qcom,lmh-temp-high-millicelsius = <95000>;
3912 interrupt-controller;
3913 #interrupt-cells = <1>;
3917 compatible = "qcom,sdm845-lmh";
3921 qcom,lmh-temp-arm-millicelsius = <65000>;
3922 qcom,lmh-temp-low-millicelsius = <94500>;
3923 qcom,lmh-temp-high-millicelsius = <95000>;
3924 interrupt-controller;
3925 #interrupt-cells = <1>;
3932 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3935 #phy-cells = <0>;
3939 clock-names = "cfg_ahb", "ref";
3943 nvmem-cells = <&qusb2p_hstx_trim>;
3947 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3950 #phy-cells = <0>;
3954 clock-names = "cfg_ahb", "ref";
3958 nvmem-cells = <&qusb2s_hstx_trim>;
3962 compatible = "qcom,sdm845-qmp-usb3-phy";
3966 #address-cells = <2>;
3967 #size-cells = <2>;
3974 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
3978 reset-names = "phy", "common";
3987 #clock-cells = <0>;
3988 #phy-cells = <0>;
3990 clock-names = "pipe0";
3991 clock-output-names = "usb3_phy_pipe_clk_src";
3996 compatible = "qcom,sdm845-qmp-usb3-uni-phy";
3999 #address-cells = <2>;
4000 #size-cells = <2>;
4007 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
4011 reset-names = "phy", "common";
4018 #clock-cells = <0>;
4019 #phy-cells = <0>;
4021 clock-names = "pipe0";
4022 clock-output-names = "usb3_uni_phy_pipe_clk_src";
4027 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4030 #address-cells = <2>;
4031 #size-cells = <2>;
4033 dma-ranges;
4040 clock-names = "cfg_noc",
4046 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4048 assigned-clock-rates = <19200000>, <150000000>;
4054 interrupt-names = "hs_phy_irq", "ss_phy_irq",
4057 power-domains = <&gcc USB30_PRIM_GDSC>;
4063 interconnect-names = "usb-ddr", "apps-usb";
4073 phy-names = "usb2-phy", "usb3-phy";
4078 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4081 #address-cells = <2>;
4082 #size-cells = <2>;
4084 dma-ranges;
4091 clock-names = "cfg_noc",
4097 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4099 assigned-clock-rates = <19200000>, <150000000>;
4105 interrupt-names = "hs_phy_irq", "ss_phy_irq",
4108 power-domains = <&gcc USB30_SEC_GDSC>;
4114 interconnect-names = "usb-ddr", "apps-usb";
4124 phy-names = "usb2-phy", "usb3-phy";
4128 venus: video-codec@aa00000 {
4129 compatible = "qcom,sdm845-venus-v2";
4132 power-domains = <&videocc VENUS_GDSC>,
4136 power-domain-names = "venus", "vcodec0", "vcodec1", "cx";
4137 operating-points-v2 = <&venus_opp_table>;
4145 clock-names = "core", "iface", "bus",
4150 memory-region = <&venus_mem>;
4153 interconnect-names = "video-mem", "cpu-cfg";
4157 video-core0 {
4158 compatible = "venus-decoder";
4161 video-core1 {
4162 compatible = "venus-encoder";
4165 venus_opp_table: opp-table {
4166 compatible = "operating-points-v2";
4168 opp-100000000 {
4169 opp-hz = /bits/ 64 <100000000>;
4170 required-opps = <&rpmhpd_opp_min_svs>;
4173 opp-200000000 {
4174 opp-hz = /bits/ 64 <200000000>;
4175 required-opps = <&rpmhpd_opp_low_svs>;
4178 opp-320000000 {
4179 opp-hz = /bits/ 64 <320000000>;
4180 required-opps = <&rpmhpd_opp_svs>;
4183 opp-380000000 {
4184 opp-hz = /bits/ 64 <380000000>;
4185 required-opps = <&rpmhpd_opp_svs_l1>;
4188 opp-444000000 {
4189 opp-hz = /bits/ 64 <444000000>;
4190 required-opps = <&rpmhpd_opp_nom>;
4193 opp-533000097 {
4194 opp-hz = /bits/ 64 <533000097>;
4195 required-opps = <&rpmhpd_opp_turbo>;
4200 videocc: clock-controller@ab00000 {
4201 compatible = "qcom,sdm845-videocc";
4204 clock-names = "bi_tcxo";
4205 #clock-cells = <1>;
4206 #power-domain-cells = <1>;
4207 #reset-cells = <1>;
4211 compatible = "qcom,sdm845-camss";
4223 reg-names = "csid0",
4244 interrupt-names = "csid0",
4255 power-domains = <&clock_camcc IFE_0_GDSC>,
4295 clock-names = "camnoc_axi",
4340 #address-cells = <1>;
4341 #size-cells = <0>;
4346 compatible = "qcom,sdm845-cci";
4347 #address-cells = <1>;
4348 #size-cells = <0>;
4352 power-domains = <&clock_camcc TITAN_TOP_GDSC>;
4360 clock-names = "camnoc_axi",
4367 assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4369 assigned-clock-rates = <80000000>, <37500000>;
4371 pinctrl-names = "default", "sleep";
4372 pinctrl-0 = <&cci0_default &cci1_default>;
4373 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
4377 cci_i2c0: i2c-bus@0 {
4379 clock-frequency = <1000000>;
4380 #address-cells = <1>;
4381 #size-cells = <0>;
4384 cci_i2c1: i2c-bus@1 {
4386 clock-frequency = <1000000>;
4387 #address-cells = <1>;
4388 #size-cells = <0>;
4392 clock_camcc: clock-controller@ad00000 {
4393 compatible = "qcom,sdm845-camcc";
4395 #clock-cells = <1>;
4396 #reset-cells = <1>;
4397 #power-domain-cells = <1>;
4399 clock-names = "bi_tcxo";
4402 dsi_opp_table: opp-table-dsi {
4403 compatible = "operating-points-v2";
4405 opp-19200000 {
4406 opp-hz = /bits/ 64 <19200000>;
4407 required-opps = <&rpmhpd_opp_min_svs>;
4410 opp-180000000 {
4411 opp-hz = /bits/ 64 <180000000>;
4412 required-opps = <&rpmhpd_opp_low_svs>;
4415 opp-275000000 {
4416 opp-hz = /bits/ 64 <275000000>;
4417 required-opps = <&rpmhpd_opp_svs>;
4420 opp-328580000 {
4421 opp-hz = /bits/ 64 <328580000>;
4422 required-opps = <&rpmhpd_opp_svs_l1>;
4425 opp-358000000 {
4426 opp-hz = /bits/ 64 <358000000>;
4427 required-opps = <&rpmhpd_opp_nom>;
4432 compatible = "qcom,sdm845-mdss";
4434 reg-names = "mdss";
4436 power-domains = <&dispcc MDSS_GDSC>;
4440 clock-names = "iface", "core";
4443 interrupt-controller;
4444 #interrupt-cells = <1>;
4448 interconnect-names = "mdp0-mem", "mdp1-mem";
4455 #address-cells = <2>;
4456 #size-cells = <2>;
4459 mdss_mdp: display-controller@ae01000 {
4460 compatible = "qcom,sdm845-dpu";
4463 reg-names = "mdp", "vbif";
4470 clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
4472 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4473 assigned-clock-rates = <19200000>;
4474 operating-points-v2 = <&mdp_opp_table>;
4475 power-domains = <&rpmhpd SDM845_CX>;
4477 interrupt-parent = <&mdss>;
4481 #address-cells = <1>;
4482 #size-cells = <0>;
4487 remote-endpoint = <&dsi0_in>;
4494 remote-endpoint = <&dsi1_in>;
4499 mdp_opp_table: opp-table {
4500 compatible = "operating-points-v2";
4502 opp-19200000 {
4503 opp-hz = /bits/ 64 <19200000>;
4504 required-opps = <&rpmhpd_opp_min_svs>;
4507 opp-171428571 {
4508 opp-hz = /bits/ 64 <171428571>;
4509 required-opps = <&rpmhpd_opp_low_svs>;
4512 opp-344000000 {
4513 opp-hz = /bits/ 64 <344000000>;
4514 required-opps = <&rpmhpd_opp_svs_l1>;
4517 opp-430000000 {
4518 opp-hz = /bits/ 64 <430000000>;
4519 required-opps = <&rpmhpd_opp_nom>;
4525 compatible = "qcom,mdss-dsi-ctrl";
4527 reg-names = "dsi_ctrl";
4529 interrupt-parent = <&mdss>;
4538 clock-names = "byte",
4544 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4545 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
4547 operating-points-v2 = <&dsi_opp_table>;
4548 power-domains = <&rpmhpd SDM845_CX>;
4551 phy-names = "dsi";
4555 #address-cells = <1>;
4556 #size-cells = <0>;
4559 #address-cells = <1>;
4560 #size-cells = <0>;
4565 remote-endpoint = <&dpu_intf1_out>;
4577 dsi0_phy: dsi-phy@ae94400 {
4578 compatible = "qcom,dsi-phy-10nm";
4582 reg-names = "dsi_phy",
4586 #clock-cells = <1>;
4587 #phy-cells = <0>;
4591 clock-names = "iface", "ref";
4597 compatible = "qcom,mdss-dsi-ctrl";
4599 reg-names = "dsi_ctrl";
4601 interrupt-parent = <&mdss>;
4610 clock-names = "byte",
4616 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4617 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
4619 operating-points-v2 = <&dsi_opp_table>;
4620 power-domains = <&rpmhpd SDM845_CX>;
4623 phy-names = "dsi";
4627 #address-cells = <1>;
4628 #size-cells = <0>;
4631 #address-cells = <1>;
4632 #size-cells = <0>;
4637 remote-endpoint = <&dpu_intf2_out>;
4649 dsi1_phy: dsi-phy@ae96400 {
4650 compatible = "qcom,dsi-phy-10nm";
4654 reg-names = "dsi_phy",
4658 #clock-cells = <1>;
4659 #phy-cells = <0>;
4663 clock-names = "iface", "ref";
4670 compatible = "qcom,adreno-630.2", "qcom,adreno";
4673 reg-names = "kgsl_3d0_reg_memory", "cx_mem";
4684 operating-points-v2 = <&gpu_opp_table>;
4689 interconnect-names = "gfx-mem";
4693 gpu_opp_table: opp-table {
4694 compatible = "operating-points-v2";
4696 opp-710000000 {
4697 opp-hz = /bits/ 64 <710000000>;
4698 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4699 opp-peak-kBps = <7216000>;
4702 opp-675000000 {
4703 opp-hz = /bits/ 64 <675000000>;
4704 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4705 opp-peak-kBps = <7216000>;
4708 opp-596000000 {
4709 opp-hz = /bits/ 64 <596000000>;
4710 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4711 opp-peak-kBps = <6220000>;
4714 opp-520000000 {
4715 opp-hz = /bits/ 64 <520000000>;
4716 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4717 opp-peak-kBps = <6220000>;
4720 opp-414000000 {
4721 opp-hz = /bits/ 64 <414000000>;
4722 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4723 opp-peak-kBps = <4068000>;
4726 opp-342000000 {
4727 opp-hz = /bits/ 64 <342000000>;
4728 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4729 opp-peak-kBps = <2724000>;
4732 opp-257000000 {
4733 opp-hz = /bits/ 64 <257000000>;
4734 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4735 opp-peak-kBps = <1648000>;
4741 compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
4743 #iommu-cells = <1>;
4744 #global-interrupts = <2>;
4757 clock-names = "bus", "iface";
4759 power-domains = <&gpucc GPU_CX_GDSC>;
4763 compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
4768 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
4772 interrupt-names = "hfi", "gmu";
4778 clock-names = "gmu", "cxo", "axi", "memnoc";
4780 power-domains = <&gpucc GPU_CX_GDSC>,
4782 power-domain-names = "cx", "gx";
4786 operating-points-v2 = <&gmu_opp_table>;
4790 gmu_opp_table: opp-table {
4791 compatible = "operating-points-v2";
4793 opp-400000000 {
4794 opp-hz = /bits/ 64 <400000000>;
4795 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4798 opp-200000000 {
4799 opp-hz = /bits/ 64 <200000000>;
4800 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4805 dispcc: clock-controller@af00000 {
4806 compatible = "qcom,sdm845-dispcc";
4817 clock-names = "bi_tcxo",
4826 #clock-cells = <1>;
4827 #reset-cells = <1>;
4828 #power-domain-cells = <1>;
4831 pdc_intc: interrupt-controller@b220000 {
4832 compatible = "qcom,sdm845-pdc", "qcom,pdc";
4834 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
4835 #interrupt-cells = <2>;
4836 interrupt-parent = <&intc>;
4837 interrupt-controller;
4840 pdc_reset: reset-controller@b2e0000 {
4841 compatible = "qcom,sdm845-pdc-global";
4843 #reset-cells = <1>;
4846 tsens0: thermal-sensor@c263000 {
4847 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
4853 interrupt-names = "uplow", "critical";
4854 #thermal-sensor-cells = <1>;
4857 tsens1: thermal-sensor@c265000 {
4858 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
4864 interrupt-names = "uplow", "critical";
4865 #thermal-sensor-cells = <1>;
4868 aoss_reset: reset-controller@c2a0000 {
4869 compatible = "qcom,sdm845-aoss-cc";
4871 #reset-cells = <1>;
4874 aoss_qmp: power-controller@c300000 {
4875 compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp";
4880 #clock-cells = <0>;
4883 #cooling-cells = <2>;
4887 #cooling-cells = <2>;
4892 compatible = "qcom,sdm845-rpmh-stats";
4897 compatible = "qcom,spmi-pmic-arb";
4903 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4904 interrupt-names = "periph_irq";
4908 #address-cells = <2>;
4909 #size-cells = <0>;
4910 interrupt-controller;
4911 #interrupt-cells = <4>;
4912 cell-index = <0>;
4916 compatible = "qcom,sdm845-imem", "syscon", "simple-mfd";
4919 #address-cells = <1>;
4920 #size-cells = <1>;
4924 pil-reloc@94c {
4925 compatible = "qcom,pil-reloc-info";
4931 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
4933 #iommu-cells = <2>;
4934 #global-interrupts = <1>;
5002 lpasscc: clock-controller@17014000 {
5003 compatible = "qcom,sdm845-lpasscc";
5005 reg-names = "cc", "qdsp6ss";
5006 #clock-cells = <1>;
5011 compatible = "qcom,sdm845-gladiator-noc";
5013 #interconnect-cells = <2>;
5014 qcom,bcm-voters = <&apps_bcm_voter>;
5018 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
5025 compatible = "qcom,sdm845-apss-shared";
5027 #mbox-cells = <1>;
5032 compatible = "qcom,rpmh-rsc";
5036 reg-names = "drv-0", "drv-1", "drv-2";
5040 qcom,tcs-offset = <0xd00>;
5041 qcom,drv-id = <2>;
5042 qcom,tcs-config = <ACTIVE_TCS 2>,
5047 apps_bcm_voter: bcm-voter {
5048 compatible = "qcom,bcm-voter";
5051 rpmhcc: clock-controller {
5052 compatible = "qcom,sdm845-rpmh-clk";
5053 #clock-cells = <1>;
5054 clock-names = "xo";
5058 rpmhpd: power-controller {
5059 compatible = "qcom,sdm845-rpmhpd";
5060 #power-domain-cells = <1>;
5061 operating-points-v2 = <&rpmhpd_opp_table>;
5063 rpmhpd_opp_table: opp-table {
5064 compatible = "operating-points-v2";
5067 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5071 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5075 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5079 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5083 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5087 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5091 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5095 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5099 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5103 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5109 intc: interrupt-controller@17a00000 {
5110 compatible = "arm,gic-v3";
5111 #address-cells = <2>;
5112 #size-cells = <2>;
5114 #interrupt-cells = <3>;
5115 interrupt-controller;
5120 msi-controller@17a40000 {
5121 compatible = "arm,gic-v3-its";
5122 msi-controller;
5123 #msi-cells = <1>;
5129 slimbam: dma-controller@17184000 {
5130 compatible = "qcom,bam-v1.7.0";
5131 qcom,controlled-remotely;
5133 num-channels = <31>;
5135 #dma-cells = <1>;
5137 qcom,num-ees = <2>;
5142 #address-cells = <1>;
5143 #size-cells = <1>;
5145 compatible = "arm,armv7-timer-mem";
5149 frame-number = <0>;
5157 frame-number = <1>;
5164 frame-number = <2>;
5171 frame-number = <3>;
5178 frame-number = <4>;
5185 frame-number = <5>;
5192 frame-number = <6>;
5200 compatible = "qcom,sdm845-osm-l3";
5204 clock-names = "xo", "alternate";
5206 #interconnect-cells = <1>;
5210 compatible = "qcom,cpufreq-hw";
5212 reg-names = "freq-domain0", "freq-domain1";
5214 interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>;
5217 clock-names = "xo", "alternate";
5219 #freq-domain-cells = <1>;
5223 compatible = "qcom,wcn3990-wifi";
5226 reg-names = "membase";
5227 memory-region = <&wlan_msa_mem>;
5228 clock-names = "cxo_ref_clk_pin";
5247 thermal-zones {
5248 cpu0-thermal {
5249 polling-delay-passive = <250>;
5250 polling-delay = <1000>;
5252 thermal-sensors = <&tsens0 1>;
5255 cpu0_alert0: trip-point0 {
5261 cpu0_alert1: trip-point1 {
5275 cpu1-thermal {
5276 polling-delay-passive = <250>;
5277 polling-delay = <1000>;
5279 thermal-sensors = <&tsens0 2>;
5282 cpu1_alert0: trip-point0 {
5288 cpu1_alert1: trip-point1 {
5302 cpu2-thermal {
5303 polling-delay-passive = <250>;
5304 polling-delay = <1000>;
5306 thermal-sensors = <&tsens0 3>;
5309 cpu2_alert0: trip-point0 {
5315 cpu2_alert1: trip-point1 {
5329 cpu3-thermal {
5330 polling-delay-passive = <250>;
5331 polling-delay = <1000>;
5333 thermal-sensors = <&tsens0 4>;
5336 cpu3_alert0: trip-point0 {
5342 cpu3_alert1: trip-point1 {
5356 cpu4-thermal {
5357 polling-delay-passive = <250>;
5358 polling-delay = <1000>;
5360 thermal-sensors = <&tsens0 7>;
5363 cpu4_alert0: trip-point0 {
5369 cpu4_alert1: trip-point1 {
5383 cpu5-thermal {
5384 polling-delay-passive = <250>;
5385 polling-delay = <1000>;
5387 thermal-sensors = <&tsens0 8>;
5390 cpu5_alert0: trip-point0 {
5396 cpu5_alert1: trip-point1 {
5410 cpu6-thermal {
5411 polling-delay-passive = <250>;
5412 polling-delay = <1000>;
5414 thermal-sensors = <&tsens0 9>;
5417 cpu6_alert0: trip-point0 {
5423 cpu6_alert1: trip-point1 {
5437 cpu7-thermal {
5438 polling-delay-passive = <250>;
5439 polling-delay = <1000>;
5441 thermal-sensors = <&tsens0 10>;
5444 cpu7_alert0: trip-point0 {
5450 cpu7_alert1: trip-point1 {
5464 aoss0-thermal {
5465 polling-delay-passive = <250>;
5466 polling-delay = <1000>;
5468 thermal-sensors = <&tsens0 0>;
5471 aoss0_alert0: trip-point0 {
5479 cluster0-thermal {
5480 polling-delay-passive = <250>;
5481 polling-delay = <1000>;
5483 thermal-sensors = <&tsens0 5>;
5486 cluster0_alert0: trip-point0 {
5499 cluster1-thermal {
5500 polling-delay-passive = <250>;
5501 polling-delay = <1000>;
5503 thermal-sensors = <&tsens0 6>;
5506 cluster1_alert0: trip-point0 {
5519 gpu-top-thermal {
5520 polling-delay-passive = <250>;
5521 polling-delay = <1000>;
5523 thermal-sensors = <&tsens0 11>;
5526 gpu1_alert0: trip-point0 {
5534 gpu-bottom-thermal {
5535 polling-delay-passive = <250>;
5536 polling-delay = <1000>;
5538 thermal-sensors = <&tsens0 12>;
5541 gpu2_alert0: trip-point0 {
5549 aoss1-thermal {
5550 polling-delay-passive = <250>;
5551 polling-delay = <1000>;
5553 thermal-sensors = <&tsens1 0>;
5556 aoss1_alert0: trip-point0 {
5564 q6-modem-thermal {
5565 polling-delay-passive = <250>;
5566 polling-delay = <1000>;
5568 thermal-sensors = <&tsens1 1>;
5571 q6_modem_alert0: trip-point0 {
5579 mem-thermal {
5580 polling-delay-passive = <250>;
5581 polling-delay = <1000>;
5583 thermal-sensors = <&tsens1 2>;
5586 mem_alert0: trip-point0 {
5594 wlan-thermal {
5595 polling-delay-passive = <250>;
5596 polling-delay = <1000>;
5598 thermal-sensors = <&tsens1 3>;
5601 wlan_alert0: trip-point0 {
5609 q6-hvx-thermal {
5610 polling-delay-passive = <250>;
5611 polling-delay = <1000>;
5613 thermal-sensors = <&tsens1 4>;
5616 q6_hvx_alert0: trip-point0 {
5624 camera-thermal {
5625 polling-delay-passive = <250>;
5626 polling-delay = <1000>;
5628 thermal-sensors = <&tsens1 5>;
5631 camera_alert0: trip-point0 {
5639 video-thermal {
5640 polling-delay-passive = <250>;
5641 polling-delay = <1000>;
5643 thermal-sensors = <&tsens1 6>;
5646 video_alert0: trip-point0 {
5654 modem-thermal {
5655 polling-delay-passive = <250>;
5656 polling-delay = <1000>;
5658 thermal-sensors = <&tsens1 7>;
5661 modem_alert0: trip-point0 {