Lines Matching +full:0 +full:x1c02
75 reg = <0 0x80000000 0 0>;
84 reg = <0 0x85700000 0 0x600000>;
89 reg = <0 0x85e00000 0 0x100000>;
94 reg = <0 0x85fc0000 0 0x20000>;
100 reg = <0x0 0x85fe0000 0 0x20000>;
106 reg = <0x0 0x86000000 0 0x200000>;
112 reg = <0 0x86200000 0 0x2d00000>;
118 reg = <0 0x88f00000 0 0x200000>;
126 reg = <0 0x8ab00000 0 0x1400000>;
131 reg = <0 0x8bf00000 0 0x500000>;
136 reg = <0 0x8c400000 0 0x10000>;
141 reg = <0 0x8c410000 0 0x5000>;
146 reg = <0 0x8c415000 0 0x2000>;
151 reg = <0 0x8c500000 0 0x1a00000>;
156 reg = <0 0x8df00000 0 0x100000>;
161 reg = <0 0x8e000000 0 0x7800000>;
166 reg = <0 0x95800000 0 0x500000>;
171 reg = <0 0x95d00000 0 0x800000>;
176 reg = <0 0x96500000 0 0x200000>;
181 reg = <0 0x96700000 0 0x1400000>;
186 reg = <0 0x97b00000 0 0x100000>;
193 #size-cells = <0>;
195 CPU0: cpu@0 {
198 reg = <0x0 0x0>;
202 qcom,freq-domain = <&cpufreq_hw 0>;
222 reg = <0x0 0x100>;
226 qcom,freq-domain = <&cpufreq_hw 0>;
243 reg = <0x0 0x200>;
247 qcom,freq-domain = <&cpufreq_hw 0>;
264 reg = <0x0 0x300>;
268 qcom,freq-domain = <&cpufreq_hw 0>;
285 reg = <0x0 0x400>;
306 reg = <0x0 0x500>;
327 reg = <0x0 0x600>;
348 reg = <0x0 0x700>;
405 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
408 arm,psci-suspend-param = <0x40000004>;
415 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
418 arm,psci-suspend-param = <0x40000004>;
427 CLUSTER_SLEEP_0: cluster-sleep-0 {
430 arm,psci-suspend-param = <0x4100c244>;
709 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
715 #clock-cells = <0>;
722 #clock-cells = <0>;
737 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
751 qcom,smem-states = <&adsp_smp2p_out 0>;
767 #size-cells = <0>;
783 #size-cells = <0>;
795 #size-cells = <0>;
797 iommus = <&apps_smmu 0x1821 0x0>;
807 #sound-dai-cells = <0>;
818 #size-cells = <0>;
823 iommus = <&apps_smmu 0x1823 0x0>;
829 iommus = <&apps_smmu 0x1824 0x0>;
839 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
853 qcom,smem-states = <&cdsp_smp2p_out 0>;
869 #size-cells = <0>;
874 iommus = <&apps_smmu 0x1401 0x30>;
880 iommus = <&apps_smmu 0x1402 0x30>;
886 iommus = <&apps_smmu 0x1403 0x30>;
892 iommus = <&apps_smmu 0x1404 0x30>;
898 iommus = <&apps_smmu 0x1405 0x30>;
904 iommus = <&apps_smmu 0x1406 0x30>;
910 iommus = <&apps_smmu 0x1407 0x30>;
916 iommus = <&apps_smmu 0x1408 0x30>;
930 qcom,local-pid = <0>;
954 qcom,local-pid = <0>;
975 qcom,local-pid = <0>;
1006 qcom,local-pid = <0>;
1026 #power-domain-cells = <0>;
1032 #power-domain-cells = <0>;
1038 #power-domain-cells = <0>;
1044 #power-domain-cells = <0>;
1050 #power-domain-cells = <0>;
1056 #power-domain-cells = <0>;
1062 #power-domain-cells = <0>;
1068 #power-domain-cells = <0>;
1074 #power-domain-cells = <0>;
1079 soc: soc@0 {
1082 ranges = <0 0 0 0 0x10 0>;
1083 dma-ranges = <0 0 0 0 0x10 0>;
1088 reg = <0 0x00100000 0 0x1f0000>;
1106 reg = <0 0x00784000 0 0x8ff>;
1111 reg = <0x1eb 0x1>;
1116 reg = <0x1eb 0x2>;
1123 reg = <0 0x00793000 0 0x1000>;
1155 reg = <0 0x00800000 0 0x60000>;
1170 dma-channel-mask = <0xfa>;
1171 iommus = <&apps_smmu 0x0016 0x0>;
1177 reg = <0 0x008c0000 0 0x6000>;
1181 iommus = <&apps_smmu 0x3 0x0>;
1185 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>;
1191 reg = <0 0x00880000 0 0x4000>;
1195 pinctrl-0 = <&qup_i2c0_default>;
1198 #size-cells = <0>;
1201 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1202 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1203 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1205 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1206 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1213 reg = <0 0x00880000 0 0x4000>;
1217 pinctrl-0 = <&qup_spi0_default>;
1220 #size-cells = <0>;
1221 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1222 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1224 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1225 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1232 reg = <0 0x00880000 0 0x4000>;
1236 pinctrl-0 = <&qup_uart0_default>;
1240 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1241 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1248 reg = <0 0x00884000 0 0x4000>;
1252 pinctrl-0 = <&qup_i2c1_default>;
1255 #size-cells = <0>;
1258 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1259 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1260 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1262 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1270 reg = <0 0x00884000 0 0x4000>;
1274 pinctrl-0 = <&qup_spi1_default>;
1277 #size-cells = <0>;
1278 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1279 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1281 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1289 reg = <0 0x00884000 0 0x4000>;
1293 pinctrl-0 = <&qup_uart1_default>;
1297 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1298 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1305 reg = <0 0x00888000 0 0x4000>;
1309 pinctrl-0 = <&qup_i2c2_default>;
1312 #size-cells = <0>;
1315 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1316 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1317 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1319 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1327 reg = <0 0x00888000 0 0x4000>;
1331 pinctrl-0 = <&qup_spi2_default>;
1334 #size-cells = <0>;
1335 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1336 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1338 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1346 reg = <0 0x00888000 0 0x4000>;
1350 pinctrl-0 = <&qup_uart2_default>;
1354 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1355 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1362 reg = <0 0x0088c000 0 0x4000>;
1366 pinctrl-0 = <&qup_i2c3_default>;
1369 #size-cells = <0>;
1372 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1373 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1374 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1376 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1384 reg = <0 0x0088c000 0 0x4000>;
1388 pinctrl-0 = <&qup_spi3_default>;
1391 #size-cells = <0>;
1392 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1393 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1395 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1403 reg = <0 0x0088c000 0 0x4000>;
1407 pinctrl-0 = <&qup_uart3_default>;
1411 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1412 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1419 reg = <0 0x00890000 0 0x4000>;
1423 pinctrl-0 = <&qup_i2c4_default>;
1426 #size-cells = <0>;
1429 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1430 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1431 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1433 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1441 reg = <0 0x00890000 0 0x4000>;
1445 pinctrl-0 = <&qup_spi4_default>;
1448 #size-cells = <0>;
1449 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1450 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1452 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1460 reg = <0 0x00890000 0 0x4000>;
1464 pinctrl-0 = <&qup_uart4_default>;
1468 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1469 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1476 reg = <0 0x00894000 0 0x4000>;
1480 pinctrl-0 = <&qup_i2c5_default>;
1483 #size-cells = <0>;
1486 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1487 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1488 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1490 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1498 reg = <0 0x00894000 0 0x4000>;
1502 pinctrl-0 = <&qup_spi5_default>;
1505 #size-cells = <0>;
1506 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1507 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1509 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1517 reg = <0 0x00894000 0 0x4000>;
1521 pinctrl-0 = <&qup_uart5_default>;
1525 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1526 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1533 reg = <0 0x00898000 0 0x4000>;
1537 pinctrl-0 = <&qup_i2c6_default>;
1540 #size-cells = <0>;
1543 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1544 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1545 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1547 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1555 reg = <0 0x00898000 0 0x4000>;
1559 pinctrl-0 = <&qup_spi6_default>;
1562 #size-cells = <0>;
1563 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1564 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1566 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1574 reg = <0 0x00898000 0 0x4000>;
1578 pinctrl-0 = <&qup_uart6_default>;
1582 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1583 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1590 reg = <0 0x0089c000 0 0x4000>;
1594 pinctrl-0 = <&qup_i2c7_default>;
1597 #size-cells = <0>;
1605 reg = <0 0x0089c000 0 0x4000>;
1609 pinctrl-0 = <&qup_spi7_default>;
1612 #size-cells = <0>;
1613 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1614 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1616 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1624 reg = <0 0x0089c000 0 0x4000>;
1628 pinctrl-0 = <&qup_uart7_default>;
1632 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1633 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1639 gpi_dma1: dma-controller@0xa00000 {
1642 reg = <0 0x00a00000 0 0x60000>;
1657 dma-channel-mask = <0xfa>;
1658 iommus = <&apps_smmu 0x06d6 0x0>;
1664 reg = <0 0x00ac0000 0 0x6000>;
1668 iommus = <&apps_smmu 0x6c3 0x0>;
1672 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>;
1678 reg = <0 0x00a80000 0 0x4000>;
1682 pinctrl-0 = <&qup_i2c8_default>;
1685 #size-cells = <0>;
1688 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1689 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1690 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1692 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1693 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1700 reg = <0 0x00a80000 0 0x4000>;
1704 pinctrl-0 = <&qup_spi8_default>;
1707 #size-cells = <0>;
1708 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1709 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1711 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1712 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1719 reg = <0 0x00a80000 0 0x4000>;
1723 pinctrl-0 = <&qup_uart8_default>;
1727 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1728 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1735 reg = <0 0x00a84000 0 0x4000>;
1739 pinctrl-0 = <&qup_i2c9_default>;
1742 #size-cells = <0>;
1745 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1746 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1747 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1749 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1757 reg = <0 0x00a84000 0 0x4000>;
1761 pinctrl-0 = <&qup_spi9_default>;
1764 #size-cells = <0>;
1765 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1766 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1768 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1776 reg = <0 0x00a84000 0 0x4000>;
1780 pinctrl-0 = <&qup_uart9_default>;
1784 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1785 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1792 reg = <0 0x00a88000 0 0x4000>;
1796 pinctrl-0 = <&qup_i2c10_default>;
1799 #size-cells = <0>;
1802 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1803 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1804 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1806 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1814 reg = <0 0x00a88000 0 0x4000>;
1818 pinctrl-0 = <&qup_spi10_default>;
1821 #size-cells = <0>;
1822 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1823 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1825 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1833 reg = <0 0x00a88000 0 0x4000>;
1837 pinctrl-0 = <&qup_uart10_default>;
1841 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1842 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1849 reg = <0 0x00a8c000 0 0x4000>;
1853 pinctrl-0 = <&qup_i2c11_default>;
1856 #size-cells = <0>;
1859 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1860 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1861 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1863 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1871 reg = <0 0x00a8c000 0 0x4000>;
1875 pinctrl-0 = <&qup_spi11_default>;
1878 #size-cells = <0>;
1879 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1880 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1882 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1890 reg = <0 0x00a8c000 0 0x4000>;
1894 pinctrl-0 = <&qup_uart11_default>;
1898 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1899 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1906 reg = <0 0x00a90000 0 0x4000>;
1910 pinctrl-0 = <&qup_i2c12_default>;
1913 #size-cells = <0>;
1916 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1917 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1918 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1920 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1928 reg = <0 0x00a90000 0 0x4000>;
1932 pinctrl-0 = <&qup_spi12_default>;
1935 #size-cells = <0>;
1936 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1937 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1939 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1947 reg = <0 0x00a90000 0 0x4000>;
1951 pinctrl-0 = <&qup_uart12_default>;
1955 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1956 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1963 reg = <0 0x00a94000 0 0x4000>;
1967 pinctrl-0 = <&qup_i2c13_default>;
1970 #size-cells = <0>;
1973 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1974 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1975 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1977 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1985 reg = <0 0x00a94000 0 0x4000>;
1989 pinctrl-0 = <&qup_spi13_default>;
1992 #size-cells = <0>;
1993 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1994 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1996 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
2004 reg = <0 0x00a94000 0 0x4000>;
2008 pinctrl-0 = <&qup_uart13_default>;
2012 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2013 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2020 reg = <0 0x00a98000 0 0x4000>;
2024 pinctrl-0 = <&qup_i2c14_default>;
2027 #size-cells = <0>;
2030 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2031 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2032 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2034 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
2042 reg = <0 0x00a98000 0 0x4000>;
2046 pinctrl-0 = <&qup_spi14_default>;
2049 #size-cells = <0>;
2050 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2051 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2053 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
2061 reg = <0 0x00a98000 0 0x4000>;
2065 pinctrl-0 = <&qup_uart14_default>;
2069 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2070 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2077 reg = <0 0x00a9c000 0 0x4000>;
2081 pinctrl-0 = <&qup_i2c15_default>;
2084 #size-cells = <0>;
2088 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2089 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2090 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2092 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
2099 reg = <0 0x00a9c000 0 0x4000>;
2103 pinctrl-0 = <&qup_spi15_default>;
2106 #size-cells = <0>;
2107 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2108 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2110 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
2118 reg = <0 0x00a9c000 0 0x4000>;
2122 pinctrl-0 = <&qup_uart15_default>;
2126 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2127 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2135 reg = <0 0x01100000 0 0x31000>, <0 0x01300000 0 0x50000>;
2142 reg = <0 0x0114a000 0 0x1000>;
2159 opp-0 {
2179 reg = <0 0x01436400 0 0x600>;
2196 opp-0 {
2216 reg = <0 0x01c00000 0 0x2000>,
2217 <0 0x60000000 0 0xf1d>,
2218 <0 0x60000f20 0 0xa8>,
2219 <0 0x60100000 0 0x100000>;
2222 linux,pci-domain = <0>;
2223 bus-range = <0x00 0xff>;
2229 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
2230 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>;
2235 interrupt-map-mask = <0 0 0 0x7>;
2236 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2237 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2238 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2239 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2256 iommus = <&apps_smmu 0x1c10 0xf>;
2257 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
2258 <0x100 &apps_smmu 0x1c11 0x1>,
2259 <0x200 &apps_smmu 0x1c12 0x1>,
2260 <0x300 &apps_smmu 0x1c13 0x1>,
2261 <0x400 &apps_smmu 0x1c14 0x1>,
2262 <0x500 &apps_smmu 0x1c15 0x1>,
2263 <0x600 &apps_smmu 0x1c16 0x1>,
2264 <0x700 &apps_smmu 0x1c17 0x1>,
2265 <0x800 &apps_smmu 0x1c18 0x1>,
2266 <0x900 &apps_smmu 0x1c19 0x1>,
2267 <0xa00 &apps_smmu 0x1c1a 0x1>,
2268 <0xb00 &apps_smmu 0x1c1b 0x1>,
2269 <0xc00 &apps_smmu 0x1c1c 0x1>,
2270 <0xd00 &apps_smmu 0x1c1d 0x1>,
2271 <0xe00 &apps_smmu 0x1c1e 0x1>,
2272 <0xf00 &apps_smmu 0x1c1f 0x1>;
2287 reg = <0 0x01c06000 0 0x18c>;
2306 reg = <0 0x01c06200 0 0x128>,
2307 <0 0x01c06400 0 0x1fc>,
2308 <0 0x01c06800 0 0x218>,
2309 <0 0x01c06600 0 0x70>;
2313 #clock-cells = <0>;
2314 #phy-cells = <0>;
2321 reg = <0 0x01c08000 0 0x2000>,
2322 <0 0x40000000 0 0xf1d>,
2323 <0 0x40000f20 0 0xa8>,
2324 <0 0x40100000 0 0x100000>;
2328 bus-range = <0x00 0xff>;
2334 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
2335 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2340 interrupt-map-mask = <0 0 0 0x7>;
2341 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2342 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2343 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2344 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2366 iommus = <&apps_smmu 0x1c00 0xf>;
2367 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2368 <0x100 &apps_smmu 0x1c01 0x1>,
2369 <0x200 &apps_smmu 0x1c02 0x1>,
2370 <0x300 &apps_smmu 0x1c03 0x1>,
2371 <0x400 &apps_smmu 0x1c04 0x1>,
2372 <0x500 &apps_smmu 0x1c05 0x1>,
2373 <0x600 &apps_smmu 0x1c06 0x1>,
2374 <0x700 &apps_smmu 0x1c07 0x1>,
2375 <0x800 &apps_smmu 0x1c08 0x1>,
2376 <0x900 &apps_smmu 0x1c09 0x1>,
2377 <0xa00 &apps_smmu 0x1c0a 0x1>,
2378 <0xb00 &apps_smmu 0x1c0b 0x1>,
2379 <0xc00 &apps_smmu 0x1c0c 0x1>,
2380 <0xd00 &apps_smmu 0x1c0d 0x1>,
2381 <0xe00 &apps_smmu 0x1c0e 0x1>,
2382 <0xf00 &apps_smmu 0x1c0f 0x1>;
2397 reg = <0 0x01c0a000 0 0x800>;
2416 reg = <0 0x01c0a800 0 0x800>,
2417 <0 0x01c0a800 0 0x800>,
2418 <0 0x01c0b800 0 0x400>;
2422 #clock-cells = <0>;
2423 #phy-cells = <0>;
2430 reg = <0 0x01380000 0 0x27200>;
2437 reg = <0 0x014e0000 0 0x400>;
2444 reg = <0 0x01500000 0 0x5080>;
2451 reg = <0 0x01620000 0 0x18080>;
2458 reg = <0 0x016e0000 0 0x15080>;
2465 reg = <0 0x01700000 0 0x1f300>;
2472 reg = <0 0x01740000 0 0x1c100>;
2480 reg = <0 0x01d84000 0 0x2500>,
2481 <0 0x01d90000 0 0x8000>;
2492 iommus = <&apps_smmu 0x100 0xf>;
2516 <0 0>,
2517 <0 0>,
2519 <0 0>,
2520 <0 0>,
2521 <0 0>,
2522 <0 0>,
2523 <0 300000000>;
2530 reg = <0 0x01d87000 0 0x18c>;
2539 resets = <&ufs_mem_hc 0>;
2544 reg = <0 0x01d87400 0 0x108>,
2545 <0 0x01d87600 0 0x1e0>,
2546 <0 0x01d87c00 0 0x1dc>,
2547 <0 0x01d87800 0 0x108>,
2548 <0 0x01d87a00 0 0x1e0>;
2549 #phy-cells = <0>;
2555 reg = <0 0x01dc4000 0 0x24000>;
2560 qcom,ee = <0>;
2562 iommus = <&apps_smmu 0x704 0x1>,
2563 <&apps_smmu 0x706 0x1>,
2564 <&apps_smmu 0x714 0x1>,
2565 <&apps_smmu 0x716 0x1>;
2570 reg = <0 0x01dfa000 0 0x6000>;
2577 iommus = <&apps_smmu 0x704 0x1>,
2578 <&apps_smmu 0x706 0x1>,
2579 <&apps_smmu 0x714 0x1>,
2580 <&apps_smmu 0x716 0x1>;
2586 iommus = <&apps_smmu 0x720 0x0>,
2587 <&apps_smmu 0x722 0x0>;
2588 reg = <0 0x1e40000 0 0x7000>,
2589 <0 0x1e47000 0 0x2000>,
2590 <0 0x1e04000 0 0x2c000>;
2597 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2607 interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>,
2608 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
2609 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
2614 qcom,smem-states = <&ipa_smp2p_out 0>,
2624 reg = <0 0x01f40000 0 0x20000>;
2630 reg = <0 0x01f60000 0 0x20000>;
2635 reg = <0 0x03400000 0 0xc00000>;
2641 gpio-ranges = <&tlmm 0 0 151>;
3213 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
3218 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3240 qcom,smem-states = <&modem_smp2p_out 0>;
3247 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
3274 reg = <0 0x05090000 0 0x9000>;
3288 reg = <0 0x06002000 0 0x1000>,
3289 <0 0x16280000 0 0x180000>;
3307 reg = <0 0x06041000 0 0x1000>;
3323 #size-cells = <0>;
3336 reg = <0 0x06043000 0 0x1000>;
3352 #size-cells = <0>;
3366 reg = <0 0x06045000 0 0x1000>;
3381 #size-cells = <0>;
3383 port@0 {
3384 reg = <0>;
3403 reg = <0 0x06046000 0 0x1000>;
3427 reg = <0 0x06047000 0 0x1000>;
3443 #size-cells = <0>;
3457 reg = <0 0x06048000 0 0x1000>;
3475 reg = <0 0x07040000 0 0x1000>;
3495 reg = <0 0x07140000 0 0x1000>;
3515 reg = <0 0x07240000 0 0x1000>;
3535 reg = <0 0x07340000 0 0x1000>;
3555 reg = <0 0x07440000 0 0x1000>;
3575 reg = <0 0x07540000 0 0x1000>;
3595 reg = <0 0x07640000 0 0x1000>;
3615 reg = <0 0x07740000 0 0x1000>;
3635 reg = <0 0x07800000 0 0x1000>;
3651 #size-cells = <0>;
3653 port@0 {
3654 reg = <0>;
3721 reg = <0 0x07810000 0 0x1000>;
3747 reg = <0 0x08804000 0 0x1000>;
3757 iommus = <&apps_smmu 0xa0 0xf>;
3814 reg = <0 0x088df000 0 0x600>;
3816 #size-cells = <0>;
3828 reg = <0 0x171c0000 0 0x2c000>;
3831 qcom,apps-ch-pipes = <0x780000>;
3832 qcom,ea-pc = <0x270>;
3838 iommus = <&apps_smmu 0x1806 0x0>;
3840 #size-cells = <0>;
3845 #size-cells = <0>;
3847 wcd9340_ifd: ifd@0{
3849 reg = <0 0>;
3854 reg = <1 0>;
3863 #clock-cells = <0>;
3878 reg = <0x42 0x2>;
3883 reg = <0xc85 0x40>;
3888 qcom,ports-sinterval-low =/bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>;
3889 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >;
3890 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>;
3896 #size-cells = <0>;
3906 reg = <0 0x17d70800 0 0x400>;
3918 reg = <0 0x17d78800 0 0x400>;
3933 reg = <0 0x088e2000 0 0x400>;
3935 #phy-cells = <0>;
3948 reg = <0 0x088e3000 0 0x400>;
3950 #phy-cells = <0>;
3963 reg = <0 0x088e9000 0 0x18c>,
3964 <0 0x088e8000 0 0x10>;
3981 reg = <0 0x088e9200 0 0x128>,
3982 <0 0x088e9400 0 0x200>,
3983 <0 0x088e9c00 0 0x218>,
3984 <0 0x088e9600 0 0x128>,
3985 <0 0x088e9800 0 0x200>,
3986 <0 0x088e9a00 0 0x100>;
3987 #clock-cells = <0>;
3988 #phy-cells = <0>;
3997 reg = <0 0x088eb000 0 0x18c>;
4014 reg = <0 0x088eb200 0 0x128>,
4015 <0 0x088eb400 0 0x1fc>,
4016 <0 0x088eb800 0 0x218>,
4017 <0 0x088eb600 0 0x70>;
4018 #clock-cells = <0>;
4019 #phy-cells = <0>;
4028 reg = <0 0x0a6f8800 0 0x400>;
4061 interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>,
4062 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
4067 reg = <0 0x0a600000 0 0xcd00>;
4069 iommus = <&apps_smmu 0x740 0>;
4079 reg = <0 0x0a8f8800 0 0x400>;
4112 interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>,
4113 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
4118 reg = <0 0x0a800000 0 0xcd00>;
4120 iommus = <&apps_smmu 0x760 0>;
4130 reg = <0 0x0aa00000 0 0xff000>;
4148 iommus = <&apps_smmu 0x10a0 0x8>,
4149 <&apps_smmu 0x10b0 0x0>;
4151 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>,
4152 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
4202 reg = <0 0x0ab00000 0 0x10000>;
4213 reg = <0 0xacb3000 0 0x1000>,
4214 <0 0xacba000 0 0x1000>,
4215 <0 0xacc8000 0 0x1000>,
4216 <0 0xac65000 0 0x1000>,
4217 <0 0xac66000 0 0x1000>,
4218 <0 0xac67000 0 0x1000>,
4219 <0 0xac68000 0 0x1000>,
4220 <0 0xacaf000 0 0x4000>,
4221 <0 0xacb6000 0 0x4000>,
4222 <0 0xacc4000 0 0x4000>;
4332 iommus = <&apps_smmu 0x0808 0x0>,
4333 <&apps_smmu 0x0810 0x8>,
4334 <&apps_smmu 0x0c08 0x0>,
4335 <&apps_smmu 0x0c10 0x8>;
4341 #size-cells = <0>;
4348 #size-cells = <0>;
4350 reg = <0 0x0ac4a000 0 0x4000>;
4372 pinctrl-0 = <&cci0_default &cci1_default>;
4377 cci_i2c0: i2c-bus@0 {
4378 reg = <0>;
4381 #size-cells = <0>;
4388 #size-cells = <0>;
4394 reg = <0 0x0ad00000 0 0x10000>;
4433 reg = <0 0x0ae00000 0 0x1000>;
4446 interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>,
4447 <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>;
4450 iommus = <&apps_smmu 0x880 0x8>,
4451 <&apps_smmu 0xc80 0x8>;
4461 reg = <0 0x0ae01000 0 0x8f000>,
4462 <0 0x0aeb0000 0 0x2008>;
4478 interrupts = <0>;
4482 #size-cells = <0>;
4484 port@0 {
4485 reg = <0>;
4526 reg = <0 0x0ae94000 0 0x400>;
4545 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
4556 #size-cells = <0>;
4560 #size-cells = <0>;
4562 port@0 {
4563 reg = <0>;
4579 reg = <0 0x0ae94400 0 0x200>,
4580 <0 0x0ae94600 0 0x280>,
4581 <0 0x0ae94a00 0 0x1e0>;
4587 #phy-cells = <0>;
4598 reg = <0 0x0ae96000 0 0x400>;
4617 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
4628 #size-cells = <0>;
4632 #size-cells = <0>;
4634 port@0 {
4635 reg = <0>;
4651 reg = <0 0x0ae96400 0 0x200>,
4652 <0 0x0ae96600 0 0x280>,
4653 <0 0x0ae96a00 0 0x10e>;
4659 #phy-cells = <0>;
4672 reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>;
4682 iommus = <&adreno_smmu 0>;
4688 interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>;
4742 reg = <0 0x5040000 0 0x10000>;
4765 reg = <0 0x506a000 0 0x30000>,
4766 <0 0xb280000 0 0x10000>,
4767 <0 0xb480000 0 0x10000>;
4807 reg = <0 0x0af00000 0 0x10000>;
4811 <&dsi0_phy 0>,
4813 <&dsi1_phy 0>,
4815 <0>,
4816 <0>;
4833 reg = <0 0x0b220000 0 0x30000>;
4834 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
4842 reg = <0 0x0b2e0000 0 0x20000>;
4848 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4849 <0 0x0c222000 0 0x1ff>; /* SROT */
4859 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4860 <0 0x0c223000 0 0x1ff>; /* SROT */
4870 reg = <0 0x0c2a0000 0 0x31000>;
4876 reg = <0 0x0c300000 0 0x400>;
4878 mboxes = <&apss_shared 0>;
4880 #clock-cells = <0>;
4893 reg = <0 0x0c3f0000 0 0x400>;
4898 reg = <0 0x0c440000 0 0x1100>,
4899 <0 0x0c600000 0 0x2000000>,
4900 <0 0x0e600000 0 0x100000>,
4901 <0 0x0e700000 0 0xa0000>,
4902 <0 0x0c40a000 0 0x26000>;
4906 qcom,ee = <0>;
4907 qcom,channel = <0>;
4909 #size-cells = <0>;
4912 cell-index = <0>;
4917 reg = <0 0x146bf000 0 0x1000>;
4922 ranges = <0 0 0x146bf000 0x1000>;
4926 reg = <0x94c 0xc8>;
4932 reg = <0 0x15000000 0 0x80000>;
5004 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
5012 reg = <0 0x17900000 0 0xd080>;
5019 reg = <0 0x17980000 0 0x1000>;
5021 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
5026 reg = <0 0x17990000 0 0x1000>;
5033 reg = <0 0x179c0000 0 0x10000>,
5034 <0 0x179d0000 0 0x10000>,
5035 <0 0x179e0000 0 0x10000>;
5036 reg-names = "drv-0", "drv-1", "drv-2";
5040 qcom,tcs-offset = <0xd00>;
5116 reg = <0 0x17a00000 0 0x10000>, /* GICD */
5117 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
5124 reg = <0 0x17a40000 0 0x20000>;
5132 reg = <0 0x17184000 0 0x2a000>;
5138 iommus = <&apps_smmu 0x1806 0x0>;
5144 ranges = <0 0 0 0x20000000>;
5146 reg = <0 0x17c90000 0 0x1000>;
5149 frame-number = <0>;
5152 reg = <0x17ca0000 0x1000>,
5153 <0x17cb0000 0x1000>;
5159 reg = <0x17cc0000 0x1000>;
5166 reg = <0x17cd0000 0x1000>;
5173 reg = <0x17ce0000 0x1000>;
5180 reg = <0x17cf0000 0x1000>;
5187 reg = <0x17d00000 0x1000>;
5194 reg = <0x17d10000 0x1000>;
5201 reg = <0 0x17d41000 0 0x1400>;
5211 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
5214 interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>;
5225 reg = <0 0x18800000 0 0x800000>;
5243 iommus = <&apps_smmu 0x0040 0x1>;
5468 thermal-sensors = <&tsens0 0>;
5553 thermal-sensors = <&tsens1 0>;