Lines Matching +full:msm +full:- +full:uartdm +full:- +full:v1
1 // SPDX-License-Identifier: BSD-3-Clause
7 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
8 #include <dt-bindings/clock/qcom,gpucc-sdm660.h>
9 #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
10 #include <dt-bindings/clock/qcom,rpmcc.h>
11 #include <dt-bindings/interconnect/qcom,sdm660.h>
12 #include <dt-bindings/power/qcom-rpmpd.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/soc/qcom,apr.h>
18 interrupt-parent = <&intc>;
20 #address-cells = <2>;
21 #size-cells = <2>;
31 xo_board: xo-board {
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
34 clock-frequency = <19200000>;
35 clock-output-names = "xo_board";
38 sleep_clk: sleep-clk {
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
41 clock-frequency = <32764>;
42 clock-output-names = "sleep_clk";
47 #address-cells = <2>;
48 #size-cells = <0>;
52 compatible = "arm,cortex-a53";
54 enable-method = "psci";
55 cpu-idle-states = <&PERF_CPU_SLEEP_0
60 capacity-dmips-mhz = <1126>;
61 #cooling-cells = <2>;
62 next-level-cache = <&L2_1>;
63 L2_1: l2-cache {
65 cache-level = <2>;
71 compatible = "arm,cortex-a53";
73 enable-method = "psci";
74 cpu-idle-states = <&PERF_CPU_SLEEP_0
79 capacity-dmips-mhz = <1126>;
80 #cooling-cells = <2>;
81 next-level-cache = <&L2_1>;
86 compatible = "arm,cortex-a53";
88 enable-method = "psci";
89 cpu-idle-states = <&PERF_CPU_SLEEP_0
94 capacity-dmips-mhz = <1126>;
95 #cooling-cells = <2>;
96 next-level-cache = <&L2_1>;
101 compatible = "arm,cortex-a53";
103 enable-method = "psci";
104 cpu-idle-states = <&PERF_CPU_SLEEP_0
109 capacity-dmips-mhz = <1126>;
110 #cooling-cells = <2>;
111 next-level-cache = <&L2_1>;
116 compatible = "arm,cortex-a53";
118 enable-method = "psci";
119 cpu-idle-states = <&PWR_CPU_SLEEP_0
124 capacity-dmips-mhz = <1024>;
125 #cooling-cells = <2>;
126 next-level-cache = <&L2_0>;
127 L2_0: l2-cache {
129 cache-level = <2>;
135 compatible = "arm,cortex-a53";
137 enable-method = "psci";
138 cpu-idle-states = <&PWR_CPU_SLEEP_0
143 capacity-dmips-mhz = <1024>;
144 #cooling-cells = <2>;
145 next-level-cache = <&L2_0>;
150 compatible = "arm,cortex-a53";
152 enable-method = "psci";
153 cpu-idle-states = <&PWR_CPU_SLEEP_0
158 capacity-dmips-mhz = <1024>;
159 #cooling-cells = <2>;
160 next-level-cache = <&L2_0>;
165 compatible = "arm,cortex-a53";
167 enable-method = "psci";
168 cpu-idle-states = <&PWR_CPU_SLEEP_0
173 capacity-dmips-mhz = <1024>;
174 #cooling-cells = <2>;
175 next-level-cache = <&L2_0>;
178 cpu-map {
216 idle-states {
217 entry-method = "psci";
219 PWR_CPU_SLEEP_0: cpu-sleep-0-0 {
220 compatible = "arm,idle-state";
221 idle-state-name = "pwr-retention";
222 arm,psci-suspend-param = <0x40000002>;
223 entry-latency-us = <338>;
224 exit-latency-us = <423>;
225 min-residency-us = <200>;
228 PWR_CPU_SLEEP_1: cpu-sleep-0-1 {
229 compatible = "arm,idle-state";
230 idle-state-name = "pwr-power-collapse";
231 arm,psci-suspend-param = <0x40000003>;
232 entry-latency-us = <515>;
233 exit-latency-us = <1821>;
234 min-residency-us = <1000>;
235 local-timer-stop;
238 PERF_CPU_SLEEP_0: cpu-sleep-1-0 {
239 compatible = "arm,idle-state";
240 idle-state-name = "perf-retention";
241 arm,psci-suspend-param = <0x40000002>;
242 entry-latency-us = <154>;
243 exit-latency-us = <87>;
244 min-residency-us = <200>;
247 PERF_CPU_SLEEP_1: cpu-sleep-1-1 {
248 compatible = "arm,idle-state";
249 idle-state-name = "perf-power-collapse";
250 arm,psci-suspend-param = <0x40000003>;
251 entry-latency-us = <262>;
252 exit-latency-us = <301>;
253 min-residency-us = <1000>;
254 local-timer-stop;
257 PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 {
258 compatible = "arm,idle-state";
259 idle-state-name = "pwr-cluster-dynamic-retention";
260 arm,psci-suspend-param = <0x400000F2>;
261 entry-latency-us = <284>;
262 exit-latency-us = <384>;
263 min-residency-us = <9987>;
264 local-timer-stop;
267 PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 {
268 compatible = "arm,idle-state";
269 idle-state-name = "pwr-cluster-retention";
270 arm,psci-suspend-param = <0x400000F3>;
271 entry-latency-us = <338>;
272 exit-latency-us = <423>;
273 min-residency-us = <9987>;
274 local-timer-stop;
277 PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 {
278 compatible = "arm,idle-state";
279 idle-state-name = "pwr-cluster-retention";
280 arm,psci-suspend-param = <0x400000F4>;
281 entry-latency-us = <515>;
282 exit-latency-us = <1821>;
283 min-residency-us = <9987>;
284 local-timer-stop;
287 PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 {
288 compatible = "arm,idle-state";
289 idle-state-name = "perf-cluster-dynamic-retention";
290 arm,psci-suspend-param = <0x400000F2>;
291 entry-latency-us = <272>;
292 exit-latency-us = <329>;
293 min-residency-us = <9987>;
294 local-timer-stop;
297 PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 {
298 compatible = "arm,idle-state";
299 idle-state-name = "perf-cluster-retention";
300 arm,psci-suspend-param = <0x400000F3>;
301 entry-latency-us = <332>;
302 exit-latency-us = <368>;
303 min-residency-us = <9987>;
304 local-timer-stop;
307 PERF_CLUSTER_SLEEP_2: cluster-sleep-1-2 {
308 compatible = "arm,idle-state";
309 idle-state-name = "perf-cluster-retention";
310 arm,psci-suspend-param = <0x400000F4>;
311 entry-latency-us = <545>;
312 exit-latency-us = <1609>;
313 min-residency-us = <9987>;
314 local-timer-stop;
321 compatible = "qcom,scm-msm8998", "qcom,scm";
332 compatible = "arm,armv8-pmuv3";
337 compatible = "arm,psci-1.0";
341 reserved-memory {
342 #address-cells = <2>;
343 #size-cells = <2>;
346 wlan_msa_guard: wlan-msa-guard@85600000 {
348 no-map;
351 wlan_msa_mem: wlan-msa-mem@85700000 {
353 no-map;
356 qhee_code: qhee-code@85800000 {
358 no-map;
362 compatible = "qcom,rmtfs-mem";
364 no-map;
366 qcom,client-id = <1>;
370 smem_region: smem-mem@86000000 {
372 no-map;
377 no-map;
382 no-map;
387 no-map;
392 no-map;
397 no-map;
402 no-map;
405 adsp_mem: adsp-region@f6000000 {
407 no-map;
410 qseecom_mem: qseecom-region@f6800000 {
412 no-map;
416 compatible = "shared-dma-pool";
418 no-map;
422 rpm-glink {
423 compatible = "qcom,glink-rpm";
426 qcom,rpm-msg-ram = <&rpm_msg_ram>;
429 rpm_requests: rpm-requests {
430 compatible = "qcom,rpm-sdm660";
431 qcom,glink-channels = "rpm_requests";
433 rpmcc: clock-controller {
434 compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc";
435 #clock-cells = <1>;
438 rpmpd: power-controller {
439 compatible = "qcom,sdm660-rpmpd";
440 #power-domain-cells = <1>;
441 operating-points-v2 = <&rpmpd_opp_table>;
443 rpmpd_opp_table: opp-table {
444 compatible = "operating-points-v2";
447 opp-level = <RPM_SMD_LEVEL_RETENTION>;
451 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
455 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
459 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
463 opp-level = <RPM_SMD_LEVEL_SVS>;
467 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
471 opp-level = <RPM_SMD_LEVEL_NOM>;
475 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
479 opp-level = <RPM_SMD_LEVEL_TURBO>;
488 memory-region = <&smem_region>;
492 smp2p-adsp {
497 qcom,local-pid = <0>;
498 qcom,remote-pid = <2>;
500 adsp_smp2p_out: master-kernel {
501 qcom,entry-name = "master-kernel";
502 #qcom,smem-state-cells = <1>;
505 adsp_smp2p_in: slave-kernel {
506 qcom,entry-name = "slave-kernel";
507 interrupt-controller;
508 #interrupt-cells = <2>;
512 smp2p-mpss {
517 qcom,local-pid = <0>;
518 qcom,remote-pid = <1>;
520 modem_smp2p_out: master-kernel {
521 qcom,entry-name = "master-kernel";
522 #qcom,smem-state-cells = <1>;
525 modem_smp2p_in: slave-kernel {
526 qcom,entry-name = "slave-kernel";
527 interrupt-controller;
528 #interrupt-cells = <2>;
533 #address-cells = <1>;
534 #size-cells = <1>;
536 compatible = "simple-bus";
538 gcc: clock-controller@100000 {
539 compatible = "qcom,gcc-sdm630";
540 #clock-cells = <1>;
541 #reset-cells = <1>;
542 #power-domain-cells = <1>;
545 clock-names = "xo", "sleep_clk";
551 compatible = "qcom,rpm-msg-ram";
556 compatible = "qcom,sdm630-qfprom", "qcom,qfprom";
558 #address-cells = <1>;
559 #size-cells = <1>;
561 qusb2_hstx_trim: hstx-trim@240 {
566 gpu_speed_bin: gpu-speed-bin@41a0 {
573 compatible = "qcom,prng-ee";
576 clock-names = "core";
580 compatible = "qcom,sdm660-bimc";
582 #interconnect-cells = <1>;
583 clock-names = "bus", "bus_a";
594 compatible = "qcom,sdm660-cnoc";
596 #interconnect-cells = <1>;
597 clock-names = "bus", "bus_a";
603 compatible = "qcom,sdm660-snoc";
605 #interconnect-cells = <1>;
606 clock-names = "bus", "bus_a";
612 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
615 assigned-clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
616 assigned-clock-rates = <1000>;
618 clock-names = "bus";
619 #global-interrupts = <2>;
620 #iommu-cells = <1>;
660 compatible = "qcom,sdm660-a2noc";
662 #interconnect-cells = <1>;
663 clock-names = "bus",
680 compatible = "qcom,sdm660-mnoc";
682 #interconnect-cells = <1>;
683 clock-names = "bus", "bus_a", "iface";
689 tsens: thermal-sensor@10ae000 {
690 compatible = "qcom,sdm630-tsens", "qcom,tsens-v2";
696 interrupt-names = "uplow", "critical";
697 #thermal-sensor-cells = <1>;
701 compatible = "qcom,tcsr-mutex";
703 #hwlock-cells = <1>;
707 compatible = "qcom,sdm630-tcsr", "syscon";
712 compatible = "qcom,sdm630-pinctrl";
716 reg-names = "south", "center", "north";
718 gpio-controller;
719 gpio-ranges = <&tlmm 0 0 114>;
720 #gpio-cells = <2>;
721 interrupt-controller;
722 #interrupt-cells = <2>;
724 blsp1_uart1_default: blsp1-uart1-default {
726 drive-strength = <2>;
727 bias-disable;
730 blsp1_uart1_sleep: blsp1-uart1-sleep {
732 drive-strength = <2>;
733 bias-disable;
736 blsp1_uart2_default: blsp1-uart2-default {
738 drive-strength = <2>;
739 bias-disable;
742 blsp2_uart1_default: blsp2-uart1-active {
743 tx-rts {
746 drive-strength = <2>;
747 bias-disable;
757 drive-strength = <2>;
758 bias-pull-up;
765 drive-strength = <2>;
766 bias-pull-down;
770 blsp2_uart1_sleep: blsp2-uart1-sleep {
774 drive-strength = <2>;
775 bias-pull-up;
778 rx-cts-rts {
781 drive-strength = <2>;
782 bias-no-pull;
786 i2c1_default: i2c1-default {
789 drive-strength = <2>;
790 bias-disable;
793 i2c1_sleep: i2c1-sleep {
796 drive-strength = <2>;
797 bias-pull-up;
800 i2c2_default: i2c2-default {
803 drive-strength = <2>;
804 bias-disable;
807 i2c2_sleep: i2c2-sleep {
810 drive-strength = <2>;
811 bias-pull-up;
814 i2c3_default: i2c3-default {
817 drive-strength = <2>;
818 bias-disable;
821 i2c3_sleep: i2c3-sleep {
824 drive-strength = <2>;
825 bias-pull-up;
828 i2c4_default: i2c4-default {
831 drive-strength = <2>;
832 bias-disable;
835 i2c4_sleep: i2c4-sleep {
838 drive-strength = <2>;
839 bias-pull-up;
842 i2c5_default: i2c5-default {
845 drive-strength = <2>;
846 bias-disable;
849 i2c5_sleep: i2c5-sleep {
852 drive-strength = <2>;
853 bias-pull-up;
856 i2c6_default: i2c6-default {
859 drive-strength = <2>;
860 bias-disable;
863 i2c6_sleep: i2c6-sleep {
866 drive-strength = <2>;
867 bias-pull-up;
870 i2c7_default: i2c7-default {
873 drive-strength = <2>;
874 bias-disable;
877 i2c7_sleep: i2c7-sleep {
880 drive-strength = <2>;
881 bias-pull-up;
884 i2c8_default: i2c8-default {
887 drive-strength = <2>;
888 bias-disable;
891 i2c8_sleep: i2c8-sleep {
894 drive-strength = <2>;
895 bias-pull-up;
906 bias-pull-up;
907 drive-strength = <2>;
919 bias-pull-up;
920 drive-strength = <2>;
924 sdc1_state_on: sdc1-on {
927 bias-disable;
928 drive-strength = <16>;
933 bias-pull-up;
934 drive-strength = <10>;
939 bias-pull-up;
940 drive-strength = <10>;
945 bias-pull-down;
949 sdc1_state_off: sdc1-off {
952 bias-disable;
953 drive-strength = <2>;
958 bias-pull-up;
959 drive-strength = <2>;
964 bias-pull-up;
965 drive-strength = <2>;
970 bias-pull-down;
974 sdc2_state_on: sdc2-on {
977 bias-disable;
978 drive-strength = <16>;
983 bias-pull-up;
984 drive-strength = <10>;
989 bias-pull-up;
990 drive-strength = <10>;
994 sdc2_state_off: sdc2-off {
997 bias-disable;
998 drive-strength = <2>;
1003 bias-pull-up;
1004 drive-strength = <2>;
1009 bias-pull-up;
1010 drive-strength = <2>;
1016 compatible = "qcom,adreno-508.0", "qcom,adreno";
1019 reg-names = "kgsl_3d0_reg_memory";
1030 clock-names = "iface",
1037 power-domains = <&rpmpd SDM660_VDDMX>;
1040 nvmem-cells = <&gpu_speed_bin>;
1041 nvmem-cell-names = "speed_bin";
1044 interconnect-names = "gfx-mem";
1046 operating-points-v2 = <&gpu_sdm630_opp_table>;
1050 gpu_sdm630_opp_table: opp-table {
1051 compatible = "operating-points-v2";
1052 opp-775000000 {
1053 opp-hz = /bits/ 64 <775000000>;
1054 opp-level = <RPM_SMD_LEVEL_TURBO>;
1055 opp-peak-kBps = <5412000>;
1056 opp-supported-hw = <0xA2>;
1058 opp-647000000 {
1059 opp-hz = /bits/ 64 <647000000>;
1060 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
1061 opp-peak-kBps = <4068000>;
1062 opp-supported-hw = <0xFF>;
1064 opp-588000000 {
1065 opp-hz = /bits/ 64 <588000000>;
1066 opp-level = <RPM_SMD_LEVEL_NOM>;
1067 opp-peak-kBps = <3072000>;
1068 opp-supported-hw = <0xFF>;
1070 opp-465000000 {
1071 opp-hz = /bits/ 64 <465000000>;
1072 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
1073 opp-peak-kBps = <2724000>;
1074 opp-supported-hw = <0xFF>;
1076 opp-370000000 {
1077 opp-hz = /bits/ 64 <370000000>;
1078 opp-level = <RPM_SMD_LEVEL_SVS>;
1079 opp-peak-kBps = <2188000>;
1080 opp-supported-hw = <0xFF>;
1082 opp-240000000 {
1083 opp-hz = /bits/ 64 <240000000>;
1084 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
1085 opp-peak-kBps = <1648000>;
1086 opp-supported-hw = <0xFF>;
1088 opp-160000000 {
1089 opp-hz = /bits/ 64 <160000000>;
1090 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
1091 opp-peak-kBps = <1200000>;
1092 opp-supported-hw = <0xFF>;
1098 compatible = "qcom,sdm630-smmu-v2",
1099 "qcom,adreno-smmu", "qcom,smmu-v2";
1109 power-domains = <&gpucc GPU_GX_GDSC>;
1113 clock-names = "iface", "mem", "mem_iface";
1114 #global-interrupts = <2>;
1115 #iommu-cells = <1>;
1133 gpucc: clock-controller@5065000 {
1134 compatible = "qcom,gpucc-sdm630";
1135 #clock-cells = <1>;
1136 #reset-cells = <1>;
1137 #power-domain-cells = <1>;
1143 clock-names = "xo",
1150 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
1152 #iommu-cells = <1>;
1154 #global-interrupts = <2>;
1181 compatible = "qcom,rpm-stats";
1186 compatible = "qcom,spmi-pmic-arb";
1192 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1193 interrupt-names = "periph_irq";
1197 #address-cells = <2>;
1198 #size-cells = <0>;
1199 interrupt-controller;
1200 #interrupt-cells = <4>;
1201 cell-index = <0>;
1205 compatible = "qcom,sdm660-dwc3", "qcom,dwc3";
1208 #address-cells = <1>;
1209 #size-cells = <1>;
1218 clock-names = "cfg_noc",
1225 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1228 assigned-clock-rates = <19200000>, <120000000>,
1233 interrupt-names = "hs_phy_irq", "ss_phy_irq";
1235 power-domains = <&gcc USB_30_GDSC>;
1236 qcom,select-utmi-as-pipe-clk;
1251 maximum-speed = "high-speed";
1253 phy-names = "usb2-phy";
1254 snps,hird-threshold = /bits/ 8 <0>;
1259 compatible = "qcom,sdm660-qusb2-phy";
1261 #phy-cells = <0>;
1265 clock-names = "cfg_ahb", "ref";
1268 nvmem-cells = <&qusb2_hstx_trim>;
1273 compatible = "qcom,sdm660-qusb2-phy";
1275 #phy-cells = <0>;
1279 clock-names = "cfg_ahb", "ref";
1282 nvmem-cells = <&qusb2_hstx_trim>;
1287 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
1289 reg-names = "hc";
1293 interrupt-names = "hc_irq", "pwr_irq";
1295 bus-width = <4>;
1300 clock-names = "iface", "core", "xo";
1305 interconnect-names = "sdhc-ddr","cpu-sdhc";
1306 operating-points-v2 = <&sdhc2_opp_table>;
1308 pinctrl-names = "default", "sleep";
1309 pinctrl-0 = <&sdc2_state_on>;
1310 pinctrl-1 = <&sdc2_state_off>;
1311 power-domains = <&rpmpd SDM660_VDDCX>;
1315 sdhc2_opp_table: opp-table {
1316 compatible = "operating-points-v2";
1318 opp-50000000 {
1319 opp-hz = /bits/ 64 <50000000>;
1320 required-opps = <&rpmpd_opp_low_svs>;
1321 opp-peak-kBps = <200000 140000>;
1322 opp-avg-kBps = <130718 133320>;
1324 opp-100000000 {
1325 opp-hz = /bits/ 64 <100000000>;
1326 required-opps = <&rpmpd_opp_svs>;
1327 opp-peak-kBps = <250000 160000>;
1328 opp-avg-kBps = <196078 150000>;
1330 opp-200000000 {
1331 opp-hz = /bits/ 64 <200000000>;
1332 required-opps = <&rpmpd_opp_nom>;
1333 opp-peak-kBps = <4096000 4096000>;
1334 opp-avg-kBps = <1338562 1338562>;
1340 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
1344 reg-names = "hc", "cqhci", "ice";
1348 interrupt-names = "hc_irq", "pwr_irq";
1354 clock-names = "iface", "core", "xo", "ice";
1358 interconnect-names = "sdhc-ddr", "cpu-sdhc";
1359 operating-points-v2 = <&sdhc1_opp_table>;
1360 pinctrl-names = "default", "sleep";
1361 pinctrl-0 = <&sdc1_state_on>;
1362 pinctrl-1 = <&sdc1_state_off>;
1363 power-domains = <&rpmpd SDM660_VDDCX>;
1365 bus-width = <8>;
1366 non-removable;
1370 sdhc1_opp_table: opp-table {
1371 compatible = "operating-points-v2";
1373 opp-50000000 {
1374 opp-hz = /bits/ 64 <50000000>;
1375 required-opps = <&rpmpd_opp_low_svs>;
1376 opp-peak-kBps = <200000 140000>;
1377 opp-avg-kBps = <130718 133320>;
1379 opp-100000000 {
1380 opp-hz = /bits/ 64 <100000000>;
1381 required-opps = <&rpmpd_opp_svs>;
1382 opp-peak-kBps = <250000 160000>;
1383 opp-avg-kBps = <196078 150000>;
1385 opp-384000000 {
1386 opp-hz = /bits/ 64 <384000000>;
1387 required-opps = <&rpmpd_opp_nom>;
1388 opp-peak-kBps = <4096000 4096000>;
1389 opp-avg-kBps = <1338562 1338562>;
1395 compatible = "qcom,sdm660-dwc3", "qcom,dwc3";
1398 #address-cells = <1>;
1399 #size-cells = <1>;
1406 clock-names = "cfg_noc", "core",
1409 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
1411 assigned-clock-rates = <19200000>, <60000000>;
1414 interrupt-names = "hs_phy_irq";
1416 qcom,select-utmi-as-pipe-clk;
1427 /* This is the HS-only host */
1428 maximum-speed = "high-speed";
1430 phy-names = "usb2-phy";
1431 snps,hird-threshold = /bits/ 8 <0>;
1435 mmcc: clock-controller@c8c0000 {
1436 compatible = "qcom,mmcc-sdm630";
1438 #clock-cells = <1>;
1439 #reset-cells = <1>;
1440 #power-domain-cells = <1>;
1441 clock-names = "xo",
1463 dsi_opp_table: opp-table-dsi {
1464 compatible = "operating-points-v2";
1466 opp-131250000 {
1467 opp-hz = /bits/ 64 <131250000>;
1468 required-opps = <&rpmpd_opp_svs>;
1471 opp-210000000 {
1472 opp-hz = /bits/ 64 <210000000>;
1473 required-opps = <&rpmpd_opp_svs_plus>;
1476 opp-262500000 {
1477 opp-hz = /bits/ 64 <262500000>;
1478 required-opps = <&rpmpd_opp_nom>;
1486 reg-names = "mdss_phys", "vbif_phys";
1488 power-domains = <&mmcc MDSS_GDSC>;
1494 clock-names = "iface",
1501 interrupt-controller;
1502 #interrupt-cells = <1>;
1504 #address-cells = <1>;
1505 #size-cells = <1>;
1512 reg-names = "mdp_phys";
1514 interrupt-parent = <&mdss>;
1517 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
1519 assigned-clock-rates = <300000000>,
1525 clock-names = "iface",
1533 interconnect-names = "mdp0-mem",
1534 "mdp1-mem",
1535 "rotator-mem";
1537 operating-points-v2 = <&mdp_opp_table>;
1538 power-domains = <&rpmpd SDM660_VDDCX>;
1541 #address-cells = <1>;
1542 #size-cells = <0>;
1547 remote-endpoint = <&dsi0_in>;
1552 mdp_opp_table: opp-table {
1553 compatible = "operating-points-v2";
1555 opp-150000000 {
1556 opp-hz = /bits/ 64 <150000000>;
1557 opp-peak-kBps = <320000 320000 76800>;
1558 required-opps = <&rpmpd_opp_low_svs>;
1560 opp-275000000 {
1561 opp-hz = /bits/ 64 <275000000>;
1562 opp-peak-kBps = <6400000 6400000 160000>;
1563 required-opps = <&rpmpd_opp_svs>;
1565 opp-300000000 {
1566 opp-hz = /bits/ 64 <300000000>;
1567 opp-peak-kBps = <6400000 6400000 190000>;
1568 required-opps = <&rpmpd_opp_svs_plus>;
1570 opp-330000000 {
1571 opp-hz = /bits/ 64 <330000000>;
1572 opp-peak-kBps = <6400000 6400000 240000>;
1573 required-opps = <&rpmpd_opp_nom>;
1575 opp-412500000 {
1576 opp-hz = /bits/ 64 <412500000>;
1577 opp-peak-kBps = <6400000 6400000 320000>;
1578 required-opps = <&rpmpd_opp_turbo>;
1584 compatible = "qcom,mdss-dsi-ctrl";
1586 reg-names = "dsi_ctrl";
1588 operating-points-v2 = <&dsi_opp_table>;
1589 power-domains = <&rpmpd SDM660_VDDCX>;
1591 interrupt-parent = <&mdss>;
1594 assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
1596 assigned-clock-parents = <&dsi0_phy 0>,
1608 clock-names = "mdp_core",
1619 phy-names = "dsi";
1624 #address-cells = <1>;
1625 #size-cells = <0>;
1630 remote-endpoint = <&mdp5_intf1_out>;
1642 dsi0_phy: dsi-phy@c994400 {
1643 compatible = "qcom,dsi-phy-14nm-660";
1647 reg-names = "dsi_phy",
1651 #clock-cells = <1>;
1652 #phy-cells = <0>;
1655 clock-names = "iface", "ref";
1660 blsp1_dma: dma-controller@c144000 {
1661 compatible = "qcom,bam-v1.7.0";
1665 clock-names = "bam_clk";
1666 #dma-cells = <1>;
1668 qcom,controlled-remotely;
1669 num-channels = <18>;
1670 qcom,num-ees = <4>;
1674 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1679 clock-names = "core", "iface";
1681 dma-names = "tx", "rx";
1682 pinctrl-names = "default", "sleep";
1683 pinctrl-0 = <&blsp1_uart1_default>;
1684 pinctrl-1 = <&blsp1_uart1_sleep>;
1689 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1694 clock-names = "core", "iface";
1696 dma-names = "tx", "rx";
1697 pinctrl-names = "default";
1698 pinctrl-0 = <&blsp1_uart2_default>;
1703 compatible = "qcom,i2c-qup-v2.2.1";
1709 clock-names = "core", "iface";
1710 clock-frequency = <400000>;
1712 dma-names = "tx", "rx";
1714 pinctrl-names = "default", "sleep";
1715 pinctrl-0 = <&i2c1_default>;
1716 pinctrl-1 = <&i2c1_sleep>;
1717 #address-cells = <1>;
1718 #size-cells = <0>;
1723 compatible = "qcom,i2c-qup-v2.2.1";
1729 clock-names = "core", "iface";
1730 clock-frequency = <400000>;
1732 dma-names = "tx", "rx";
1734 pinctrl-names = "default", "sleep";
1735 pinctrl-0 = <&i2c2_default>;
1736 pinctrl-1 = <&i2c2_sleep>;
1737 #address-cells = <1>;
1738 #size-cells = <0>;
1743 compatible = "qcom,i2c-qup-v2.2.1";
1749 clock-names = "core", "iface";
1750 clock-frequency = <400000>;
1752 dma-names = "tx", "rx";
1754 pinctrl-names = "default", "sleep";
1755 pinctrl-0 = <&i2c3_default>;
1756 pinctrl-1 = <&i2c3_sleep>;
1757 #address-cells = <1>;
1758 #size-cells = <0>;
1763 compatible = "qcom,i2c-qup-v2.2.1";
1769 clock-names = "core", "iface";
1770 clock-frequency = <400000>;
1772 dma-names = "tx", "rx";
1774 pinctrl-names = "default", "sleep";
1775 pinctrl-0 = <&i2c4_default>;
1776 pinctrl-1 = <&i2c4_sleep>;
1777 #address-cells = <1>;
1778 #size-cells = <0>;
1782 blsp2_dma: dma-controller@c184000 {
1783 compatible = "qcom,bam-v1.7.0";
1787 clock-names = "bam_clk";
1788 #dma-cells = <1>;
1790 qcom,controlled-remotely;
1791 num-channels = <18>;
1792 qcom,num-ees = <4>;
1796 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1801 clock-names = "core", "iface";
1803 dma-names = "tx", "rx";
1804 pinctrl-names = "default", "sleep";
1805 pinctrl-0 = <&blsp2_uart1_default>;
1806 pinctrl-1 = <&blsp2_uart1_sleep>;
1811 compatible = "qcom,i2c-qup-v2.2.1";
1817 clock-names = "core", "iface";
1818 clock-frequency = <400000>;
1820 dma-names = "tx", "rx";
1822 pinctrl-names = "default", "sleep";
1823 pinctrl-0 = <&i2c5_default>;
1824 pinctrl-1 = <&i2c5_sleep>;
1825 #address-cells = <1>;
1826 #size-cells = <0>;
1831 compatible = "qcom,i2c-qup-v2.2.1";
1837 clock-names = "core", "iface";
1838 clock-frequency = <400000>;
1840 dma-names = "tx", "rx";
1842 pinctrl-names = "default", "sleep";
1843 pinctrl-0 = <&i2c6_default>;
1844 pinctrl-1 = <&i2c6_sleep>;
1845 #address-cells = <1>;
1846 #size-cells = <0>;
1851 compatible = "qcom,i2c-qup-v2.2.1";
1857 clock-names = "core", "iface";
1858 clock-frequency = <400000>;
1860 dma-names = "tx", "rx";
1862 pinctrl-names = "default", "sleep";
1863 pinctrl-0 = <&i2c7_default>;
1864 pinctrl-1 = <&i2c7_sleep>;
1865 #address-cells = <1>;
1866 #size-cells = <0>;
1871 compatible = "qcom,i2c-qup-v2.2.1";
1877 clock-names = "core", "iface";
1878 clock-frequency = <400000>;
1880 dma-names = "tx", "rx";
1882 pinctrl-names = "default", "sleep";
1883 pinctrl-0 = <&i2c8_default>;
1884 pinctrl-1 = <&i2c8_sleep>;
1885 #address-cells = <1>;
1886 #size-cells = <0>;
1891 compatible = "qcom,sdm630-imem", "syscon", "simple-mfd";
1894 #address-cells = <1>;
1895 #size-cells = <1>;
1899 pil-reloc@94c {
1900 compatible = "qcom,pil-reloc-info";
1906 compatible = "qcom,sdm660-camss";
1921 reg-names = "csi_clk_mux",
1945 interrupt-names = "csid0",
1997 clock-names = "ahb",
2040 interconnect-names = "vfe-mem";
2045 power-domains = <&mmcc CAMSS_VFE0_GDSC>,
2050 #address-cells = <1>;
2051 #size-cells = <0>;
2056 compatible = "qcom,msm8996-cci";
2057 #address-cells = <1>;
2058 #size-cells = <0>;
2062 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
2064 assigned-clock-rates = <80800000>, <37500000>;
2069 clock-names = "camss_top_ahb",
2074 pinctrl-names = "default";
2075 pinctrl-0 = <&cci0_default &cci1_default>;
2076 power-domains = <&mmcc CAMSS_TOP_GDSC>;
2079 cci_i2c0: i2c-bus@0 {
2081 clock-frequency = <400000>;
2082 #address-cells = <1>;
2083 #size-cells = <0>;
2086 cci_i2c1: i2c-bus@1 {
2088 clock-frequency = <400000>;
2089 #address-cells = <1>;
2090 #size-cells = <0>;
2094 venus: video-codec@cc00000 {
2095 compatible = "qcom,sdm660-venus";
2101 clock-names = "core", "iface", "bus", "bus_throttle";
2104 interconnect-names = "cpu-cfg", "video-mem";
2126 memory-region = <&venus_region>;
2127 power-domains = <&mmcc VENUS_GDSC>;
2130 video-decoder {
2131 compatible = "venus-decoder";
2133 clock-names = "vcodec0_core";
2134 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2137 video-encoder {
2138 compatible = "venus-encoder";
2140 clock-names = "vcodec0_core";
2141 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2146 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
2153 clock-names = "iface-mm", "iface-smmu",
2154 "bus-mm", "bus-smmu";
2155 #global-interrupts = <2>;
2156 #iommu-cells = <1>;
2191 compatible = "qcom,sdm660-adsp-pas";
2194 interrupts-extended =
2200 interrupt-names = "wdog", "fatal", "ready",
2201 "handover", "stop-ack";
2204 clock-names = "xo";
2206 memory-region = <&adsp_region>;
2207 power-domains = <&rpmpd SDM660_VDDCX>;
2208 power-domain-names = "cx";
2210 qcom,smem-states = <&adsp_smp2p_out 0>;
2211 qcom,smem-state-names = "stop";
2213 glink-edge {
2218 qcom,remote-pid = <2>;
2221 compatible = "qcom,apr-v2";
2222 qcom,glink-channels = "apr_audio_svc";
2224 #address-cells = <1>;
2225 #size-cells = <0>;
2232 q6afe: apr-service@4 {
2236 compatible = "qcom,q6afe-dais";
2237 #address-cells = <1>;
2238 #size-cells = <0>;
2239 #sound-dai-cells = <1>;
2243 q6asm: apr-service@7 {
2247 compatible = "qcom,q6asm-dais";
2248 #address-cells = <1>;
2249 #size-cells = <0>;
2250 #sound-dai-cells = <1>;
2255 q6adm: apr-service@8 {
2259 compatible = "qcom,q6adm-routing";
2260 #sound-dai-cells = <0>;
2268 compatible = "qcom,sdm660-gnoc";
2270 #interconnect-cells = <1>;
2275 clock-names = "bus", "bus_a";
2280 compatible = "qcom,sdm660-apcs-hmss-global";
2283 #mbox-cells = <1>;
2287 #address-cells = <1>;
2288 #size-cells = <1>;
2290 compatible = "arm,armv7-timer-mem";
2292 clock-frequency = <19200000>;
2295 frame-number = <0>;
2303 frame-number = <1>;
2310 frame-number = <2>;
2317 frame-number = <3>;
2324 frame-number = <4>;
2331 frame-number = <5>;
2338 frame-number = <6>;
2345 intc: interrupt-controller@17a00000 {
2346 compatible = "arm,gic-v3";
2349 #interrupt-cells = <3>;
2350 #address-cells = <1>;
2351 #size-cells = <1>;
2353 interrupt-controller;
2354 #redistributor-regions = <1>;
2355 redistributor-stride = <0x0 0x20000>;
2363 thermal-zones {
2364 aoss-thermal {
2365 polling-delay-passive = <250>;
2366 polling-delay = <1000>;
2368 thermal-sensors = <&tsens 0>;
2371 aoss_alert0: trip-point0 {
2379 cpuss0-thermal {
2380 polling-delay-passive = <250>;
2381 polling-delay = <1000>;
2383 thermal-sensors = <&tsens 1>;
2386 cpuss0_alert0: trip-point0 {
2394 cpuss1-thermal {
2395 polling-delay-passive = <250>;
2396 polling-delay = <1000>;
2398 thermal-sensors = <&tsens 2>;
2401 cpuss1_alert0: trip-point0 {
2409 cpu0-thermal {
2410 polling-delay-passive = <250>;
2411 polling-delay = <1000>;
2413 thermal-sensors = <&tsens 3>;
2416 cpu0_alert0: trip-point0 {
2430 cpu1-thermal {
2431 polling-delay-passive = <250>;
2432 polling-delay = <1000>;
2434 thermal-sensors = <&tsens 4>;
2437 cpu1_alert0: trip-point0 {
2451 cpu2-thermal {
2452 polling-delay-passive = <250>;
2453 polling-delay = <1000>;
2455 thermal-sensors = <&tsens 5>;
2458 cpu2_alert0: trip-point0 {
2472 cpu3-thermal {
2473 polling-delay-passive = <250>;
2474 polling-delay = <1000>;
2476 thermal-sensors = <&tsens 6>;
2479 cpu3_alert0: trip-point0 {
2499 pwr-cluster-thermal {
2500 polling-delay-passive = <250>;
2501 polling-delay = <1000>;
2503 thermal-sensors = <&tsens 7>;
2506 pwr_cluster_alert0: trip-point0 {
2520 gpu-thermal {
2521 polling-delay-passive = <250>;
2522 polling-delay = <1000>;
2524 thermal-sensors = <&tsens 8>;
2527 gpu_alert0: trip-point0 {
2537 compatible = "arm,armv8-timer";