Lines Matching +full:0 +full:x146bf000
33 #clock-cells = <0>;
40 #clock-cells = <0>;
48 #size-cells = <0>;
53 reg = <0x0 0x100>;
72 reg = <0x0 0x101>;
87 reg = <0x0 0x102>;
102 reg = <0x0 0x103>;
114 CPU4: cpu@0 {
117 reg = <0x0 0x0>;
136 reg = <0x0 0x1>;
151 reg = <0x0 0x2>;
166 reg = <0x0 0x3>;
219 PWR_CPU_SLEEP_0: cpu-sleep-0-0 {
222 arm,psci-suspend-param = <0x40000002>;
228 PWR_CPU_SLEEP_1: cpu-sleep-0-1 {
231 arm,psci-suspend-param = <0x40000003>;
238 PERF_CPU_SLEEP_0: cpu-sleep-1-0 {
241 arm,psci-suspend-param = <0x40000002>;
250 arm,psci-suspend-param = <0x40000003>;
257 PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 {
260 arm,psci-suspend-param = <0x400000F2>;
267 PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 {
270 arm,psci-suspend-param = <0x400000F3>;
277 PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 {
280 arm,psci-suspend-param = <0x400000F4>;
287 PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 {
290 arm,psci-suspend-param = <0x400000F2>;
300 arm,psci-suspend-param = <0x400000F3>;
310 arm,psci-suspend-param = <0x400000F4>;
328 reg = <0x0 0x80000000 0x0 0x0>;
347 reg = <0x0 0x85600000 0x0 0x100000>;
352 reg = <0x0 0x85700000 0x0 0x100000>;
357 reg = <0x0 0x85800000 0x0 0x600000>;
363 reg = <0x0 0x85e00000 0x0 0x200000>;
371 reg = <0 0x86000000 0 0x200000>;
376 reg = <0x0 0x86200000 0x0 0x3300000>;
381 reg = <0x0 0x8ac00000 0x0 0x7e00000>;
386 reg = <0x0 0x92a00000 0x0 0x1e00000>;
391 reg = <0x0 0x94800000 0x0 0x200000>;
396 reg = <0x0 0x94a00000 0x0 0x100000>;
401 reg = <0x0 0x9f800000 0x0 0x800000>;
406 reg = <0x0 0xf6000000 0x0 0x800000>;
411 reg = <0x0 0xf6800000 0x0 0x1400000>;
417 reg = <0x0 0xfed00000 0x0 0xa00000>;
427 mboxes = <&apcs_glb 0>;
497 qcom,local-pid = <0>;
517 qcom,local-pid = <0>;
535 ranges = <0 0 0 0xffffffff>;
543 reg = <0x00100000 0x94000>;
552 reg = <0x00778000 0x7000>;
557 reg = <0x00780000 0x621c>;
562 reg = <0x243 0x1>;
567 reg = <0x41a2 0x1>;
574 reg = <0x00793000 0x1000>;
581 reg = <0x01008000 0x78000>;
590 reg = <0x010ac000 0x4>;
595 reg = <0x01500000 0x10000>;
604 reg = <0x01626000 0x7090>;
613 reg = <0x016c0000 0x40000>;
661 reg = <0x01704000 0xc100>;
681 reg = <0x01745000 0xA010>;
691 reg = <0x010ae000 0x1000>, /* TM */
692 <0x010ad000 0x1000>; /* SROT */
702 reg = <0x01f40000 0x20000>;
708 reg = <0x01f60000 0x20000>;
713 reg = <0x03100000 0x400000>,
714 <0x03500000 0x400000>,
715 <0x03900000 0x400000>;
719 gpio-ranges = <&tlmm 0 0 114>;
1018 reg = <0x05000000 0x40000>;
1021 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
1038 iommus = <&kgsl_smmu 0>;
1056 opp-supported-hw = <0xA2>;
1062 opp-supported-hw = <0xFF>;
1068 opp-supported-hw = <0xFF>;
1074 opp-supported-hw = <0xFF>;
1080 opp-supported-hw = <0xFF>;
1086 opp-supported-hw = <0xFF>;
1092 opp-supported-hw = <0xFF>;
1100 reg = <0x05040000 0x10000>;
1138 reg = <0x05065000 0x9038>;
1151 reg = <0x05100000 0x40000>;
1182 reg = <0x00290000 0x10000>;
1187 reg = <0x0800f000 0x1000>,
1188 <0x08400000 0x1000000>,
1189 <0x09400000 0x1000000>,
1190 <0x0a400000 0x220000>,
1191 <0x0800a000 0x3000>;
1195 qcom,ee = <0>;
1196 qcom,channel = <0>;
1198 #size-cells = <0>;
1201 cell-index = <0>;
1206 reg = <0x0a8f8800 0x400>;
1242 reg = <0x0a800000 0xc8d0>;
1254 snps,hird-threshold = /bits/ 8 <0>;
1260 reg = <0x0c012000 0x180>;
1261 #phy-cells = <0>;
1274 reg = <0x0c014000 0x180>;
1275 #phy-cells = <0>;
1288 reg = <0x0c084000 0x1000>;
1304 <&gnoc 0 &cnoc 28>;
1309 pinctrl-0 = <&sdc2_state_on>;
1341 reg = <0x0c0c4000 0x1000>,
1342 <0x0c0c5000 0x1000>,
1343 <0x0c0c8000 0x8000>;
1357 <&gnoc 0 &cnoc 27>;
1361 pinctrl-0 = <&sdc1_state_on>;
1396 reg = <0x0c2f8800 0x400>;
1422 reg = <0x0c200000 0xc8d0>;
1431 snps,hird-threshold = /bits/ 8 <0>;
1437 reg = <0x0c8c0000 0x40000>;
1456 <&dsi0_phy 0>,
1457 <0>,
1458 <0>,
1459 <0>,
1460 <0>;
1484 reg = <0x0c900000 0x1000>,
1485 <0x0c9b0000 0x1040>;
1511 reg = <0x0c901000 0x89000>;
1515 interrupts = <0>;
1532 <&gnoc 0 &mnoc 17>;
1536 iommus = <&mmss_smmu 0>;
1542 #size-cells = <0>;
1544 port@0 {
1545 reg = <0>;
1585 reg = <0x0c994000 0x400>;
1596 assigned-clock-parents = <&dsi0_phy 0>,
1625 #size-cells = <0>;
1627 port@0 {
1628 reg = <0>;
1644 reg = <0x0c994400 0x100>,
1645 <0x0c994500 0x300>,
1646 <0x0c994800 0x188>;
1652 #phy-cells = <0>;
1662 reg = <0x0c144000 0x1f000>;
1667 qcom,ee = <0>;
1675 reg = <0x0c16f000 0x200>;
1680 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>;
1683 pinctrl-0 = <&blsp1_uart1_default>;
1690 reg = <0x0c170000 0x1000>;
1698 pinctrl-0 = <&blsp1_uart2_default>;
1704 reg = <0x0c175000 0x600>;
1715 pinctrl-0 = <&i2c1_default>;
1718 #size-cells = <0>;
1724 reg = <0x0c176000 0x600>;
1735 pinctrl-0 = <&i2c2_default>;
1738 #size-cells = <0>;
1744 reg = <0x0c177000 0x600>;
1755 pinctrl-0 = <&i2c3_default>;
1758 #size-cells = <0>;
1764 reg = <0x0c178000 0x600>;
1775 pinctrl-0 = <&i2c4_default>;
1778 #size-cells = <0>;
1784 reg = <0x0c184000 0x1f000>;
1789 qcom,ee = <0>;
1797 reg = <0x0c1af000 0x200>;
1802 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
1805 pinctrl-0 = <&blsp2_uart1_default>;
1812 reg = <0x0c1b5000 0x600>;
1823 pinctrl-0 = <&i2c5_default>;
1826 #size-cells = <0>;
1832 reg = <0x0c1b6000 0x600>;
1843 pinctrl-0 = <&i2c6_default>;
1846 #size-cells = <0>;
1852 reg = <0x0c1b7000 0x600>;
1863 pinctrl-0 = <&i2c7_default>;
1866 #size-cells = <0>;
1872 reg = <0x0c1b8000 0x600>;
1883 pinctrl-0 = <&i2c8_default>;
1886 #size-cells = <0>;
1892 reg = <0x146bf000 0x1000>;
1897 ranges = <0 0x146bf000 0x1000>;
1901 reg = <0x94c 0xc8>;
1907 reg = <0x0ca00020 0x10>,
1908 <0x0ca30000 0x100>,
1909 <0x0ca30400 0x100>,
1910 <0x0ca30800 0x100>,
1911 <0x0ca30c00 0x100>,
1912 <0x0c824000 0x1000>,
1913 <0x0ca00120 0x4>,
1914 <0x0c825000 0x1000>,
1915 <0x0ca00124 0x4>,
1916 <0x0c826000 0x1000>,
1917 <0x0ca00128 0x4>,
1918 <0x0ca31000 0x500>,
1919 <0x0ca10000 0x1000>,
1920 <0x0ca14000 0x1000>;
2041 iommus = <&mmss_smmu 0xc00>,
2042 <&mmss_smmu 0xc01>,
2043 <&mmss_smmu 0xc02>,
2044 <&mmss_smmu 0xc03>;
2051 #size-cells = <0>;
2058 #size-cells = <0>;
2059 reg = <0x0ca0c000 0x1000>;
2075 pinctrl-0 = <&cci0_default &cci1_default>;
2079 cci_i2c0: i2c-bus@0 {
2080 reg = <0>;
2083 #size-cells = <0>;
2090 #size-cells = <0>;
2096 reg = <0x0cc00000 0xff000>;
2102 interconnects = <&gnoc 0 &mnoc 13>,
2106 iommus = <&mmss_smmu 0x400>,
2107 <&mmss_smmu 0x401>,
2108 <&mmss_smmu 0x40a>,
2109 <&mmss_smmu 0x407>,
2110 <&mmss_smmu 0x40e>,
2111 <&mmss_smmu 0x40f>,
2112 <&mmss_smmu 0x408>,
2113 <&mmss_smmu 0x409>,
2114 <&mmss_smmu 0x40b>,
2115 <&mmss_smmu 0x40c>,
2116 <&mmss_smmu 0x40d>,
2117 <&mmss_smmu 0x410>,
2118 <&mmss_smmu 0x421>,
2119 <&mmss_smmu 0x428>,
2120 <&mmss_smmu 0x429>,
2121 <&mmss_smmu 0x42b>,
2122 <&mmss_smmu 0x42c>,
2123 <&mmss_smmu 0x42d>,
2124 <&mmss_smmu 0x411>,
2125 <&mmss_smmu 0x431>;
2147 reg = <0x0cd00000 0x40000>;
2192 reg = <0x15700000 0x4040>;
2196 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2210 qcom,smem-states = <&adsp_smp2p_out 0>;
2225 #size-cells = <0>;
2238 #size-cells = <0>;
2249 #size-cells = <0>;
2260 #sound-dai-cells = <0>;
2269 reg = <0x17900000 0xe000>;
2281 reg = <0x17911000 0x1000>;
2291 reg = <0x17920000 0x1000>;
2295 frame-number = <0>;
2296 interrupts = <0 8 0x4>,
2297 <0 7 0x4>;
2298 reg = <0x17921000 0x1000>,
2299 <0x17922000 0x1000>;
2304 interrupts = <0 9 0x4>;
2305 reg = <0x17923000 0x1000>;
2311 interrupts = <0 10 0x4>;
2312 reg = <0x17924000 0x1000>;
2318 interrupts = <0 11 0x4>;
2319 reg = <0x17925000 0x1000>;
2325 interrupts = <0 12 0x4>;
2326 reg = <0x17926000 0x1000>;
2332 interrupts = <0 13 0x4>;
2333 reg = <0x17927000 0x1000>;
2339 interrupts = <0 14 0x4>;
2340 reg = <0x17928000 0x1000>;
2347 reg = <0x17a00000 0x10000>, /* GICD */
2348 <0x17b00000 0x100000>; /* GICR * 8 */
2355 redistributor-stride = <0x0 0x20000>;
2368 thermal-sensors = <&tsens 0>;
2538 interrupts = <GIC_PPI 1 0xf08>,
2539 <GIC_PPI 2 0xf08>,
2540 <GIC_PPI 3 0xf08>,
2541 <GIC_PPI 0 0xf08>;