Lines Matching refs:gcc
7 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
700 gcc: clock-controller@100000 { label
701 compatible = "qcom,gcc-sc8280xp";
754 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
755 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
768 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
783 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
799 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
800 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
814 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
830 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
831 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
851 resets = <&gcc GCC_UFS_PHY_BCR>;
854 power-domains = <&gcc UFS_PHY_GDSC>;
859 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
860 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
861 <&gcc GCC_UFS_PHY_AHB_CLK>,
862 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
864 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
865 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
866 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
894 clocks = <&gcc GCC_UFS_REF_CLKREF_CLK>,
895 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
920 resets = <&gcc GCC_UFS_CARD_BCR>;
923 power-domains = <&gcc UFS_CARD_GDSC>;
927 clocks = <&gcc GCC_UFS_CARD_AXI_CLK>,
928 <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>,
929 <&gcc GCC_UFS_CARD_AHB_CLK>,
930 <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>,
932 <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>,
933 <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>,
934 <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>;
962 clocks = <&gcc GCC_UFS_REF_CLKREF_CLK>,
963 <&gcc GCC_UFS_CARD_PHY_AUX_CLK>;
992 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1003 clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>;
1005 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;
1016 clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>;
1018 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>;
1029 clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>;
1031 resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>;
1042 clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>;
1044 resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>;
1058 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
1060 <&gcc GCC_USB3_MP0_CLKREF_CLK>,
1061 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>;
1064 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,
1065 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
1068 power-domains = <&gcc USB30_MP_GDSC>;
1078 clocks = <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
1091 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
1093 <&gcc GCC_USB3_MP1_CLKREF_CLK>,
1094 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>;
1097 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
1098 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
1101 power-domains = <&gcc USB30_MP_GDSC>;
1111 clocks = <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;
1167 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
1169 <&gcc GCC_USB4_EUD_CLKREF_CLK>,
1170 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
1173 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
1174 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
1177 power-domains = <&gcc USB30_PRIM_GDSC>;
1190 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
1205 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
1219 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
1221 <&gcc GCC_USB4_CLKREF_CLK>,
1222 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
1225 resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
1226 <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>;
1229 power-domains = <&gcc USB30_SEC_GDSC>;
1242 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
1262 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1263 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1264 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
1265 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
1266 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1267 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
1268 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
1269 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
1270 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
1274 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1275 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1287 power-domains = <&gcc USB30_PRIM_GDSC>;
1289 resets = <&gcc GCC_USB30_PRIM_BCR>;
1316 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
1317 <&gcc GCC_USB30_SEC_MASTER_CLK>,
1318 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
1319 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
1320 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1321 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
1322 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
1323 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
1324 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
1328 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1329 <&gcc GCC_USB30_SEC_MASTER_CLK>;
1341 power-domains = <&gcc USB30_SEC_GDSC>;
1343 resets = <&gcc GCC_USB30_SEC_BCR>;
1795 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;