Lines Matching +full:fastrpc +full:- +full:compute +full:- +full:cb
1 // SPDX-License-Identifier: BSD-3-Clause
7 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
8 #include <dt-bindings/clock/qcom,rpmh.h>
9 #include <dt-bindings/interconnect/qcom,sc8280xp.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/mailbox/qcom-ipcc.h>
12 #include <dt-bindings/power/qcom-rpmpd.h>
13 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
14 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&intc>;
19 #address-cells = <2>;
20 #size-cells = <2>;
23 xo_board_clk: xo-board-clk {
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
28 sleep_clk: sleep-clk {
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <32764>;
35 cpu0_opp_table: cpu0-opp-table {
36 compatible = "operating-points-v2";
37 opp-shared;
39 opp-300000000 {
40 opp-hz = /bits/ 64 <300000000>;
42 opp-403200000 {
43 opp-hz = /bits/ 64 <403200000>;
45 opp-499200000 {
46 opp-hz = /bits/ 64 <499200000>;
48 opp-595200000 {
49 opp-hz = /bits/ 64 <595200000>;
51 opp-691200000 {
52 opp-hz = /bits/ 64 <691200000>;
54 opp-806400000 {
55 opp-hz = /bits/ 64 <806400000>;
57 opp-902400000 {
58 opp-hz = /bits/ 64 <902400000>;
60 opp-1017600000 {
61 opp-hz = /bits/ 64 <1017600000>;
63 opp-1113600000 {
64 opp-hz = /bits/ 64 <1113600000>;
66 opp-1209600000 {
67 opp-hz = /bits/ 64 <1209600000>;
69 opp-1324800000 {
70 opp-hz = /bits/ 64 <1324800000>;
72 opp-1440000000 {
73 opp-hz = /bits/ 64 <1440000000>;
75 opp-1555200000 {
76 opp-hz = /bits/ 64 <1555200000>;
78 opp-1670400000 {
79 opp-hz = /bits/ 64 <1670400000>;
81 opp-1785600000 {
82 opp-hz = /bits/ 64 <1785600000>;
84 opp-1881600000 {
85 opp-hz = /bits/ 64 <1881600000>;
87 opp-1996800000 {
88 opp-hz = /bits/ 64 <1996800000>;
90 opp-2112000000 {
91 opp-hz = /bits/ 64 <2112000000>;
93 opp-2227200000 {
94 opp-hz = /bits/ 64 <2227200000>;
96 opp-2342400000 {
97 opp-hz = /bits/ 64 <2342400000>;
99 opp-2438400000 {
100 opp-hz = /bits/ 64 <2438400000>;
104 cpu4_opp_table: cpu4-opp-table {
105 compatible = "operating-points-v2";
106 opp-shared;
108 opp-825600000 {
109 opp-hz = /bits/ 64 <825600000>;
111 opp-940800000 {
112 opp-hz = /bits/ 64 <940800000>;
114 opp-1056000000 {
115 opp-hz = /bits/ 64 <1056000000>;
117 opp-1171200000 {
118 opp-hz = /bits/ 64 <1171200000>;
120 opp-1286400000 {
121 opp-hz = /bits/ 64 <1286400000>;
123 opp-1401600000 {
124 opp-hz = /bits/ 64 <1401600000>;
126 opp-1516800000 {
127 opp-hz = /bits/ 64 <1516800000>;
129 opp-1632000000 {
130 opp-hz = /bits/ 64 <1632000000>;
132 opp-1747200000 {
133 opp-hz = /bits/ 64 <1747200000>;
135 opp-1862400000 {
136 opp-hz = /bits/ 64 <1862400000>;
138 opp-1977600000 {
139 opp-hz = /bits/ 64 <1977600000>;
141 opp-2073600000 {
142 opp-hz = /bits/ 64 <2073600000>;
144 opp-2169600000 {
145 opp-hz = /bits/ 64 <2169600000>;
147 opp-2284800000 {
148 opp-hz = /bits/ 64 <2284800000>;
150 opp-2400000000 {
151 opp-hz = /bits/ 64 <2400000000>;
153 opp-2496000000 {
154 opp-hz = /bits/ 64 <2496000000>;
156 opp-2592000000 {
157 opp-hz = /bits/ 64 <2592000000>;
159 opp-2688000000 {
160 opp-hz = /bits/ 64 <2688000000>;
162 opp-2803200000 {
163 opp-hz = /bits/ 64 <2803200000>;
165 opp-2899200000 {
166 opp-hz = /bits/ 64 <2899200000>;
168 opp-2995200000 {
169 opp-hz = /bits/ 64 <2995200000>;
174 #address-cells = <2>;
175 #size-cells = <0>;
181 enable-method = "psci";
182 capacity-dmips-mhz = <602>;
183 next-level-cache = <&L2_0>;
184 power-domains = <&CPU_PD0>;
185 power-domain-names = "psci";
186 qcom,freq-domain = <&cpufreq_hw 0>;
187 operating-points-v2 = <&cpu0_opp_table>;
188 #cooling-cells = <2>;
189 L2_0: l2-cache {
191 next-level-cache = <&L3_0>;
192 L3_0: l3-cache {
202 enable-method = "psci";
203 capacity-dmips-mhz = <602>;
204 next-level-cache = <&L2_100>;
205 power-domains = <&CPU_PD1>;
206 power-domain-names = "psci";
207 qcom,freq-domain = <&cpufreq_hw 0>;
208 operating-points-v2 = <&cpu0_opp_table>;
209 #cooling-cells = <2>;
210 L2_100: l2-cache {
212 next-level-cache = <&L3_0>;
220 enable-method = "psci";
221 capacity-dmips-mhz = <602>;
222 next-level-cache = <&L2_200>;
223 power-domains = <&CPU_PD2>;
224 power-domain-names = "psci";
225 qcom,freq-domain = <&cpufreq_hw 0>;
226 operating-points-v2 = <&cpu0_opp_table>;
227 #cooling-cells = <2>;
228 L2_200: l2-cache {
230 next-level-cache = <&L3_0>;
238 enable-method = "psci";
239 capacity-dmips-mhz = <602>;
240 next-level-cache = <&L2_300>;
241 power-domains = <&CPU_PD3>;
242 power-domain-names = "psci";
243 qcom,freq-domain = <&cpufreq_hw 0>;
244 operating-points-v2 = <&cpu0_opp_table>;
245 #cooling-cells = <2>;
246 L2_300: l2-cache {
248 next-level-cache = <&L3_0>;
256 enable-method = "psci";
257 capacity-dmips-mhz = <1024>;
258 next-level-cache = <&L2_400>;
259 power-domains = <&CPU_PD4>;
260 power-domain-names = "psci";
261 qcom,freq-domain = <&cpufreq_hw 1>;
262 operating-points-v2 = <&cpu4_opp_table>;
263 #cooling-cells = <2>;
264 L2_400: l2-cache {
266 next-level-cache = <&L3_0>;
274 enable-method = "psci";
275 capacity-dmips-mhz = <1024>;
276 next-level-cache = <&L2_500>;
277 power-domains = <&CPU_PD5>;
278 power-domain-names = "psci";
279 qcom,freq-domain = <&cpufreq_hw 1>;
280 operating-points-v2 = <&cpu4_opp_table>;
281 #cooling-cells = <2>;
282 L2_500: l2-cache {
284 next-level-cache = <&L3_0>;
292 enable-method = "psci";
293 capacity-dmips-mhz = <1024>;
294 next-level-cache = <&L2_600>;
295 power-domains = <&CPU_PD6>;
296 power-domain-names = "psci";
297 qcom,freq-domain = <&cpufreq_hw 1>;
298 operating-points-v2 = <&cpu4_opp_table>;
299 #cooling-cells = <2>;
300 L2_600: l2-cache {
302 next-level-cache = <&L3_0>;
310 enable-method = "psci";
311 capacity-dmips-mhz = <1024>;
312 next-level-cache = <&L2_700>;
313 power-domains = <&CPU_PD7>;
314 power-domain-names = "psci";
315 qcom,freq-domain = <&cpufreq_hw 1>;
316 operating-points-v2 = <&cpu4_opp_table>;
317 #cooling-cells = <2>;
318 L2_700: l2-cache {
320 next-level-cache = <&L3_0>;
324 cpu-map {
360 idle-states {
361 entry-method = "psci";
363 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
364 compatible = "arm,idle-state";
365 idle-state-name = "little-rail-power-collapse";
366 arm,psci-suspend-param = <0x40000004>;
367 entry-latency-us = <355>;
368 exit-latency-us = <909>;
369 min-residency-us = <3934>;
370 local-timer-stop;
373 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
374 compatible = "arm,idle-state";
375 idle-state-name = "big-rail-power-collapse";
376 arm,psci-suspend-param = <0x40000004>;
377 entry-latency-us = <241>;
378 exit-latency-us = <1461>;
379 min-residency-us = <4488>;
380 local-timer-stop;
384 domain-idle-states {
385 CLUSTER_SLEEP_0: cluster-sleep-0 {
386 compatible = "domain-idle-state";
387 idle-state-name = "cluster-power-collapse";
388 arm,psci-suspend-param = <0x4100c344>;
389 entry-latency-us = <3263>;
390 exit-latency-us = <6562>;
391 min-residency-us = <9987>;
398 compatible = "qcom,scm-sc8280xp", "qcom,scm";
402 aggre1_noc: interconnect-aggre1-noc {
403 compatible = "qcom,sc8280xp-aggre1-noc";
404 #interconnect-cells = <2>;
405 qcom,bcm-voters = <&apps_bcm_voter>;
408 aggre2_noc: interconnect-aggre2-noc {
409 compatible = "qcom,sc8280xp-aggre2-noc";
410 #interconnect-cells = <2>;
411 qcom,bcm-voters = <&apps_bcm_voter>;
414 clk_virt: interconnect-clk-virt {
415 compatible = "qcom,sc8280xp-clk-virt";
416 #interconnect-cells = <2>;
417 qcom,bcm-voters = <&apps_bcm_voter>;
420 config_noc: interconnect-config-noc {
421 compatible = "qcom,sc8280xp-config-noc";
422 #interconnect-cells = <2>;
423 qcom,bcm-voters = <&apps_bcm_voter>;
426 dc_noc: interconnect-dc-noc {
427 compatible = "qcom,sc8280xp-dc-noc";
428 #interconnect-cells = <2>;
429 qcom,bcm-voters = <&apps_bcm_voter>;
432 gem_noc: interconnect-gem-noc {
433 compatible = "qcom,sc8280xp-gem-noc";
434 #interconnect-cells = <2>;
435 qcom,bcm-voters = <&apps_bcm_voter>;
438 lpass_noc: interconnect-lpass-ag-noc {
439 compatible = "qcom,sc8280xp-lpass-ag-noc";
440 #interconnect-cells = <2>;
441 qcom,bcm-voters = <&apps_bcm_voter>;
444 mc_virt: interconnect-mc-virt {
445 compatible = "qcom,sc8280xp-mc-virt";
446 #interconnect-cells = <2>;
447 qcom,bcm-voters = <&apps_bcm_voter>;
450 mmss_noc: interconnect-mmss-noc {
451 compatible = "qcom,sc8280xp-mmss-noc";
452 #interconnect-cells = <2>;
453 qcom,bcm-voters = <&apps_bcm_voter>;
456 nspa_noc: interconnect-nspa-noc {
457 compatible = "qcom,sc8280xp-nspa-noc";
458 #interconnect-cells = <2>;
459 qcom,bcm-voters = <&apps_bcm_voter>;
462 nspb_noc: interconnect-nspb-noc {
463 compatible = "qcom,sc8280xp-nspb-noc";
464 #interconnect-cells = <2>;
465 qcom,bcm-voters = <&apps_bcm_voter>;
468 system_noc: interconnect-system-noc {
469 compatible = "qcom,sc8280xp-system-noc";
470 #interconnect-cells = <2>;
471 qcom,bcm-voters = <&apps_bcm_voter>;
481 compatible = "arm,armv8-pmuv3";
486 compatible = "arm,psci-1.0";
490 #power-domain-cells = <0>;
491 power-domains = <&CLUSTER_PD>;
492 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
496 #power-domain-cells = <0>;
497 power-domains = <&CLUSTER_PD>;
498 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
502 #power-domain-cells = <0>;
503 power-domains = <&CLUSTER_PD>;
504 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
508 #power-domain-cells = <0>;
509 power-domains = <&CLUSTER_PD>;
510 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
514 #power-domain-cells = <0>;
515 power-domains = <&CLUSTER_PD>;
516 domain-idle-states = <&BIG_CPU_SLEEP_0>;
520 #power-domain-cells = <0>;
521 power-domains = <&CLUSTER_PD>;
522 domain-idle-states = <&BIG_CPU_SLEEP_0>;
526 #power-domain-cells = <0>;
527 power-domains = <&CLUSTER_PD>;
528 domain-idle-states = <&BIG_CPU_SLEEP_0>;
532 #power-domain-cells = <0>;
533 power-domains = <&CLUSTER_PD>;
534 domain-idle-states = <&BIG_CPU_SLEEP_0>;
537 CLUSTER_PD: cpu-cluster0 {
538 #power-domain-cells = <0>;
539 domain-idle-states = <&CLUSTER_SLEEP_0>;
543 qup_opp_table_100mhz: qup-100mhz-opp-table {
544 compatible = "operating-points-v2";
546 opp-75000000 {
547 opp-hz = /bits/ 64 <75000000>;
548 required-opps = <&rpmhpd_opp_low_svs>;
551 opp-100000000 {
552 opp-hz = /bits/ 64 <100000000>;
553 required-opps = <&rpmhpd_opp_svs>;
557 reserved-memory {
558 #address-cells = <2>;
559 #size-cells = <2>;
562 reserved-region@80000000 {
564 no-map;
567 cmd_db: cmd-db-region@80860000 {
568 compatible = "qcom,cmd-db";
570 no-map;
573 reserved-region@80880000 {
575 no-map;
578 smem_mem: smem-region@80900000 {
581 no-map;
585 reserved-region@80b00000 {
587 no-map;
590 reserved-region@83b00000 {
592 no-map;
595 reserved-region@85b00000 {
597 no-map;
600 pil_adsp_mem: adsp-region@86c00000 {
602 no-map;
605 pil_nsp0_mem: cdsp0-region@8a100000 {
607 no-map;
610 pil_nsp1_mem: cdsp1-region@8c600000 {
612 no-map;
615 reserved-region@aeb00000 {
617 no-map;
621 smp2p-adsp {
624 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
630 qcom,local-pid = <0>;
631 qcom,remote-pid = <2>;
633 smp2p_adsp_out: master-kernel {
634 qcom,entry-name = "master-kernel";
635 #qcom,smem-state-cells = <1>;
638 smp2p_adsp_in: slave-kernel {
639 qcom,entry-name = "slave-kernel";
640 interrupt-controller;
641 #interrupt-cells = <2>;
645 smp2p-nsp0 {
648 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
654 qcom,local-pid = <0>;
655 qcom,remote-pid = <5>;
657 smp2p_nsp0_out: master-kernel {
658 qcom,entry-name = "master-kernel";
659 #qcom,smem-state-cells = <1>;
662 smp2p_nsp0_in: slave-kernel {
663 qcom,entry-name = "slave-kernel";
664 interrupt-controller;
665 #interrupt-cells = <2>;
669 smp2p-nsp1 {
672 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
678 qcom,local-pid = <0>;
679 qcom,remote-pid = <12>;
681 smp2p_nsp1_out: master-kernel {
682 qcom,entry-name = "master-kernel";
683 #qcom,smem-state-cells = <1>;
686 smp2p_nsp1_in: slave-kernel {
687 qcom,entry-name = "slave-kernel";
688 interrupt-controller;
689 #interrupt-cells = <2>;
694 compatible = "simple-bus";
695 #address-cells = <2>;
696 #size-cells = <2>;
698 dma-ranges = <0 0 0 0 0x10 0>;
700 gcc: clock-controller@100000 {
701 compatible = "qcom,gcc-sc8280xp";
703 #clock-cells = <1>;
704 #reset-cells = <1>;
705 #power-domain-cells = <1>;
739 power-domains = <&rpmhpd SC8280XP_CX>;
743 compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc";
746 interrupt-controller;
747 #interrupt-cells = <3>;
748 #mbox-cells = <2>;
752 compatible = "qcom,geni-se-qup";
756 clock-names = "m-ahb", "s-ahb";
759 #address-cells = <2>;
760 #size-cells = <2>;
766 compatible = "qcom,geni-uart";
769 clock-names = "se";
771 operating-points-v2 = <&qup_opp_table_100mhz>;
772 power-domains = <&rpmhpd SC8280XP_CX>;
775 interconnect-names = "qup-core", "qup-config";
780 compatible = "qcom,geni-i2c";
782 clock-names = "se";
785 #address-cells = <1>;
786 #size-cells = <0>;
787 power-domains = <&rpmhpd SC8280XP_CX>;
791 interconnect-names = "qup-core", "qup-config", "qup-memory";
797 compatible = "qcom,geni-se-qup";
801 clock-names = "m-ahb", "s-ahb";
804 #address-cells = <2>;
805 #size-cells = <2>;
811 compatible = "qcom,geni-i2c";
813 clock-names = "se";
816 #address-cells = <1>;
817 #size-cells = <0>;
818 power-domains = <&rpmhpd SC8280XP_CX>;
822 interconnect-names = "qup-core", "qup-config", "qup-memory";
828 compatible = "qcom,geni-se-qup";
832 clock-names = "m-ahb", "s-ahb";
835 #address-cells = <2>;
836 #size-cells = <2>;
843 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
844 "jedec,ufs-2.0";
848 phy-names = "ufsphy";
849 lanes-per-direction = <2>;
850 #reset-cells = <1>;
852 reset-names = "rst";
854 power-domains = <&gcc UFS_PHY_GDSC>;
855 required-opps = <&rpmhpd_opp_nom>;
867 clock-names = "core_clk",
875 freq-table-hz = <75000000 300000000>,
887 compatible = "qcom,sc8280xp-qmp-ufs-phy";
889 #address-cells = <2>;
890 #size-cells = <2>;
892 clock-names = "ref",
898 reset-names = "ufsphy";
907 #phy-cells = <0>;
912 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
913 "jedec,ufs-2.0";
917 phy-names = "ufsphy";
918 lanes-per-direction = <2>;
919 #reset-cells = <1>;
921 reset-names = "rst";
923 power-domains = <&gcc UFS_CARD_GDSC>;
935 clock-names = "core_clk",
943 freq-table-hz = <75000000 300000000>,
955 compatible = "qcom,sc8280xp-qmp-ufs-phy";
957 #address-cells = <2>;
958 #size-cells = <2>;
960 clock-names = "ref",
966 reset-names = "ufsphy";
976 #phy-cells = <0>;
981 compatible = "qcom,tcsr-mutex";
983 #hwlock-cells = <1>;
987 compatible = "qcom,sc8280xp-usb-hs-phy",
988 "qcom,usb-snps-hs-5nm-phy";
991 clock-names = "ref";
994 #phy-cells = <0>;
1000 compatible = "qcom,sc8280xp-usb-hs-phy",
1001 "qcom,usb-snps-hs-5nm-phy";
1004 clock-names = "ref";
1007 #phy-cells = <0>;
1013 compatible = "qcom,sc8280xp-usb-hs-phy",
1014 "qcom,usb-snps-hs-5nm-phy";
1017 clock-names = "ref";
1020 #phy-cells = <0>;
1026 compatible = "qcom,sc8280xp-usb-hs-phy",
1027 "qcom,usb-snps-hs-5nm-phy";
1030 clock-names = "ref";
1033 #phy-cells = <0>;
1039 compatible = "qcom,sc8280xp-usb-hs-phy",
1040 "qcom,usb-snps-hs-5nm-phy";
1043 clock-names = "ref";
1046 #phy-cells = <0>;
1051 usb_2_qmpphy0: phy-wrapper@88ef000 {
1052 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
1054 #address-cells = <2>;
1055 #size-cells = <2>;
1062 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
1066 reset-names = "phy", "common";
1068 power-domains = <&gcc USB30_MP_GDSC>;
1076 #phy-cells = <0>;
1077 #clock-cells = <0>;
1079 clock-names = "pipe0";
1080 clock-output-names = "usb2_phy0_pipe_clk";
1084 usb_2_qmpphy1: phy-wrapper@88f1000 {
1085 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
1087 #address-cells = <2>;
1088 #size-cells = <2>;
1095 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
1099 reset-names = "phy", "common";
1101 power-domains = <&gcc USB30_MP_GDSC>;
1109 #phy-cells = <0>;
1110 #clock-cells = <0>;
1112 clock-names = "pipe0";
1113 clock-output-names = "usb2_phy1_pipe_clk";
1118 compatible = "qcom,sc8280xp-adsp-pas";
1121 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
1127 interrupt-names = "wdog", "fatal", "ready",
1128 "handover", "stop-ack", "shutdown-ack";
1131 clock-names = "xo";
1133 power-domains = <&rpmhpd SC8280XP_LCX>,
1135 power-domain-names = "lcx", "lmx";
1137 memory-region = <&pil_adsp_mem>;
1141 qcom,smem-states = <&smp2p_adsp_out 0>;
1142 qcom,smem-state-names = "stop";
1146 remoteproc_adsp_glink: glink-edge {
1147 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
1154 qcom,remote-pid = <2>;
1158 usb_0_qmpphy: phy-wrapper@88ec000 {
1159 compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
1163 #address-cells = <2>;
1164 #size-cells = <2>;
1171 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
1175 reset-names = "phy", "common";
1177 power-domains = <&gcc USB30_PRIM_GDSC>;
1181 usb_0_ssphy: usb3-phy@88eb400 {
1188 #phy-cells = <0>;
1189 #clock-cells = <0>;
1191 clock-names = "pipe0";
1192 clock-output-names = "usb0_phy_pipe_clk_src";
1197 compatible = "qcom,sc8280xp-usb-hs-phy",
1198 "qcom,usb-snps-hs-5nm-phy";
1200 #phy-cells = <0>;
1203 clock-names = "ref";
1210 usb_1_qmpphy: phy-wrapper@8904000 {
1211 compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
1215 #address-cells = <2>;
1216 #size-cells = <2>;
1223 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
1227 reset-names = "phy", "common";
1229 power-domains = <&gcc USB30_SEC_GDSC>;
1233 usb_1_ssphy: usb3-phy@8903400 {
1240 #phy-cells = <0>;
1241 #clock-cells = <0>;
1243 clock-names = "pipe0";
1244 clock-output-names = "usb1_phy_pipe_clk_src";
1248 system-cache-controller@9200000 {
1249 compatible = "qcom,sc8280xp-llcc";
1251 reg-names = "llcc_base", "llcc_broadcast_base";
1256 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
1258 #address-cells = <2>;
1259 #size-cells = <2>;
1271 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
1274 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1276 assigned-clock-rates = <19200000>, <200000000>;
1278 interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
1282 interrupt-names = "pwr_event",
1287 power-domains = <&gcc USB30_PRIM_GDSC>;
1293 interconnect-names = "usb-ddr", "apps-usb";
1295 wakeup-source;
1305 phy-names = "usb2-phy", "usb3-phy";
1310 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
1312 #address-cells = <2>;
1313 #size-cells = <2>;
1325 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
1328 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1330 assigned-clock-rates = <19200000>, <200000000>;
1332 interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
1336 interrupt-names = "pwr_event",
1341 power-domains = <&gcc USB30_SEC_GDSC>;
1347 interconnect-names = "usb-ddr", "apps-usb";
1349 wakeup-source;
1359 phy-names = "usb2-phy", "usb3-phy";
1363 pdc: interrupt-controller@b220000 {
1364 compatible = "qcom,sc8280xp-pdc", "qcom,pdc";
1366 qcom,pdc-ranges = <0 480 40>,
1423 #interrupt-cells = <2>;
1424 interrupt-parent = <&intc>;
1425 interrupt-controller;
1428 tsens0: thermal-sensor@c263000 {
1429 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
1433 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
1435 interrupt-names = "uplow", "critical";
1436 #thermal-sensor-cells = <1>;
1439 tsens1: thermal-sensor@c265000 {
1440 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
1444 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
1446 interrupt-names = "uplow", "critical";
1447 #thermal-sensor-cells = <1>;
1450 aoss_qmp: power-controller@c300000 {
1451 compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp";
1453 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>;
1456 #clock-cells = <0>;
1460 compatible = "qcom,spmi-pmic-arb";
1466 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1467 interrupt-names = "periph_irq";
1468 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
1471 #address-cells = <1>;
1472 #size-cells = <1>;
1473 interrupt-controller;
1474 #interrupt-cells = <4>;
1478 compatible = "qcom,sc8280xp-tlmm";
1481 gpio-controller;
1482 #gpio-cells = <2>;
1483 interrupt-controller;
1484 #interrupt-cells = <2>;
1485 gpio-ranges = <&tlmm 0 0 230>;
1489 compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500";
1491 #iommu-cells = <2>;
1492 #global-interrupts = <2>;
1625 intc: interrupt-controller@17a00000 {
1626 compatible = "arm,gic-v3";
1627 interrupt-controller;
1628 #interrupt-cells = <3>;
1632 #redistributor-regions = <1>;
1633 redistributor-stride = <0 0x20000>;
1635 #address-cells = <2>;
1636 #size-cells = <2>;
1639 gic-its@17a40000 {
1640 compatible = "arm,gic-v3-its";
1642 msi-controller;
1643 #msi-cells = <1>;
1648 compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt";
1655 compatible = "arm,armv7-timer-mem";
1657 #address-cells = <1>;
1658 #size-cells = <1>;
1662 frame-number = <0>;
1670 frame-number = <1>;
1677 frame-number = <2>;
1684 frame-number = <3>;
1691 frame-number = <4>;
1698 frame-number = <5>;
1705 frame-number = <6>;
1713 compatible = "qcom,rpmh-rsc";
1717 reg-names = "drv-0", "drv-1", "drv-2";
1721 qcom,tcs-offset = <0xd00>;
1722 qcom,drv-id = <2>;
1723 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
1727 apps_bcm_voter: bcm-voter {
1728 compatible = "qcom,bcm-voter";
1731 rpmhcc: clock-controller {
1732 compatible = "qcom,sc8280xp-rpmh-clk";
1733 #clock-cells = <1>;
1734 clock-names = "xo";
1738 rpmhpd: power-controller {
1739 compatible = "qcom,sc8280xp-rpmhpd";
1740 #power-domain-cells = <1>;
1741 operating-points-v2 = <&rpmhpd_opp_table>;
1743 rpmhpd_opp_table: opp-table {
1744 compatible = "operating-points-v2";
1747 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1751 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1755 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1759 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1763 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1767 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1771 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1775 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
1779 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1783 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1790 compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss";
1793 reg-names = "freq-domain0", "freq-domain1";
1796 clock-names = "xo", "alternate";
1798 #freq-domain-cells = <1>;
1802 compatible = "qcom,sc8280xp-nsp0-pas";
1805 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
1810 interrupt-names = "wdog", "fatal", "ready",
1811 "handover", "stop-ack";
1814 clock-names = "xo";
1816 power-domains = <&rpmhpd SC8280XP_NSP>;
1817 power-domain-names = "nsp";
1819 memory-region = <&pil_nsp0_mem>;
1821 qcom,smem-states = <&smp2p_nsp0_out 0>;
1822 qcom,smem-state-names = "stop";
1828 glink-edge {
1829 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
1836 qcom,remote-pid = <5>;
1838 fastrpc {
1839 compatible = "qcom,fastrpc";
1840 qcom,glink-channels = "fastrpcglink-apps-dsp";
1842 #address-cells = <1>;
1843 #size-cells = <0>;
1845 compute-cb@1 {
1846 compatible = "qcom,fastrpc-compute-cb";
1851 compute-cb@2 {
1852 compatible = "qcom,fastrpc-compute-cb";
1857 compute-cb@3 {
1858 compatible = "qcom,fastrpc-compute-cb";
1863 compute-cb@4 {
1864 compatible = "qcom,fastrpc-compute-cb";
1869 compute-cb@5 {
1870 compatible = "qcom,fastrpc-compute-cb";
1875 compute-cb@6 {
1876 compatible = "qcom,fastrpc-compute-cb";
1881 compute-cb@7 {
1882 compatible = "qcom,fastrpc-compute-cb";
1887 compute-cb@8 {
1888 compatible = "qcom,fastrpc-compute-cb";
1893 compute-cb@9 {
1894 compatible = "qcom,fastrpc-compute-cb";
1899 compute-cb@10 {
1900 compatible = "qcom,fastrpc-compute-cb";
1905 compute-cb@11 {
1906 compatible = "qcom,fastrpc-compute-cb";
1911 compute-cb@12 {
1912 compatible = "qcom,fastrpc-compute-cb";
1917 compute-cb@13 {
1918 compatible = "qcom,fastrpc-compute-cb";
1923 compute-cb@14 {
1924 compatible = "qcom,fastrpc-compute-cb";
1933 compatible = "qcom,sc8280xp-nsp1-pas";
1936 interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
1941 interrupt-names = "wdog", "fatal", "ready",
1942 "handover", "stop-ack";
1945 clock-names = "xo";
1947 power-domains = <&rpmhpd SC8280XP_NSP>;
1948 power-domain-names = "nsp";
1950 memory-region = <&pil_nsp1_mem>;
1952 qcom,smem-states = <&smp2p_nsp1_out 0>;
1953 qcom,smem-state-names = "stop";
1959 glink-edge {
1960 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
1967 qcom,remote-pid = <12>;
1972 thermal-zones {
1973 cpu0-thermal {
1974 polling-delay-passive = <250>;
1975 polling-delay = <1000>;
1977 thermal-sensors = <&tsens0 1>;
1980 cpu-crit {
1988 cpu1-thermal {
1989 polling-delay-passive = <250>;
1990 polling-delay = <1000>;
1992 thermal-sensors = <&tsens0 2>;
1995 cpu-crit {
2003 cpu2-thermal {
2004 polling-delay-passive = <250>;
2005 polling-delay = <1000>;
2007 thermal-sensors = <&tsens0 3>;
2010 cpu-crit {
2018 cpu3-thermal {
2019 polling-delay-passive = <250>;
2020 polling-delay = <1000>;
2022 thermal-sensors = <&tsens0 4>;
2025 cpu-crit {
2033 cpu4-thermal {
2034 polling-delay-passive = <250>;
2035 polling-delay = <1000>;
2037 thermal-sensors = <&tsens0 5>;
2040 cpu-crit {
2048 cpu5-thermal {
2049 polling-delay-passive = <250>;
2050 polling-delay = <1000>;
2052 thermal-sensors = <&tsens0 6>;
2055 cpu-crit {
2063 cpu6-thermal {
2064 polling-delay-passive = <250>;
2065 polling-delay = <1000>;
2067 thermal-sensors = <&tsens0 7>;
2070 cpu-crit {
2078 cpu7-thermal {
2079 polling-delay-passive = <250>;
2080 polling-delay = <1000>;
2082 thermal-sensors = <&tsens0 8>;
2085 cpu-crit {
2093 cluster0-thermal {
2094 polling-delay-passive = <250>;
2095 polling-delay = <1000>;
2097 thermal-sensors = <&tsens0 9>;
2100 cpu-crit {
2108 mem-thermal {
2109 polling-delay-passive = <250>;
2110 polling-delay = <1000>;
2112 thermal-sensors = <&tsens1 15>;
2115 trip-point0 {
2125 compatible = "arm,armv8-timer";