Lines Matching +full:opp +full:- +full:160000000
1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
7 #include <dt-bindings/clock/qcom,camcc-sc7280.h>
8 #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7280.h>
11 #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
12 #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sc7280.h>
15 #include <dt-bindings/dma/qcom-gpi.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interconnect/qcom,osm-l3.h>
18 #include <dt-bindings/interconnect/qcom,sc7280.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 #include <dt-bindings/mailbox/qcom-ipcc.h>
21 #include <dt-bindings/power/qcom-rpmpd.h>
22 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
23 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
24 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
25 #include <dt-bindings/sound/qcom,lpass.h>
26 #include <dt-bindings/thermal/thermal.h>
29 interrupt-parent = <&intc>;
31 #address-cells = <2>;
32 #size-cells = <2>;
74 xo_board: xo-board {
75 compatible = "fixed-clock";
76 clock-frequency = <76800000>;
77 #clock-cells = <0>;
80 sleep_clk: sleep-clk {
81 compatible = "fixed-clock";
82 clock-frequency = <32000>;
83 #clock-cells = <0>;
87 reserved-memory {
88 #address-cells = <2>;
89 #size-cells = <2>;
93 no-map;
99 no-map;
104 no-map;
109 no-map;
114 compatible = "qcom,cmd-db";
115 no-map;
120 no-map;
125 no-map;
130 no-map;
134 no-map;
140 no-map;
145 no-map;
150 no-map;
154 compatible = "qcom,rmtfs-mem";
156 no-map;
158 qcom,client-id = <1>;
164 #address-cells = <2>;
165 #size-cells = <0>;
171 enable-method = "psci";
172 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
175 next-level-cache = <&L2_0>;
176 operating-points-v2 = <&cpu0_opp_table>;
179 qcom,freq-domain = <&cpufreq_hw 0>;
180 #cooling-cells = <2>;
181 L2_0: l2-cache {
183 next-level-cache = <&L3_0>;
184 L3_0: l3-cache {
194 enable-method = "psci";
195 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
198 next-level-cache = <&L2_100>;
199 operating-points-v2 = <&cpu0_opp_table>;
202 qcom,freq-domain = <&cpufreq_hw 0>;
203 #cooling-cells = <2>;
204 L2_100: l2-cache {
206 next-level-cache = <&L3_0>;
214 enable-method = "psci";
215 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
218 next-level-cache = <&L2_200>;
219 operating-points-v2 = <&cpu0_opp_table>;
222 qcom,freq-domain = <&cpufreq_hw 0>;
223 #cooling-cells = <2>;
224 L2_200: l2-cache {
226 next-level-cache = <&L3_0>;
234 enable-method = "psci";
235 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
238 next-level-cache = <&L2_300>;
239 operating-points-v2 = <&cpu0_opp_table>;
242 qcom,freq-domain = <&cpufreq_hw 0>;
243 #cooling-cells = <2>;
244 L2_300: l2-cache {
246 next-level-cache = <&L3_0>;
254 enable-method = "psci";
255 cpu-idle-states = <&BIG_CPU_SLEEP_0
258 next-level-cache = <&L2_400>;
259 operating-points-v2 = <&cpu4_opp_table>;
262 qcom,freq-domain = <&cpufreq_hw 1>;
263 #cooling-cells = <2>;
264 L2_400: l2-cache {
266 next-level-cache = <&L3_0>;
274 enable-method = "psci";
275 cpu-idle-states = <&BIG_CPU_SLEEP_0
278 next-level-cache = <&L2_500>;
279 operating-points-v2 = <&cpu4_opp_table>;
282 qcom,freq-domain = <&cpufreq_hw 1>;
283 #cooling-cells = <2>;
284 L2_500: l2-cache {
286 next-level-cache = <&L3_0>;
294 enable-method = "psci";
295 cpu-idle-states = <&BIG_CPU_SLEEP_0
298 next-level-cache = <&L2_600>;
299 operating-points-v2 = <&cpu4_opp_table>;
302 qcom,freq-domain = <&cpufreq_hw 1>;
303 #cooling-cells = <2>;
304 L2_600: l2-cache {
306 next-level-cache = <&L3_0>;
314 enable-method = "psci";
315 cpu-idle-states = <&BIG_CPU_SLEEP_0
318 next-level-cache = <&L2_700>;
319 operating-points-v2 = <&cpu7_opp_table>;
322 qcom,freq-domain = <&cpufreq_hw 2>;
323 #cooling-cells = <2>;
324 L2_700: l2-cache {
326 next-level-cache = <&L3_0>;
330 cpu-map {
366 idle-states {
367 entry-method = "psci";
369 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
370 compatible = "arm,idle-state";
371 idle-state-name = "little-power-down";
372 arm,psci-suspend-param = <0x40000003>;
373 entry-latency-us = <549>;
374 exit-latency-us = <901>;
375 min-residency-us = <1774>;
376 local-timer-stop;
379 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
380 compatible = "arm,idle-state";
381 idle-state-name = "little-rail-power-down";
382 arm,psci-suspend-param = <0x40000004>;
383 entry-latency-us = <702>;
384 exit-latency-us = <915>;
385 min-residency-us = <4001>;
386 local-timer-stop;
389 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
390 compatible = "arm,idle-state";
391 idle-state-name = "big-power-down";
392 arm,psci-suspend-param = <0x40000003>;
393 entry-latency-us = <523>;
394 exit-latency-us = <1244>;
395 min-residency-us = <2207>;
396 local-timer-stop;
399 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
400 compatible = "arm,idle-state";
401 idle-state-name = "big-rail-power-down";
402 arm,psci-suspend-param = <0x40000004>;
403 entry-latency-us = <526>;
404 exit-latency-us = <1854>;
405 min-residency-us = <5555>;
406 local-timer-stop;
409 CLUSTER_SLEEP_0: cluster-sleep-0 {
410 compatible = "arm,idle-state";
411 idle-state-name = "cluster-power-down";
412 arm,psci-suspend-param = <0x40003444>;
413 entry-latency-us = <3263>;
414 exit-latency-us = <6562>;
415 min-residency-us = <9926>;
416 local-timer-stop;
421 cpu0_opp_table: opp-table-cpu0 {
422 compatible = "operating-points-v2";
423 opp-shared;
425 cpu0_opp_300mhz: opp-300000000 {
426 opp-hz = /bits/ 64 <300000000>;
427 opp-peak-kBps = <800000 9600000>;
430 cpu0_opp_691mhz: opp-691200000 {
431 opp-hz = /bits/ 64 <691200000>;
432 opp-peak-kBps = <800000 17817600>;
435 cpu0_opp_806mhz: opp-806400000 {
436 opp-hz = /bits/ 64 <806400000>;
437 opp-peak-kBps = <800000 20889600>;
440 cpu0_opp_941mhz: opp-940800000 {
441 opp-hz = /bits/ 64 <940800000>;
442 opp-peak-kBps = <1804000 24576000>;
445 cpu0_opp_1152mhz: opp-1152000000 {
446 opp-hz = /bits/ 64 <1152000000>;
447 opp-peak-kBps = <2188000 27033600>;
450 cpu0_opp_1325mhz: opp-1324800000 {
451 opp-hz = /bits/ 64 <1324800000>;
452 opp-peak-kBps = <2188000 33792000>;
455 cpu0_opp_1517mhz: opp-1516800000 {
456 opp-hz = /bits/ 64 <1516800000>;
457 opp-peak-kBps = <3072000 38092800>;
460 cpu0_opp_1651mhz: opp-1651200000 {
461 opp-hz = /bits/ 64 <1651200000>;
462 opp-peak-kBps = <3072000 41779200>;
465 cpu0_opp_1805mhz: opp-1804800000 {
466 opp-hz = /bits/ 64 <1804800000>;
467 opp-peak-kBps = <4068000 48537600>;
470 cpu0_opp_1958mhz: opp-1958400000 {
471 opp-hz = /bits/ 64 <1958400000>;
472 opp-peak-kBps = <4068000 48537600>;
475 cpu0_opp_2016mhz: opp-2016000000 {
476 opp-hz = /bits/ 64 <2016000000>;
477 opp-peak-kBps = <6220000 48537600>;
481 cpu4_opp_table: opp-table-cpu4 {
482 compatible = "operating-points-v2";
483 opp-shared;
485 cpu4_opp_691mhz: opp-691200000 {
486 opp-hz = /bits/ 64 <691200000>;
487 opp-peak-kBps = <1804000 9600000>;
490 cpu4_opp_941mhz: opp-940800000 {
491 opp-hz = /bits/ 64 <940800000>;
492 opp-peak-kBps = <2188000 17817600>;
495 cpu4_opp_1229mhz: opp-1228800000 {
496 opp-hz = /bits/ 64 <1228800000>;
497 opp-peak-kBps = <4068000 24576000>;
500 cpu4_opp_1344mhz: opp-1344000000 {
501 opp-hz = /bits/ 64 <1344000000>;
502 opp-peak-kBps = <4068000 24576000>;
505 cpu4_opp_1517mhz: opp-1516800000 {
506 opp-hz = /bits/ 64 <1516800000>;
507 opp-peak-kBps = <4068000 24576000>;
510 cpu4_opp_1651mhz: opp-1651200000 {
511 opp-hz = /bits/ 64 <1651200000>;
512 opp-peak-kBps = <6220000 38092800>;
515 cpu4_opp_1901mhz: opp-1900800000 {
516 opp-hz = /bits/ 64 <1900800000>;
517 opp-peak-kBps = <6220000 44851200>;
520 cpu4_opp_2054mhz: opp-2054400000 {
521 opp-hz = /bits/ 64 <2054400000>;
522 opp-peak-kBps = <6220000 44851200>;
525 cpu4_opp_2112mhz: opp-2112000000 {
526 opp-hz = /bits/ 64 <2112000000>;
527 opp-peak-kBps = <6220000 44851200>;
530 cpu4_opp_2131mhz: opp-2131200000 {
531 opp-hz = /bits/ 64 <2131200000>;
532 opp-peak-kBps = <6220000 44851200>;
535 cpu4_opp_2208mhz: opp-2208000000 {
536 opp-hz = /bits/ 64 <2208000000>;
537 opp-peak-kBps = <6220000 44851200>;
540 cpu4_opp_2400mhz: opp-2400000000 {
541 opp-hz = /bits/ 64 <2400000000>;
542 opp-peak-kBps = <8532000 48537600>;
545 cpu4_opp_2611mhz: opp-2611200000 {
546 opp-hz = /bits/ 64 <2611200000>;
547 opp-peak-kBps = <8532000 48537600>;
551 cpu7_opp_table: opp-table-cpu7 {
552 compatible = "operating-points-v2";
553 opp-shared;
555 cpu7_opp_806mhz: opp-806400000 {
556 opp-hz = /bits/ 64 <806400000>;
557 opp-peak-kBps = <1804000 9600000>;
560 cpu7_opp_1056mhz: opp-1056000000 {
561 opp-hz = /bits/ 64 <1056000000>;
562 opp-peak-kBps = <2188000 17817600>;
565 cpu7_opp_1325mhz: opp-1324800000 {
566 opp-hz = /bits/ 64 <1324800000>;
567 opp-peak-kBps = <4068000 24576000>;
570 cpu7_opp_1517mhz: opp-1516800000 {
571 opp-hz = /bits/ 64 <1516800000>;
572 opp-peak-kBps = <4068000 24576000>;
575 cpu7_opp_1766mhz: opp-1766400000 {
576 opp-hz = /bits/ 64 <1766400000>;
577 opp-peak-kBps = <6220000 38092800>;
580 cpu7_opp_1862mhz: opp-1862400000 {
581 opp-hz = /bits/ 64 <1862400000>;
582 opp-peak-kBps = <6220000 38092800>;
585 cpu7_opp_2035mhz: opp-2035200000 {
586 opp-hz = /bits/ 64 <2035200000>;
587 opp-peak-kBps = <6220000 38092800>;
590 cpu7_opp_2112mhz: opp-2112000000 {
591 opp-hz = /bits/ 64 <2112000000>;
592 opp-peak-kBps = <6220000 44851200>;
595 cpu7_opp_2208mhz: opp-2208000000 {
596 opp-hz = /bits/ 64 <2208000000>;
597 opp-peak-kBps = <6220000 44851200>;
600 cpu7_opp_2381mhz: opp-2380800000 {
601 opp-hz = /bits/ 64 <2380800000>;
602 opp-peak-kBps = <6832000 44851200>;
605 cpu7_opp_2400mhz: opp-2400000000 {
606 opp-hz = /bits/ 64 <2400000000>;
607 opp-peak-kBps = <8532000 48537600>;
610 cpu7_opp_2515mhz: opp-2515200000 {
611 opp-hz = /bits/ 64 <2515200000>;
612 opp-peak-kBps = <8532000 48537600>;
615 cpu7_opp_2707mhz: opp-2707200000 {
616 opp-hz = /bits/ 64 <2707200000>;
617 opp-peak-kBps = <8532000 48537600>;
620 cpu7_opp_3014mhz: opp-3014400000 {
621 opp-hz = /bits/ 64 <3014400000>;
622 opp-peak-kBps = <8532000 48537600>;
634 compatible = "qcom,scm-sc7280", "qcom,scm";
639 compatible = "qcom,sc7280-clk-virt";
640 #interconnect-cells = <2>;
641 qcom,bcm-voters = <&apps_bcm_voter>;
646 memory-region = <&smem_mem>;
650 smp2p-adsp {
653 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
659 qcom,local-pid = <0>;
660 qcom,remote-pid = <2>;
662 adsp_smp2p_out: master-kernel {
663 qcom,entry-name = "master-kernel";
664 #qcom,smem-state-cells = <1>;
667 adsp_smp2p_in: slave-kernel {
668 qcom,entry-name = "slave-kernel";
669 interrupt-controller;
670 #interrupt-cells = <2>;
674 smp2p-cdsp {
677 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
683 qcom,local-pid = <0>;
684 qcom,remote-pid = <5>;
686 cdsp_smp2p_out: master-kernel {
687 qcom,entry-name = "master-kernel";
688 #qcom,smem-state-cells = <1>;
691 cdsp_smp2p_in: slave-kernel {
692 qcom,entry-name = "slave-kernel";
693 interrupt-controller;
694 #interrupt-cells = <2>;
698 smp2p-mpss {
701 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
707 qcom,local-pid = <0>;
708 qcom,remote-pid = <1>;
710 modem_smp2p_out: master-kernel {
711 qcom,entry-name = "master-kernel";
712 #qcom,smem-state-cells = <1>;
715 modem_smp2p_in: slave-kernel {
716 qcom,entry-name = "slave-kernel";
717 interrupt-controller;
718 #interrupt-cells = <2>;
721 ipa_smp2p_out: ipa-ap-to-modem {
722 qcom,entry-name = "ipa";
723 #qcom,smem-state-cells = <1>;
726 ipa_smp2p_in: ipa-modem-to-ap {
727 qcom,entry-name = "ipa";
728 interrupt-controller;
729 #interrupt-cells = <2>;
733 smp2p-wpss {
736 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
742 qcom,local-pid = <0>;
743 qcom,remote-pid = <13>;
745 wpss_smp2p_out: master-kernel {
746 qcom,entry-name = "master-kernel";
747 #qcom,smem-state-cells = <1>;
750 wpss_smp2p_in: slave-kernel {
751 qcom,entry-name = "slave-kernel";
752 interrupt-controller;
753 #interrupt-cells = <2>;
758 compatible = "arm,armv8-pmuv3";
763 compatible = "arm,psci-1.0";
767 qspi_opp_table: opp-table-qspi {
768 compatible = "operating-points-v2";
770 opp-75000000 {
771 opp-hz = /bits/ 64 <75000000>;
772 required-opps = <&rpmhpd_opp_low_svs>;
775 opp-150000000 {
776 opp-hz = /bits/ 64 <150000000>;
777 required-opps = <&rpmhpd_opp_svs>;
780 opp-200000000 {
781 opp-hz = /bits/ 64 <200000000>;
782 required-opps = <&rpmhpd_opp_svs_l1>;
785 opp-300000000 {
786 opp-hz = /bits/ 64 <300000000>;
787 required-opps = <&rpmhpd_opp_nom>;
791 qup_opp_table: opp-table-qup {
792 compatible = "operating-points-v2";
794 opp-75000000 {
795 opp-hz = /bits/ 64 <75000000>;
796 required-opps = <&rpmhpd_opp_low_svs>;
799 opp-100000000 {
800 opp-hz = /bits/ 64 <100000000>;
801 required-opps = <&rpmhpd_opp_svs>;
804 opp-128000000 {
805 opp-hz = /bits/ 64 <128000000>;
806 required-opps = <&rpmhpd_opp_nom>;
811 #address-cells = <2>;
812 #size-cells = <2>;
814 dma-ranges = <0 0 0 0 0x10 0>;
815 compatible = "simple-bus";
817 gcc: clock-controller@100000 {
818 compatible = "qcom,gcc-sc7280";
824 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
829 #clock-cells = <1>;
830 #reset-cells = <1>;
831 #power-domain-cells = <1>;
832 power-domains = <&rpmhpd SC7280_CX>;
836 compatible = "qcom,sc7280-ipcc", "qcom,ipcc";
839 interrupt-controller;
840 #interrupt-cells = <3>;
841 #mbox-cells = <2>;
845 compatible = "qcom,sc7280-qfprom", "qcom,qfprom";
851 clock-names = "core";
852 power-domains = <&rpmhpd SC7280_MX>;
853 #address-cells = <1>;
854 #size-cells = <1>;
863 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
864 pinctrl-names = "default", "sleep";
865 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>;
866 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>;
871 reg-names = "hc", "cqhci";
876 interrupt-names = "hc_irq", "pwr_irq";
881 clock-names = "iface", "core", "xo";
884 interconnect-names = "sdhc-ddr","cpu-sdhc";
885 power-domains = <&rpmhpd SC7280_CX>;
886 operating-points-v2 = <&sdhc1_opp_table>;
888 bus-width = <8>;
889 supports-cqe;
891 qcom,dll-config = <0x0007642c>;
892 qcom,ddr-config = <0x80040868>;
894 mmc-ddr-1_8v;
895 mmc-hs200-1_8v;
896 mmc-hs400-1_8v;
897 mmc-hs400-enhanced-strobe;
901 sdhc1_opp_table: opp-table {
902 compatible = "operating-points-v2";
904 opp-100000000 {
905 opp-hz = /bits/ 64 <100000000>;
906 required-opps = <&rpmhpd_opp_low_svs>;
907 opp-peak-kBps = <1800000 400000>;
908 opp-avg-kBps = <100000 0>;
911 opp-384000000 {
912 opp-hz = /bits/ 64 <384000000>;
913 required-opps = <&rpmhpd_opp_nom>;
914 opp-peak-kBps = <5400000 1600000>;
915 opp-avg-kBps = <390000 0>;
921 gpi_dma0: dma-controller@900000 {
922 #dma-cells = <3>;
923 compatible = "qcom,sc7280-gpi-dma";
937 dma-channels = <12>;
938 dma-channel-mask = <0x7f>;
944 compatible = "qcom,geni-se-qup";
948 clock-names = "m-ahb", "s-ahb";
949 #address-cells = <2>;
950 #size-cells = <2>;
956 compatible = "qcom,geni-i2c";
959 clock-names = "se";
960 pinctrl-names = "default";
961 pinctrl-0 = <&qup_i2c0_data_clk>;
963 #address-cells = <1>;
964 #size-cells = <0>;
968 interconnect-names = "qup-core", "qup-config",
969 "qup-memory";
972 dma-names = "tx", "rx";
977 compatible = "qcom,geni-spi";
980 clock-names = "se";
981 pinctrl-names = "default";
982 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
984 #address-cells = <1>;
985 #size-cells = <0>;
986 power-domains = <&rpmhpd SC7280_CX>;
987 operating-points-v2 = <&qup_opp_table>;
990 interconnect-names = "qup-core", "qup-config";
993 dma-names = "tx", "rx";
998 compatible = "qcom,geni-uart";
1001 clock-names = "se";
1002 pinctrl-names = "default";
1003 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>;
1005 power-domains = <&rpmhpd SC7280_CX>;
1006 operating-points-v2 = <&qup_opp_table>;
1009 interconnect-names = "qup-core", "qup-config";
1014 compatible = "qcom,geni-i2c";
1017 clock-names = "se";
1018 pinctrl-names = "default";
1019 pinctrl-0 = <&qup_i2c1_data_clk>;
1021 #address-cells = <1>;
1022 #size-cells = <0>;
1026 interconnect-names = "qup-core", "qup-config",
1027 "qup-memory";
1030 dma-names = "tx", "rx";
1035 compatible = "qcom,geni-spi";
1038 clock-names = "se";
1039 pinctrl-names = "default";
1040 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1042 #address-cells = <1>;
1043 #size-cells = <0>;
1044 power-domains = <&rpmhpd SC7280_CX>;
1045 operating-points-v2 = <&qup_opp_table>;
1048 interconnect-names = "qup-core", "qup-config";
1051 dma-names = "tx", "rx";
1056 compatible = "qcom,geni-uart";
1059 clock-names = "se";
1060 pinctrl-names = "default";
1061 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
1063 power-domains = <&rpmhpd SC7280_CX>;
1064 operating-points-v2 = <&qup_opp_table>;
1067 interconnect-names = "qup-core", "qup-config";
1072 compatible = "qcom,geni-i2c";
1075 clock-names = "se";
1076 pinctrl-names = "default";
1077 pinctrl-0 = <&qup_i2c2_data_clk>;
1079 #address-cells = <1>;
1080 #size-cells = <0>;
1084 interconnect-names = "qup-core", "qup-config",
1085 "qup-memory";
1088 dma-names = "tx", "rx";
1093 compatible = "qcom,geni-spi";
1096 clock-names = "se";
1097 pinctrl-names = "default";
1098 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1100 #address-cells = <1>;
1101 #size-cells = <0>;
1102 power-domains = <&rpmhpd SC7280_CX>;
1103 operating-points-v2 = <&qup_opp_table>;
1106 interconnect-names = "qup-core", "qup-config";
1109 dma-names = "tx", "rx";
1114 compatible = "qcom,geni-uart";
1117 clock-names = "se";
1118 pinctrl-names = "default";
1119 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>;
1121 power-domains = <&rpmhpd SC7280_CX>;
1122 operating-points-v2 = <&qup_opp_table>;
1125 interconnect-names = "qup-core", "qup-config";
1130 compatible = "qcom,geni-i2c";
1133 clock-names = "se";
1134 pinctrl-names = "default";
1135 pinctrl-0 = <&qup_i2c3_data_clk>;
1137 #address-cells = <1>;
1138 #size-cells = <0>;
1142 interconnect-names = "qup-core", "qup-config",
1143 "qup-memory";
1146 dma-names = "tx", "rx";
1151 compatible = "qcom,geni-spi";
1154 clock-names = "se";
1155 pinctrl-names = "default";
1156 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1158 #address-cells = <1>;
1159 #size-cells = <0>;
1160 power-domains = <&rpmhpd SC7280_CX>;
1161 operating-points-v2 = <&qup_opp_table>;
1164 interconnect-names = "qup-core", "qup-config";
1167 dma-names = "tx", "rx";
1172 compatible = "qcom,geni-uart";
1175 clock-names = "se";
1176 pinctrl-names = "default";
1177 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>;
1179 power-domains = <&rpmhpd SC7280_CX>;
1180 operating-points-v2 = <&qup_opp_table>;
1183 interconnect-names = "qup-core", "qup-config";
1188 compatible = "qcom,geni-i2c";
1191 clock-names = "se";
1192 pinctrl-names = "default";
1193 pinctrl-0 = <&qup_i2c4_data_clk>;
1195 #address-cells = <1>;
1196 #size-cells = <0>;
1200 interconnect-names = "qup-core", "qup-config",
1201 "qup-memory";
1204 dma-names = "tx", "rx";
1209 compatible = "qcom,geni-spi";
1212 clock-names = "se";
1213 pinctrl-names = "default";
1214 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1216 #address-cells = <1>;
1217 #size-cells = <0>;
1218 power-domains = <&rpmhpd SC7280_CX>;
1219 operating-points-v2 = <&qup_opp_table>;
1222 interconnect-names = "qup-core", "qup-config";
1225 dma-names = "tx", "rx";
1230 compatible = "qcom,geni-uart";
1233 clock-names = "se";
1234 pinctrl-names = "default";
1235 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>;
1237 power-domains = <&rpmhpd SC7280_CX>;
1238 operating-points-v2 = <&qup_opp_table>;
1241 interconnect-names = "qup-core", "qup-config";
1246 compatible = "qcom,geni-i2c";
1249 clock-names = "se";
1250 pinctrl-names = "default";
1251 pinctrl-0 = <&qup_i2c5_data_clk>;
1253 #address-cells = <1>;
1254 #size-cells = <0>;
1258 interconnect-names = "qup-core", "qup-config",
1259 "qup-memory";
1262 dma-names = "tx", "rx";
1267 compatible = "qcom,geni-spi";
1270 clock-names = "se";
1271 pinctrl-names = "default";
1272 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1274 #address-cells = <1>;
1275 #size-cells = <0>;
1276 power-domains = <&rpmhpd SC7280_CX>;
1277 operating-points-v2 = <&qup_opp_table>;
1280 interconnect-names = "qup-core", "qup-config";
1283 dma-names = "tx", "rx";
1288 compatible = "qcom,geni-uart";
1291 clock-names = "se";
1292 pinctrl-names = "default";
1293 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>;
1295 power-domains = <&rpmhpd SC7280_CX>;
1296 operating-points-v2 = <&qup_opp_table>;
1299 interconnect-names = "qup-core", "qup-config";
1304 compatible = "qcom,geni-i2c";
1307 clock-names = "se";
1308 pinctrl-names = "default";
1309 pinctrl-0 = <&qup_i2c6_data_clk>;
1311 #address-cells = <1>;
1312 #size-cells = <0>;
1316 interconnect-names = "qup-core", "qup-config",
1317 "qup-memory";
1320 dma-names = "tx", "rx";
1325 compatible = "qcom,geni-spi";
1328 clock-names = "se";
1329 pinctrl-names = "default";
1330 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1332 #address-cells = <1>;
1333 #size-cells = <0>;
1334 power-domains = <&rpmhpd SC7280_CX>;
1335 operating-points-v2 = <&qup_opp_table>;
1338 interconnect-names = "qup-core", "qup-config";
1341 dma-names = "tx", "rx";
1346 compatible = "qcom,geni-uart";
1349 clock-names = "se";
1350 pinctrl-names = "default";
1351 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>;
1353 power-domains = <&rpmhpd SC7280_CX>;
1354 operating-points-v2 = <&qup_opp_table>;
1357 interconnect-names = "qup-core", "qup-config";
1362 compatible = "qcom,geni-i2c";
1365 clock-names = "se";
1366 pinctrl-names = "default";
1367 pinctrl-0 = <&qup_i2c7_data_clk>;
1369 #address-cells = <1>;
1370 #size-cells = <0>;
1374 interconnect-names = "qup-core", "qup-config",
1375 "qup-memory";
1378 dma-names = "tx", "rx";
1383 compatible = "qcom,geni-spi";
1386 clock-names = "se";
1387 pinctrl-names = "default";
1388 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
1390 #address-cells = <1>;
1391 #size-cells = <0>;
1392 power-domains = <&rpmhpd SC7280_CX>;
1393 operating-points-v2 = <&qup_opp_table>;
1396 interconnect-names = "qup-core", "qup-config";
1399 dma-names = "tx", "rx";
1404 compatible = "qcom,geni-uart";
1407 clock-names = "se";
1408 pinctrl-names = "default";
1409 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>;
1411 power-domains = <&rpmhpd SC7280_CX>;
1412 operating-points-v2 = <&qup_opp_table>;
1415 interconnect-names = "qup-core", "qup-config";
1420 gpi_dma1: dma-controller@a00000 {
1421 #dma-cells = <3>;
1422 compatible = "qcom,sc7280-gpi-dma";
1436 dma-channels = <12>;
1437 dma-channel-mask = <0x1e>;
1443 compatible = "qcom,geni-se-qup";
1447 clock-names = "m-ahb", "s-ahb";
1448 #address-cells = <2>;
1449 #size-cells = <2>;
1455 compatible = "qcom,geni-i2c";
1458 clock-names = "se";
1459 pinctrl-names = "default";
1460 pinctrl-0 = <&qup_i2c8_data_clk>;
1462 #address-cells = <1>;
1463 #size-cells = <0>;
1467 interconnect-names = "qup-core", "qup-config",
1468 "qup-memory";
1471 dma-names = "tx", "rx";
1476 compatible = "qcom,geni-spi";
1479 clock-names = "se";
1480 pinctrl-names = "default";
1481 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1483 #address-cells = <1>;
1484 #size-cells = <0>;
1485 power-domains = <&rpmhpd SC7280_CX>;
1486 operating-points-v2 = <&qup_opp_table>;
1489 interconnect-names = "qup-core", "qup-config";
1492 dma-names = "tx", "rx";
1497 compatible = "qcom,geni-uart";
1500 clock-names = "se";
1501 pinctrl-names = "default";
1502 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>;
1504 power-domains = <&rpmhpd SC7280_CX>;
1505 operating-points-v2 = <&qup_opp_table>;
1508 interconnect-names = "qup-core", "qup-config";
1513 compatible = "qcom,geni-i2c";
1516 clock-names = "se";
1517 pinctrl-names = "default";
1518 pinctrl-0 = <&qup_i2c9_data_clk>;
1520 #address-cells = <1>;
1521 #size-cells = <0>;
1525 interconnect-names = "qup-core", "qup-config",
1526 "qup-memory";
1529 dma-names = "tx", "rx";
1534 compatible = "qcom,geni-spi";
1537 clock-names = "se";
1538 pinctrl-names = "default";
1539 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1541 #address-cells = <1>;
1542 #size-cells = <0>;
1543 power-domains = <&rpmhpd SC7280_CX>;
1544 operating-points-v2 = <&qup_opp_table>;
1547 interconnect-names = "qup-core", "qup-config";
1550 dma-names = "tx", "rx";
1555 compatible = "qcom,geni-uart";
1558 clock-names = "se";
1559 pinctrl-names = "default";
1560 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>;
1562 power-domains = <&rpmhpd SC7280_CX>;
1563 operating-points-v2 = <&qup_opp_table>;
1566 interconnect-names = "qup-core", "qup-config";
1571 compatible = "qcom,geni-i2c";
1574 clock-names = "se";
1575 pinctrl-names = "default";
1576 pinctrl-0 = <&qup_i2c10_data_clk>;
1578 #address-cells = <1>;
1579 #size-cells = <0>;
1583 interconnect-names = "qup-core", "qup-config",
1584 "qup-memory";
1587 dma-names = "tx", "rx";
1592 compatible = "qcom,geni-spi";
1595 clock-names = "se";
1596 pinctrl-names = "default";
1597 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1599 #address-cells = <1>;
1600 #size-cells = <0>;
1601 power-domains = <&rpmhpd SC7280_CX>;
1602 operating-points-v2 = <&qup_opp_table>;
1605 interconnect-names = "qup-core", "qup-config";
1608 dma-names = "tx", "rx";
1613 compatible = "qcom,geni-uart";
1616 clock-names = "se";
1617 pinctrl-names = "default";
1618 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>;
1620 power-domains = <&rpmhpd SC7280_CX>;
1621 operating-points-v2 = <&qup_opp_table>;
1624 interconnect-names = "qup-core", "qup-config";
1629 compatible = "qcom,geni-i2c";
1632 clock-names = "se";
1633 pinctrl-names = "default";
1634 pinctrl-0 = <&qup_i2c11_data_clk>;
1636 #address-cells = <1>;
1637 #size-cells = <0>;
1641 interconnect-names = "qup-core", "qup-config",
1642 "qup-memory";
1645 dma-names = "tx", "rx";
1650 compatible = "qcom,geni-spi";
1653 clock-names = "se";
1654 pinctrl-names = "default";
1655 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1657 #address-cells = <1>;
1658 #size-cells = <0>;
1659 power-domains = <&rpmhpd SC7280_CX>;
1660 operating-points-v2 = <&qup_opp_table>;
1663 interconnect-names = "qup-core", "qup-config";
1666 dma-names = "tx", "rx";
1671 compatible = "qcom,geni-uart";
1674 clock-names = "se";
1675 pinctrl-names = "default";
1676 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>;
1678 power-domains = <&rpmhpd SC7280_CX>;
1679 operating-points-v2 = <&qup_opp_table>;
1682 interconnect-names = "qup-core", "qup-config";
1687 compatible = "qcom,geni-i2c";
1690 clock-names = "se";
1691 pinctrl-names = "default";
1692 pinctrl-0 = <&qup_i2c12_data_clk>;
1694 #address-cells = <1>;
1695 #size-cells = <0>;
1699 interconnect-names = "qup-core", "qup-config",
1700 "qup-memory";
1703 dma-names = "tx", "rx";
1708 compatible = "qcom,geni-spi";
1711 clock-names = "se";
1712 pinctrl-names = "default";
1713 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1715 #address-cells = <1>;
1716 #size-cells = <0>;
1717 power-domains = <&rpmhpd SC7280_CX>;
1718 operating-points-v2 = <&qup_opp_table>;
1721 interconnect-names = "qup-core", "qup-config";
1724 dma-names = "tx", "rx";
1729 compatible = "qcom,geni-uart";
1732 clock-names = "se";
1733 pinctrl-names = "default";
1734 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>;
1736 power-domains = <&rpmhpd SC7280_CX>;
1737 operating-points-v2 = <&qup_opp_table>;
1740 interconnect-names = "qup-core", "qup-config";
1745 compatible = "qcom,geni-i2c";
1748 clock-names = "se";
1749 pinctrl-names = "default";
1750 pinctrl-0 = <&qup_i2c13_data_clk>;
1752 #address-cells = <1>;
1753 #size-cells = <0>;
1757 interconnect-names = "qup-core", "qup-config",
1758 "qup-memory";
1761 dma-names = "tx", "rx";
1766 compatible = "qcom,geni-spi";
1769 clock-names = "se";
1770 pinctrl-names = "default";
1771 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1773 #address-cells = <1>;
1774 #size-cells = <0>;
1775 power-domains = <&rpmhpd SC7280_CX>;
1776 operating-points-v2 = <&qup_opp_table>;
1779 interconnect-names = "qup-core", "qup-config";
1782 dma-names = "tx", "rx";
1787 compatible = "qcom,geni-uart";
1790 clock-names = "se";
1791 pinctrl-names = "default";
1792 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>;
1794 power-domains = <&rpmhpd SC7280_CX>;
1795 operating-points-v2 = <&qup_opp_table>;
1798 interconnect-names = "qup-core", "qup-config";
1803 compatible = "qcom,geni-i2c";
1806 clock-names = "se";
1807 pinctrl-names = "default";
1808 pinctrl-0 = <&qup_i2c14_data_clk>;
1810 #address-cells = <1>;
1811 #size-cells = <0>;
1815 interconnect-names = "qup-core", "qup-config",
1816 "qup-memory";
1819 dma-names = "tx", "rx";
1824 compatible = "qcom,geni-spi";
1827 clock-names = "se";
1828 pinctrl-names = "default";
1829 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1831 #address-cells = <1>;
1832 #size-cells = <0>;
1833 power-domains = <&rpmhpd SC7280_CX>;
1834 operating-points-v2 = <&qup_opp_table>;
1837 interconnect-names = "qup-core", "qup-config";
1840 dma-names = "tx", "rx";
1845 compatible = "qcom,geni-uart";
1848 clock-names = "se";
1849 pinctrl-names = "default";
1850 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>;
1852 power-domains = <&rpmhpd SC7280_CX>;
1853 operating-points-v2 = <&qup_opp_table>;
1856 interconnect-names = "qup-core", "qup-config";
1861 compatible = "qcom,geni-i2c";
1864 clock-names = "se";
1865 pinctrl-names = "default";
1866 pinctrl-0 = <&qup_i2c15_data_clk>;
1868 #address-cells = <1>;
1869 #size-cells = <0>;
1873 interconnect-names = "qup-core", "qup-config",
1874 "qup-memory";
1877 dma-names = "tx", "rx";
1882 compatible = "qcom,geni-spi";
1885 clock-names = "se";
1886 pinctrl-names = "default";
1887 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1889 #address-cells = <1>;
1890 #size-cells = <0>;
1891 power-domains = <&rpmhpd SC7280_CX>;
1892 operating-points-v2 = <&qup_opp_table>;
1895 interconnect-names = "qup-core", "qup-config";
1898 dma-names = "tx", "rx";
1903 compatible = "qcom,geni-uart";
1906 clock-names = "se";
1907 pinctrl-names = "default";
1908 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>;
1910 power-domains = <&rpmhpd SC7280_CX>;
1911 operating-points-v2 = <&qup_opp_table>;
1914 interconnect-names = "qup-core", "qup-config";
1921 compatible = "qcom,sc7280-cnoc2";
1922 #interconnect-cells = <2>;
1923 qcom,bcm-voters = <&apps_bcm_voter>;
1928 compatible = "qcom,sc7280-cnoc3";
1929 #interconnect-cells = <2>;
1930 qcom,bcm-voters = <&apps_bcm_voter>;
1935 compatible = "qcom,sc7280-mc-virt";
1936 #interconnect-cells = <2>;
1937 qcom,bcm-voters = <&apps_bcm_voter>;
1942 compatible = "qcom,sc7280-system-noc";
1943 #interconnect-cells = <2>;
1944 qcom,bcm-voters = <&apps_bcm_voter>;
1948 compatible = "qcom,sc7280-aggre1-noc";
1950 #interconnect-cells = <2>;
1951 qcom,bcm-voters = <&apps_bcm_voter>;
1956 compatible = "qcom,sc7280-aggre2-noc";
1957 #interconnect-cells = <2>;
1958 qcom,bcm-voters = <&apps_bcm_voter>;
1963 compatible = "qcom,sc7280-mmss-noc";
1964 #interconnect-cells = <2>;
1965 qcom,bcm-voters = <&apps_bcm_voter>;
1969 compatible = "qcom,wcn6750-wifi";
2005 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>;
2010 compatible = "qcom,pcie-sc7280";
2017 reg-names = "parf", "dbi", "elbi", "atu", "config";
2019 linux,pci-domain = <1>;
2020 bus-range = <0x00 0xff>;
2021 num-lanes = <2>;
2023 #address-cells = <3>;
2024 #size-cells = <2>;
2030 interrupt-names = "msi";
2031 #interrupt-cells = <1>;
2032 interrupt-map-mask = <0 0 0 0x7>;
2033 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
2052 clock-names = "pipe",
2066 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2067 assigned-clock-rates = <19200000>;
2070 reset-names = "pci";
2072 power-domains = <&gcc GCC_PCIE_1_GDSC>;
2075 phy-names = "pciephy";
2077 pinctrl-names = "default";
2078 pinctrl-0 = <&pcie1_clkreq_n>;
2082 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2089 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
2091 #address-cells = <2>;
2092 #size-cells = <2>;
2098 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2101 reset-names = "phy";
2103 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
2104 assigned-clock-rates = <100000000>;
2116 clock-names = "pipe0";
2118 #phy-cells = <0>;
2119 #clock-cells = <0>;
2120 clock-output-names = "pcie_1_pipe_clk";
2125 compatible = "qcom,sc7280-ipa";
2132 reg-names = "ipa-reg",
2133 "ipa-shared",
2136 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>,
2140 interrupt-names = "ipa",
2142 "ipa-clock-query",
2143 "ipa-setup-ready";
2146 clock-names = "core";
2150 interconnect-names = "memory",
2155 qcom,smem-states = <&ipa_smp2p_out 0>,
2157 qcom,smem-state-names = "ipa-clock-enabled-valid",
2158 "ipa-clock-enabled";
2164 compatible = "qcom,tcsr-mutex";
2166 #hwlock-cells = <1>;
2170 compatible = "qcom,sc7280-tcsr", "syscon";
2175 compatible = "qcom,sc7280-tcsr", "syscon";
2180 compatible = "qcom,sc7280-lpasscc";
2183 reg-names = "qdsp6ss", "top_cc";
2185 clock-names = "iface";
2186 #clock-cells = <1>;
2190 compatible = "qcom,sc7280-lpass-rx-macro";
2193 pinctrl-names = "default";
2194 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>;
2199 clock-names = "mclk", "npl", "fsgen";
2201 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2203 power-domain-names = "macro", "dcodec";
2205 #clock-cells = <0>;
2206 #sound-dai-cells = <1>;
2212 compatible = "qcom,soundwire-v1.6.0";
2217 clock-names = "iface";
2219 qcom,din-ports = <0>;
2220 qcom,dout-ports = <5>;
2223 reset-names = "swr_audio_cgcr";
2225 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2226 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>;
2227 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>;
2228 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2229 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2230 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2231 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2232 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2233 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2235 #sound-dai-cells = <1>;
2236 #address-cells = <2>;
2237 #size-cells = <0>;
2243 compatible = "qcom,sc7280-lpass-tx-macro";
2246 pinctrl-names = "default";
2247 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>;
2252 clock-names = "mclk", "npl", "fsgen";
2254 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2256 power-domain-names = "macro", "dcodec";
2258 #clock-cells = <0>;
2259 #sound-dai-cells = <1>;
2265 compatible = "qcom,soundwire-v1.6.0";
2268 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
2271 clock-names = "iface";
2273 qcom,din-ports = <3>;
2274 qcom,dout-ports = <0>;
2277 reset-names = "swr_audio_cgcr";
2279 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>;
2280 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>;
2281 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>;
2282 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>;
2283 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>;
2284 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>;
2285 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>;
2286 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>;
2287 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>;
2288 qcom,port-offset = <1>;
2290 #sound-dai-cells = <1>;
2291 #address-cells = <2>;
2292 #size-cells = <0>;
2297 lpass_audiocc: clock-controller@3300000 {
2298 compatible = "qcom,sc7280-lpassaudiocc";
2303 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src";
2304 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
2305 #clock-cells = <1>;
2306 #power-domain-cells = <1>;
2307 #reset-cells = <1>;
2311 compatible = "qcom,sc7280-lpass-va-macro";
2314 pinctrl-names = "default";
2315 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>;
2318 clock-names = "mclk";
2320 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2322 power-domain-names = "macro", "dcodec";
2324 #clock-cells = <0>;
2325 #sound-dai-cells = <1>;
2330 lpass_aon: clock-controller@3380000 {
2331 compatible = "qcom,sc7280-lpassaoncc";
2336 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface";
2337 #clock-cells = <1>;
2338 #power-domain-cells = <1>;
2341 lpass_core: clock-controller@3900000 {
2342 compatible = "qcom,sc7280-lpasscorecc";
2345 clock-names = "bi_tcxo";
2346 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>;
2347 #clock-cells = <1>;
2348 #power-domain-cells = <1>;
2352 compatible = "qcom,sc7280-lpass-cpu";
2360 reg-names = "lpass-hdmiif",
2361 "lpass-lpaif",
2362 "lpass-rxtx-cdc-dma-lpm",
2363 "lpass-rxtx-lpaif",
2364 "lpass-va-lpaif",
2365 "lpass-va-cdc-dma-lpm";
2371 power-domains = <&rpmhpd SC7280_LCX>;
2372 power-domain-names = "lcx";
2373 required-opps = <&rpmhpd_opp_nom>;
2385 clock-names = "aon_cc_audio_hm_h",
2396 #sound-dai-cells = <1>;
2397 #address-cells = <1>;
2398 #size-cells = <0>;
2404 interrupt-names = "lpass-irq-lpaif",
2405 "lpass-irq-hdmi",
2406 "lpass-irq-vaif",
2407 "lpass-irq-rxtxif";
2412 lpass_hm: clock-controller@3c00000 {
2413 compatible = "qcom,sc7280-lpasshm";
2416 clock-names = "bi_tcxo";
2417 #clock-cells = <1>;
2418 #power-domain-cells = <1>;
2423 compatible = "qcom,sc7280-lpass-ag-noc";
2424 #interconnect-cells = <2>;
2425 qcom,bcm-voters = <&apps_bcm_voter>;
2429 compatible = "qcom,sc7280-lpass-lpi-pinctrl";
2432 qcom,adsp-bypass-mode;
2433 gpio-controller;
2434 #gpio-cells = <2>;
2435 gpio-ranges = <&lpass_tlmm 0 0 15>;
2437 #clock-cells = <1>;
2439 lpass_dmic01_clk: dmic01-clk {
2444 lpass_dmic01_clk_sleep: dmic01-clk-sleep {
2449 lpass_dmic01_data: dmic01-data {
2454 lpass_dmic01_data_sleep: dmic01-data-sleep {
2459 lpass_dmic23_clk: dmic23-clk {
2464 lpass_dmic23_clk_sleep: dmic23-clk-sleep {
2469 lpass_dmic23_data: dmic23-data {
2474 lpass_dmic23_data_sleep: dmic23-data-sleep {
2479 lpass_rx_swr_clk: rx-swr-clk {
2484 lpass_rx_swr_clk_sleep: rx-swr-clk-sleep {
2489 lpass_rx_swr_data: rx-swr-data {
2494 lpass_rx_swr_data_sleep: rx-swr-data-sleep {
2499 lpass_tx_swr_clk: tx-swr-clk {
2504 lpass_tx_swr_clk_sleep: tx-swr-clk-sleep {
2509 lpass_tx_swr_data: tx-swr-data {
2514 lpass_tx_swr_data_sleep: tx-swr-data-sleep {
2521 compatible = "qcom,adreno-635.0", "qcom,adreno";
2525 reg-names = "kgsl_3d0_reg_memory",
2530 operating-points-v2 = <&gpu_opp_table>;
2533 interconnect-names = "gfx-mem";
2534 #cooling-cells = <2>;
2536 nvmem-cells = <&gpu_speed_bin>;
2537 nvmem-cell-names = "speed_bin";
2539 gpu_opp_table: opp-table {
2540 compatible = "operating-points-v2";
2542 opp-315000000 {
2543 opp-hz = /bits/ 64 <315000000>;
2544 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2545 opp-peak-kBps = <1804000>;
2546 opp-supported-hw = <0x03>;
2549 opp-450000000 {
2550 opp-hz = /bits/ 64 <450000000>;
2551 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2552 opp-peak-kBps = <4068000>;
2553 opp-supported-hw = <0x03>;
2557 opp-550000000-0 {
2558 opp-hz = /bits/ 64 <550000000>;
2559 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2560 opp-peak-kBps = <8368000>;
2561 opp-supported-hw = <0x01>;
2564 opp-550000000-1 {
2565 opp-hz = /bits/ 64 <550000000>;
2566 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2567 opp-peak-kBps = <6832000>;
2568 opp-supported-hw = <0x02>;
2571 opp-608000000 {
2572 opp-hz = /bits/ 64 <608000000>;
2573 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2574 opp-peak-kBps = <8368000>;
2575 opp-supported-hw = <0x02>;
2578 opp-700000000 {
2579 opp-hz = /bits/ 64 <700000000>;
2580 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2581 opp-peak-kBps = <8532000>;
2582 opp-supported-hw = <0x02>;
2585 opp-812000000 {
2586 opp-hz = /bits/ 64 <812000000>;
2587 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2588 opp-peak-kBps = <8532000>;
2589 opp-supported-hw = <0x02>;
2592 opp-840000000 {
2593 opp-hz = /bits/ 64 <840000000>;
2594 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2595 opp-peak-kBps = <8532000>;
2596 opp-supported-hw = <0x02>;
2599 opp-900000000 {
2600 opp-hz = /bits/ 64 <900000000>;
2601 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2602 opp-peak-kBps = <8532000>;
2603 opp-supported-hw = <0x02>;
2609 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu";
2613 reg-names = "gmu", "rscc", "gmu_pdc";
2616 interrupt-names = "hfi", "gmu";
2624 clock-names = "gmu",
2631 power-domains = <&gpucc GPU_CC_CX_GDSC>,
2633 power-domain-names = "cx",
2636 operating-points-v2 = <&gmu_opp_table>;
2638 gmu_opp_table: opp-table {
2639 compatible = "operating-points-v2";
2641 opp-200000000 {
2642 opp-hz = /bits/ 64 <200000000>;
2643 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2648 gpucc: clock-controller@3d90000 {
2649 compatible = "qcom,sc7280-gpucc";
2654 clock-names = "bi_tcxo",
2657 #clock-cells = <1>;
2658 #reset-cells = <1>;
2659 #power-domain-cells = <1>;
2663 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500";
2665 #iommu-cells = <2>;
2666 #global-interrupts = <2>;
2687 clock-names = "gcc_gpu_memnoc_gfx_clk",
2695 power-domains = <&gpucc GPU_CC_CX_GDSC>;
2699 compatible = "qcom,sc7280-mpss-pas";
2701 reg-names = "qdsp6", "rmb";
2703 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2709 interrupt-names = "wdog", "fatal", "ready", "handover",
2710 "stop-ack", "shutdown-ack";
2717 clock-names = "iface", "offline", "snoc_axi", "pka", "xo";
2719 power-domains = <&rpmhpd SC7280_CX>,
2721 power-domain-names = "cx", "mss";
2723 memory-region = <&mpss_mem>;
2727 qcom,smem-states = <&modem_smp2p_out 0>;
2728 qcom,smem-state-names = "stop";
2732 reset-names = "mss_restart", "pdc_reset";
2734 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x8000 0x13000>;
2735 qcom,ext-regs = <&tcsr_2 0x10000 0x10004 &tcsr_1 0x6004 0x6008>;
2736 qcom,qaccept-regs = <&tcsr_1 0x3030 0x3040 0x3020>;
2740 glink-edge {
2741 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2747 qcom,remote-pid = <1>;
2752 compatible = "arm,coresight-stm", "arm,primecell";
2755 reg-names = "stm-base", "stm-stimulus-base";
2758 clock-names = "apb_pclk";
2760 out-ports {
2763 remote-endpoint = <&funnel0_in7>;
2770 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2774 clock-names = "apb_pclk";
2776 out-ports {
2779 remote-endpoint = <&merge_funnel_in0>;
2784 in-ports {
2785 #address-cells = <1>;
2786 #size-cells = <0>;
2791 remote-endpoint = <&stm_out>;
2798 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2802 clock-names = "apb_pclk";
2804 out-ports {
2807 remote-endpoint = <&merge_funnel_in1>;
2812 in-ports {
2813 #address-cells = <1>;
2814 #size-cells = <0>;
2819 remote-endpoint = <&apss_merge_funnel_out>;
2826 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2830 clock-names = "apb_pclk";
2832 out-ports {
2835 remote-endpoint = <&swao_funnel_in>;
2840 in-ports {
2841 #address-cells = <1>;
2842 #size-cells = <0>;
2847 remote-endpoint = <&funnel0_out>;
2854 remote-endpoint = <&funnel1_out>;
2861 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2865 clock-names = "apb_pclk";
2867 out-ports {
2870 remote-endpoint = <&etr_in>;
2875 in-ports {
2878 remote-endpoint = <&swao_replicator_out>;
2885 compatible = "arm,coresight-tmc", "arm,primecell";
2890 clock-names = "apb_pclk";
2891 arm,scatter-gather;
2893 in-ports {
2896 remote-endpoint = <&replicator_out>;
2903 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2907 clock-names = "apb_pclk";
2909 out-ports {
2912 remote-endpoint = <&etf_in>;
2917 in-ports {
2918 #address-cells = <1>;
2919 #size-cells = <0>;
2924 remote-endpoint = <&merge_funnel_out>;
2931 compatible = "arm,coresight-tmc", "arm,primecell";
2935 clock-names = "apb_pclk";
2937 out-ports {
2940 remote-endpoint = <&swao_replicator_in>;
2945 in-ports {
2948 remote-endpoint = <&swao_funnel_out>;
2955 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2959 clock-names = "apb_pclk";
2960 qcom,replicator-loses-context;
2962 out-ports {
2965 remote-endpoint = <&replicator_in>;
2970 in-ports {
2973 remote-endpoint = <&etf_out>;
2980 compatible = "arm,coresight-etm4x", "arm,primecell";
2986 clock-names = "apb_pclk";
2987 arm,coresight-loses-context-with-cpu;
2988 qcom,skip-power-up;
2990 out-ports {
2993 remote-endpoint = <&apss_funnel_in0>;
3000 compatible = "arm,coresight-etm4x", "arm,primecell";
3006 clock-names = "apb_pclk";
3007 arm,coresight-loses-context-with-cpu;
3008 qcom,skip-power-up;
3010 out-ports {
3013 remote-endpoint = <&apss_funnel_in1>;
3020 compatible = "arm,coresight-etm4x", "arm,primecell";
3026 clock-names = "apb_pclk";
3027 arm,coresight-loses-context-with-cpu;
3028 qcom,skip-power-up;
3030 out-ports {
3033 remote-endpoint = <&apss_funnel_in2>;
3040 compatible = "arm,coresight-etm4x", "arm,primecell";
3046 clock-names = "apb_pclk";
3047 arm,coresight-loses-context-with-cpu;
3048 qcom,skip-power-up;
3050 out-ports {
3053 remote-endpoint = <&apss_funnel_in3>;
3060 compatible = "arm,coresight-etm4x", "arm,primecell";
3066 clock-names = "apb_pclk";
3067 arm,coresight-loses-context-with-cpu;
3068 qcom,skip-power-up;
3070 out-ports {
3073 remote-endpoint = <&apss_funnel_in4>;
3080 compatible = "arm,coresight-etm4x", "arm,primecell";
3086 clock-names = "apb_pclk";
3087 arm,coresight-loses-context-with-cpu;
3088 qcom,skip-power-up;
3090 out-ports {
3093 remote-endpoint = <&apss_funnel_in5>;
3100 compatible = "arm,coresight-etm4x", "arm,primecell";
3106 clock-names = "apb_pclk";
3107 arm,coresight-loses-context-with-cpu;
3108 qcom,skip-power-up;
3110 out-ports {
3113 remote-endpoint = <&apss_funnel_in6>;
3120 compatible = "arm,coresight-etm4x", "arm,primecell";
3126 clock-names = "apb_pclk";
3127 arm,coresight-loses-context-with-cpu;
3128 qcom,skip-power-up;
3130 out-ports {
3133 remote-endpoint = <&apss_funnel_in7>;
3140 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3144 clock-names = "apb_pclk";
3146 out-ports {
3149 remote-endpoint = <&apss_merge_funnel_in>;
3154 in-ports {
3155 #address-cells = <1>;
3156 #size-cells = <0>;
3161 remote-endpoint = <&etm0_out>;
3168 remote-endpoint = <&etm1_out>;
3175 remote-endpoint = <&etm2_out>;
3182 remote-endpoint = <&etm3_out>;
3189 remote-endpoint = <&etm4_out>;
3196 remote-endpoint = <&etm5_out>;
3203 remote-endpoint = <&etm6_out>;
3210 remote-endpoint = <&etm7_out>;
3217 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3221 clock-names = "apb_pclk";
3223 out-ports {
3226 remote-endpoint = <&funnel1_in4>;
3231 in-ports {
3234 remote-endpoint = <&apss_funnel_out>;
3241 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
3242 pinctrl-names = "default", "sleep";
3243 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>;
3244 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>;
3252 interrupt-names = "hc_irq", "pwr_irq";
3257 clock-names = "iface", "core", "xo";
3260 interconnect-names = "sdhc-ddr","cpu-sdhc";
3261 power-domains = <&rpmhpd SC7280_CX>;
3262 operating-points-v2 = <&sdhc2_opp_table>;
3264 bus-width = <4>;
3266 qcom,dll-config = <0x0007642c>;
3270 sdhc2_opp_table: opp-table {
3271 compatible = "operating-points-v2";
3273 opp-100000000 {
3274 opp-hz = /bits/ 64 <100000000>;
3275 required-opps = <&rpmhpd_opp_low_svs>;
3276 opp-peak-kBps = <1800000 400000>;
3277 opp-avg-kBps = <100000 0>;
3280 opp-202000000 {
3281 opp-hz = /bits/ 64 <202000000>;
3282 required-opps = <&rpmhpd_opp_nom>;
3283 opp-peak-kBps = <5400000 1600000>;
3284 opp-avg-kBps = <200000 0>;
3291 compatible = "qcom,sc7280-usb-hs-phy",
3292 "qcom,usb-snps-hs-7nm-phy";
3295 #phy-cells = <0>;
3298 clock-names = "ref";
3304 compatible = "qcom,sc7280-usb-hs-phy",
3305 "qcom,usb-snps-hs-7nm-phy";
3308 #phy-cells = <0>;
3311 clock-names = "ref";
3316 usb_1_qmpphy: phy-wrapper@88e9000 {
3317 compatible = "qcom,sc7280-qmp-usb3-dp-phy",
3318 "qcom,sm8250-qmp-usb3-dp-phy";
3323 #address-cells = <2>;
3324 #size-cells = <2>;
3330 clock-names = "aux", "ref_clk_src", "com_aux";
3334 reset-names = "phy", "common";
3336 usb_1_ssphy: usb3-phy@88e9200 {
3343 #clock-cells = <0>;
3344 #phy-cells = <0>;
3346 clock-names = "pipe0";
3347 clock-output-names = "usb3_phy_pipe_clk_src";
3350 dp_phy: dp-phy@88ea200 {
3356 #phy-cells = <0>;
3357 #clock-cells = <1>;
3362 compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
3365 #address-cells = <2>;
3366 #size-cells = <2>;
3368 dma-ranges;
3375 clock-names = "cfg_noc",
3381 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3383 assigned-clock-rates = <19200000>, <200000000>;
3385 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
3388 interrupt-names = "hs_phy_irq",
3392 power-domains = <&gcc GCC_USB30_SEC_GDSC>;
3393 required-opps = <&rpmhpd_opp_nom>;
3399 interconnect-names = "usb-ddr", "apps-usb";
3409 phy-names = "usb2-phy";
3410 maximum-speed = "high-speed";
3411 usb-role-switch;
3414 remote-endpoint = <&eud_ep>;
3421 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1";
3423 #address-cells = <1>;
3424 #size-cells = <0>;
3428 clock-names = "iface", "core";
3431 interconnect-names = "qspi-config";
3432 power-domains = <&rpmhpd SC7280_CX>;
3433 operating-points-v2 = <&qspi_opp_table>;
3438 compatible = "qcom,sc7280-wpss-pil";
3441 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>,
3447 interrupt-names = "wdog", "fatal", "ready", "handover",
3448 "stop-ack", "shutdown-ack";
3454 clock-names = "ahb_bdg", "ahb",
3457 power-domains = <&rpmhpd SC7280_CX>,
3459 power-domain-names = "cx", "mx";
3461 memory-region = <&wpss_mem>;
3465 qcom,smem-states = <&wpss_smp2p_out 0>;
3466 qcom,smem-state-names = "stop";
3470 reset-names = "restart", "pdc_sync";
3472 qcom,halt-regs = <&tcsr_1 0x17000>;
3476 glink-edge {
3477 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
3484 qcom,remote-pid = <13>;
3489 compatible = "qcom,sc7280-llcc-bwmon";
3496 operating-points-v2 = <&llcc_bwmon_opp_table>;
3498 llcc_bwmon_opp_table: opp-table {
3499 compatible = "operating-points-v2";
3501 opp-0 {
3502 opp-peak-kBps = <800000>;
3504 opp-1 {
3505 opp-peak-kBps = <1804000>;
3507 opp-2 {
3508 opp-peak-kBps = <2188000>;
3510 opp-3 {
3511 opp-peak-kBps = <3072000>;
3513 opp-4 {
3514 opp-peak-kBps = <4068000>;
3516 opp-5 {
3517 opp-peak-kBps = <6220000>;
3519 opp-6 {
3520 opp-peak-kBps = <6832000>;
3522 opp-7 {
3523 opp-peak-kBps = <8532000>;
3529 compatible = "qcom,sc7280-cpu-bwmon", "qcom,msm8998-bwmon";
3535 operating-points-v2 = <&cpu_bwmon_opp_table>;
3537 cpu_bwmon_opp_table: opp-table {
3538 compatible = "operating-points-v2";
3540 opp-0 {
3541 opp-peak-kBps = <2400000>;
3543 opp-1 {
3544 opp-peak-kBps = <4800000>;
3546 opp-2 {
3547 opp-peak-kBps = <7456000>;
3549 opp-3 {
3550 opp-peak-kBps = <9600000>;
3552 opp-4 {
3553 opp-peak-kBps = <12896000>;
3555 opp-5 {
3556 opp-peak-kBps = <14928000>;
3558 opp-6 {
3559 opp-peak-kBps = <17056000>;
3566 compatible = "qcom,sc7280-dc-noc";
3567 #interconnect-cells = <2>;
3568 qcom,bcm-voters = <&apps_bcm_voter>;
3573 compatible = "qcom,sc7280-gem-noc";
3574 #interconnect-cells = <2>;
3575 qcom,bcm-voters = <&apps_bcm_voter>;
3578 system-cache-controller@9200000 {
3579 compatible = "qcom,sc7280-llcc";
3581 reg-names = "llcc_base", "llcc_broadcast_base";
3586 compatible = "qcom,sc7280-eud","qcom,eud";
3589 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>;
3593 remote-endpoint = <&usb2_role_switch>;
3598 remote-endpoint = <&con_eud>;
3605 compatible = "usb-c-connector";
3609 remote-endpoint = <&eud_con>;
3617 compatible = "qcom,sc7280-nsp-noc";
3618 #interconnect-cells = <2>;
3619 qcom,bcm-voters = <&apps_bcm_voter>;
3623 compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
3626 #address-cells = <2>;
3627 #size-cells = <2>;
3629 dma-ranges;
3636 clock-names = "cfg_noc",
3642 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3644 assigned-clock-rates = <19200000>, <200000000>;
3646 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3650 interrupt-names = "hs_phy_irq",
3655 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
3656 required-opps = <&rpmhpd_opp_nom>;
3662 interconnect-names = "usb-ddr", "apps-usb";
3664 wakeup-source;
3674 phy-names = "usb2-phy", "usb3-phy";
3675 maximum-speed = "super-speed";
3679 venus: video-codec@aa00000 {
3680 compatible = "qcom,sc7280-venus";
3689 clock-names = "core", "bus", "iface",
3692 power-domains = <&videocc MVSC_GDSC>,
3695 power-domain-names = "venus", "vcodec0", "cx";
3696 operating-points-v2 = <&venus_opp_table>;
3700 interconnect-names = "cpu-cfg", "video-mem";
3704 memory-region = <&video_mem>;
3706 video-decoder {
3707 compatible = "venus-decoder";
3710 video-encoder {
3711 compatible = "venus-encoder";
3714 video-firmware {
3718 venus_opp_table: opp-table {
3719 compatible = "operating-points-v2";
3721 opp-133330000 {
3722 opp-hz = /bits/ 64 <133330000>;
3723 required-opps = <&rpmhpd_opp_low_svs>;
3726 opp-240000000 {
3727 opp-hz = /bits/ 64 <240000000>;
3728 required-opps = <&rpmhpd_opp_svs>;
3731 opp-335000000 {
3732 opp-hz = /bits/ 64 <335000000>;
3733 required-opps = <&rpmhpd_opp_svs_l1>;
3736 opp-424000000 {
3737 opp-hz = /bits/ 64 <424000000>;
3738 required-opps = <&rpmhpd_opp_nom>;
3741 opp-460000048 {
3742 opp-hz = /bits/ 64 <460000048>;
3743 required-opps = <&rpmhpd_opp_turbo>;
3749 videocc: clock-controller@aaf0000 {
3750 compatible = "qcom,sc7280-videocc";
3754 clock-names = "bi_tcxo", "bi_tcxo_ao";
3755 #clock-cells = <1>;
3756 #reset-cells = <1>;
3757 #power-domain-cells = <1>;
3760 camcc: clock-controller@ad00000 {
3761 compatible = "qcom,sc7280-camcc";
3766 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
3767 #clock-cells = <1>;
3768 #reset-cells = <1>;
3769 #power-domain-cells = <1>;
3772 dispcc: clock-controller@af00000 {
3773 compatible = "qcom,sc7280-dispcc";
3783 clock-names = "bi_tcxo",
3791 #clock-cells = <1>;
3792 #reset-cells = <1>;
3793 #power-domain-cells = <1>;
3796 mdss: display-subsystem@ae00000 {
3797 compatible = "qcom,sc7280-mdss";
3799 reg-names = "mdss";
3801 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
3806 clock-names = "iface",
3811 interrupt-controller;
3812 #interrupt-cells = <1>;
3815 interconnect-names = "mdp0-mem";
3819 #address-cells = <2>;
3820 #size-cells = <2>;
3825 mdss_mdp: display-controller@ae01000 {
3826 compatible = "qcom,sc7280-dpu";
3829 reg-names = "mdp", "vbif";
3837 clock-names = "bus",
3843 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
3845 assigned-clock-rates = <19200000>,
3847 operating-points-v2 = <&mdp_opp_table>;
3848 power-domains = <&rpmhpd SC7280_CX>;
3850 interrupt-parent = <&mdss>;
3856 #address-cells = <1>;
3857 #size-cells = <0>;
3862 remote-endpoint = <&dsi0_in>;
3869 remote-endpoint = <&edp_in>;
3876 remote-endpoint = <&dp_in>;
3881 mdp_opp_table: opp-table {
3882 compatible = "operating-points-v2";
3884 opp-200000000 {
3885 opp-hz = /bits/ 64 <200000000>;
3886 required-opps = <&rpmhpd_opp_low_svs>;
3889 opp-300000000 {
3890 opp-hz = /bits/ 64 <300000000>;
3891 required-opps = <&rpmhpd_opp_svs>;
3894 opp-380000000 {
3895 opp-hz = /bits/ 64 <380000000>;
3896 required-opps = <&rpmhpd_opp_svs_l1>;
3899 opp-506666667 {
3900 opp-hz = /bits/ 64 <506666667>;
3901 required-opps = <&rpmhpd_opp_nom>;
3907 compatible = "qcom,mdss-dsi-ctrl";
3909 reg-names = "dsi_ctrl";
3911 interrupt-parent = <&mdss>;
3920 clock-names = "byte",
3927 operating-points-v2 = <&dsi_opp_table>;
3928 power-domains = <&rpmhpd SC7280_CX>;
3931 phy-names = "dsi";
3933 #address-cells = <1>;
3934 #size-cells = <0>;
3939 #address-cells = <1>;
3940 #size-cells = <0>;
3945 remote-endpoint = <&dpu_intf1_out>;
3956 dsi_opp_table: opp-table {
3957 compatible = "operating-points-v2";
3959 opp-187500000 {
3960 opp-hz = /bits/ 64 <187500000>;
3961 required-opps = <&rpmhpd_opp_low_svs>;
3964 opp-300000000 {
3965 opp-hz = /bits/ 64 <300000000>;
3966 required-opps = <&rpmhpd_opp_svs>;
3969 opp-358000000 {
3970 opp-hz = /bits/ 64 <358000000>;
3971 required-opps = <&rpmhpd_opp_svs_l1>;
3977 compatible = "qcom,sc7280-dsi-phy-7nm";
3981 reg-names = "dsi_phy",
3985 #clock-cells = <1>;
3986 #phy-cells = <0>;
3990 clock-names = "iface", "ref";
3996 compatible = "qcom,sc7280-edp";
3997 pinctrl-names = "default";
3998 pinctrl-0 = <&edp_hot_plug_det>;
4005 interrupt-parent = <&mdss>;
4013 clock-names = "core_iface",
4018 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
4020 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
4023 phy-names = "dp";
4025 operating-points-v2 = <&edp_opp_table>;
4026 power-domains = <&rpmhpd SC7280_CX>;
4031 #address-cells = <1>;
4032 #size-cells = <0>;
4037 remote-endpoint = <&dpu_intf5_out>;
4047 edp_opp_table: opp-table {
4048 compatible = "operating-points-v2";
4050 opp-160000000 {
4051 opp-hz = /bits/ 64 <160000000>;
4052 required-opps = <&rpmhpd_opp_low_svs>;
4055 opp-270000000 {
4056 opp-hz = /bits/ 64 <270000000>;
4057 required-opps = <&rpmhpd_opp_svs>;
4060 opp-540000000 {
4061 opp-hz = /bits/ 64 <540000000>;
4062 required-opps = <&rpmhpd_opp_nom>;
4065 opp-810000000 {
4066 opp-hz = /bits/ 64 <810000000>;
4067 required-opps = <&rpmhpd_opp_nom>;
4073 compatible = "qcom,sc7280-edp-phy";
4082 clock-names = "aux",
4085 #clock-cells = <1>;
4086 #phy-cells = <0>;
4091 mdss_dp: displayport-controller@ae90000 {
4092 compatible = "qcom,sc7280-dp";
4100 interrupt-parent = <&mdss>;
4108 clock-names = "core_iface",
4113 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
4115 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
4117 phy-names = "dp";
4119 operating-points-v2 = <&dp_opp_table>;
4120 power-domains = <&rpmhpd SC7280_CX>;
4122 #sound-dai-cells = <0>;
4127 #address-cells = <1>;
4128 #size-cells = <0>;
4133 remote-endpoint = <&dpu_intf0_out>;
4143 dp_opp_table: opp-table {
4144 compatible = "operating-points-v2";
4146 opp-160000000 {
4147 opp-hz = /bits/ 64 <160000000>;
4148 required-opps = <&rpmhpd_opp_low_svs>;
4151 opp-270000000 {
4152 opp-hz = /bits/ 64 <270000000>;
4153 required-opps = <&rpmhpd_opp_svs>;
4156 opp-540000000 {
4157 opp-hz = /bits/ 64 <540000000>;
4158 required-opps = <&rpmhpd_opp_svs_l1>;
4161 opp-810000000 {
4162 opp-hz = /bits/ 64 <810000000>;
4163 required-opps = <&rpmhpd_opp_nom>;
4169 pdc: interrupt-controller@b220000 {
4170 compatible = "qcom,sc7280-pdc", "qcom,pdc";
4172 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
4177 #interrupt-cells = <2>;
4178 interrupt-parent = <&intc>;
4179 interrupt-controller;
4182 pdc_reset: reset-controller@b5e0000 {
4183 compatible = "qcom,sc7280-pdc-global";
4185 #reset-cells = <1>;
4188 tsens0: thermal-sensor@c263000 {
4189 compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
4195 interrupt-names = "uplow","critical";
4196 #thermal-sensor-cells = <1>;
4199 tsens1: thermal-sensor@c265000 {
4200 compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
4206 interrupt-names = "uplow","critical";
4207 #thermal-sensor-cells = <1>;
4210 aoss_reset: reset-controller@c2a0000 {
4211 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc";
4213 #reset-cells = <1>;
4216 aoss_qmp: power-controller@c300000 {
4217 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp";
4219 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
4225 #clock-cells = <0>;
4229 compatible = "qcom,rpmh-stats";
4234 compatible = "qcom,spmi-pmic-arb";
4240 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4241 interrupt-names = "periph_irq";
4242 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4245 #address-cells = <1>;
4246 #size-cells = <1>;
4247 interrupt-controller;
4248 #interrupt-cells = <4>;
4252 compatible = "qcom,sc7280-pinctrl";
4255 gpio-controller;
4256 #gpio-cells = <2>;
4257 interrupt-controller;
4258 #interrupt-cells = <2>;
4259 gpio-ranges = <&tlmm 0 0 175>;
4260 wakeup-parent = <&pdc>;
4262 dp_hot_plug_det: dp-hot-plug-det-pins {
4267 edp_hot_plug_det: edp-hot-plug-det-pins {
4272 mi2s0_data0: mi2s0-data0-pins {
4277 mi2s0_data1: mi2s0-data1-pins {
4282 mi2s0_mclk: mi2s0-mclk-pins {
4287 mi2s0_sclk: mi2s0-sclk-pins {
4292 mi2s0_ws: mi2s0-ws-pins {
4297 mi2s1_data0: mi2s1-data0-pins {
4302 mi2s1_sclk: mi2s1-sclk-pins {
4307 mi2s1_ws: mi2s1-ws-pins {
4312 pcie1_clkreq_n: pcie1-clkreq-n-pins {
4317 qspi_clk: qspi-clk-pins {
4322 qspi_cs0: qspi-cs0-pins {
4327 qspi_cs1: qspi-cs1-pins {
4332 qspi_data01: qspi-data01-pins {
4337 qspi_data12: qspi-data12-pins {
4342 qup_i2c0_data_clk: qup-i2c0-data-clk-pins {
4347 qup_i2c1_data_clk: qup-i2c1-data-clk-pins {
4352 qup_i2c2_data_clk: qup-i2c2-data-clk-pins {
4357 qup_i2c3_data_clk: qup-i2c3-data-clk-pins {
4362 qup_i2c4_data_clk: qup-i2c4-data-clk-pins {
4367 qup_i2c5_data_clk: qup-i2c5-data-clk-pins {
4372 qup_i2c6_data_clk: qup-i2c6-data-clk-pins {
4377 qup_i2c7_data_clk: qup-i2c7-data-clk-pins {
4382 qup_i2c8_data_clk: qup-i2c8-data-clk-pins {
4387 qup_i2c9_data_clk: qup-i2c9-data-clk-pins {
4392 qup_i2c10_data_clk: qup-i2c10-data-clk-pins {
4397 qup_i2c11_data_clk: qup-i2c11-data-clk-pins {
4402 qup_i2c12_data_clk: qup-i2c12-data-clk-pins {
4407 qup_i2c13_data_clk: qup-i2c13-data-clk-pins {
4412 qup_i2c14_data_clk: qup-i2c14-data-clk-pins {
4417 qup_i2c15_data_clk: qup-i2c15-data-clk-pins {
4422 qup_spi0_data_clk: qup-spi0-data-clk-pins {
4427 qup_spi0_cs: qup-spi0-cs-pins {
4432 qup_spi0_cs_gpio: qup-spi0-cs-gpio-pins {
4437 qup_spi1_data_clk: qup-spi1-data-clk-pins {
4442 qup_spi1_cs: qup-spi1-cs-pins {
4447 qup_spi1_cs_gpio: qup-spi1-cs-gpio-pins {
4452 qup_spi2_data_clk: qup-spi2-data-clk-pins {
4457 qup_spi2_cs: qup-spi2-cs-pins {
4462 qup_spi2_cs_gpio: qup-spi2-cs-gpio-pins {
4467 qup_spi3_data_clk: qup-spi3-data-clk-pins {
4472 qup_spi3_cs: qup-spi3-cs-pins {
4477 qup_spi3_cs_gpio: qup-spi3-cs-gpio-pins {
4482 qup_spi4_data_clk: qup-spi4-data-clk-pins {
4487 qup_spi4_cs: qup-spi4-cs-pins {
4492 qup_spi4_cs_gpio: qup-spi4-cs-gpio-pins {
4497 qup_spi5_data_clk: qup-spi5-data-clk-pins {
4502 qup_spi5_cs: qup-spi5-cs-pins {
4507 qup_spi5_cs_gpio: qup-spi5-cs-gpio-pins {
4512 qup_spi6_data_clk: qup-spi6-data-clk-pins {
4517 qup_spi6_cs: qup-spi6-cs-pins {
4522 qup_spi6_cs_gpio: qup-spi6-cs-gpio-pins {
4527 qup_spi7_data_clk: qup-spi7-data-clk-pins {
4532 qup_spi7_cs: qup-spi7-cs-pins {
4537 qup_spi7_cs_gpio: qup-spi7-cs-gpio-pins {
4542 qup_spi8_data_clk: qup-spi8-data-clk-pins {
4547 qup_spi8_cs: qup-spi8-cs-pins {
4552 qup_spi8_cs_gpio: qup-spi8-cs-gpio-pins {
4557 qup_spi9_data_clk: qup-spi9-data-clk-pins {
4562 qup_spi9_cs: qup-spi9-cs-pins {
4567 qup_spi9_cs_gpio: qup-spi9-cs-gpio-pins {
4572 qup_spi10_data_clk: qup-spi10-data-clk-pins {
4577 qup_spi10_cs: qup-spi10-cs-pins {
4582 qup_spi10_cs_gpio: qup-spi10-cs-gpio-pins {
4587 qup_spi11_data_clk: qup-spi11-data-clk-pins {
4592 qup_spi11_cs: qup-spi11-cs-pins {
4597 qup_spi11_cs_gpio: qup-spi11-cs-gpio-pins {
4602 qup_spi12_data_clk: qup-spi12-data-clk-pins {
4607 qup_spi12_cs: qup-spi12-cs-pins {
4612 qup_spi12_cs_gpio: qup-spi12-cs-gpio-pins {
4617 qup_spi13_data_clk: qup-spi13-data-clk-pins {
4622 qup_spi13_cs: qup-spi13-cs-pins {
4627 qup_spi13_cs_gpio: qup-spi13-cs-gpio-pins {
4632 qup_spi14_data_clk: qup-spi14-data-clk-pins {
4637 qup_spi14_cs: qup-spi14-cs-pins {
4642 qup_spi14_cs_gpio: qup-spi14-cs-gpio-pins {
4647 qup_spi15_data_clk: qup-spi15-data-clk-pins {
4652 qup_spi15_cs: qup-spi15-cs-pins {
4657 qup_spi15_cs_gpio: qup-spi15-cs-gpio-pins {
4662 qup_uart0_cts: qup-uart0-cts-pins {
4667 qup_uart0_rts: qup-uart0-rts-pins {
4672 qup_uart0_tx: qup-uart0-tx-pins {
4677 qup_uart0_rx: qup-uart0-rx-pins {
4682 qup_uart1_cts: qup-uart1-cts-pins {
4687 qup_uart1_rts: qup-uart1-rts-pins {
4692 qup_uart1_tx: qup-uart1-tx-pins {
4697 qup_uart1_rx: qup-uart1-rx-pins {
4702 qup_uart2_cts: qup-uart2-cts-pins {
4707 qup_uart2_rts: qup-uart2-rts-pins {
4712 qup_uart2_tx: qup-uart2-tx-pins {
4717 qup_uart2_rx: qup-uart2-rx-pins {
4722 qup_uart3_cts: qup-uart3-cts-pins {
4727 qup_uart3_rts: qup-uart3-rts-pins {
4732 qup_uart3_tx: qup-uart3-tx-pins {
4737 qup_uart3_rx: qup-uart3-rx-pins {
4742 qup_uart4_cts: qup-uart4-cts-pins {
4747 qup_uart4_rts: qup-uart4-rts-pins {
4752 qup_uart4_tx: qup-uart4-tx-pins {
4757 qup_uart4_rx: qup-uart4-rx-pins {
4762 qup_uart5_cts: qup-uart5-cts-pins {
4767 qup_uart5_rts: qup-uart5-rts-pins {
4772 qup_uart5_tx: qup-uart5-tx-pins {
4777 qup_uart5_rx: qup-uart5-rx-pins {
4782 qup_uart6_cts: qup-uart6-cts-pins {
4787 qup_uart6_rts: qup-uart6-rts-pins {
4792 qup_uart6_tx: qup-uart6-tx-pins {
4797 qup_uart6_rx: qup-uart6-rx-pins {
4802 qup_uart7_cts: qup-uart7-cts-pins {
4807 qup_uart7_rts: qup-uart7-rts-pins {
4812 qup_uart7_tx: qup-uart7-tx-pins {
4817 qup_uart7_rx: qup-uart7-rx-pins {
4822 qup_uart8_cts: qup-uart8-cts-pins {
4827 qup_uart8_rts: qup-uart8-rts-pins {
4832 qup_uart8_tx: qup-uart8-tx-pins {
4837 qup_uart8_rx: qup-uart8-rx-pins {
4842 qup_uart9_cts: qup-uart9-cts-pins {
4847 qup_uart9_rts: qup-uart9-rts-pins {
4852 qup_uart9_tx: qup-uart9-tx-pins {
4857 qup_uart9_rx: qup-uart9-rx-pins {
4862 qup_uart10_cts: qup-uart10-cts-pins {
4867 qup_uart10_rts: qup-uart10-rts-pins {
4872 qup_uart10_tx: qup-uart10-tx-pins {
4877 qup_uart10_rx: qup-uart10-rx-pins {
4882 qup_uart11_cts: qup-uart11-cts-pins {
4887 qup_uart11_rts: qup-uart11-rts-pins {
4892 qup_uart11_tx: qup-uart11-tx-pins {
4897 qup_uart11_rx: qup-uart11-rx-pins {
4902 qup_uart12_cts: qup-uart12-cts-pins {
4907 qup_uart12_rts: qup-uart12-rts-pins {
4912 qup_uart12_tx: qup-uart12-tx-pins {
4917 qup_uart12_rx: qup-uart12-rx-pins {
4922 qup_uart13_cts: qup-uart13-cts-pins {
4927 qup_uart13_rts: qup-uart13-rts-pins {
4932 qup_uart13_tx: qup-uart13-tx-pins {
4937 qup_uart13_rx: qup-uart13-rx-pins {
4942 qup_uart14_cts: qup-uart14-cts-pins {
4947 qup_uart14_rts: qup-uart14-rts-pins {
4952 qup_uart14_tx: qup-uart14-tx-pins {
4957 qup_uart14_rx: qup-uart14-rx-pins {
4962 qup_uart15_cts: qup-uart15-cts-pins {
4967 qup_uart15_rts: qup-uart15-rts-pins {
4972 qup_uart15_tx: qup-uart15-tx-pins {
4977 qup_uart15_rx: qup-uart15-rx-pins {
4982 sdc1_clk: sdc1-clk-pins {
4986 sdc1_cmd: sdc1-cmd-pins {
4990 sdc1_data: sdc1-data-pins {
4994 sdc1_rclk: sdc1-rclk-pins {
4998 sdc1_clk_sleep: sdc1-clk-sleep-pins {
5000 drive-strength = <2>;
5001 bias-bus-hold;
5004 sdc1_cmd_sleep: sdc1-cmd-sleep-pins {
5006 drive-strength = <2>;
5007 bias-bus-hold;
5010 sdc1_data_sleep: sdc1-data-sleep-pins {
5012 drive-strength = <2>;
5013 bias-bus-hold;
5016 sdc1_rclk_sleep: sdc1-rclk-sleep-pins {
5018 drive-strength = <2>;
5019 bias-bus-hold;
5022 sdc2_clk: sdc2-clk-pins {
5026 sdc2_cmd: sdc2-cmd-pins {
5030 sdc2_data: sdc2-data-pins {
5034 sdc2_clk_sleep: sdc2-clk-sleep-pins {
5036 drive-strength = <2>;
5037 bias-bus-hold;
5040 sdc2_cmd_sleep: sdc2-cmd-sleep-pins {
5042 drive-strength = <2>;
5043 bias-bus-hold;
5046 sdc2_data_sleep: sdc2-data-sleep-pins {
5048 drive-strength = <2>;
5049 bias-bus-hold;
5054 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd";
5057 #address-cells = <1>;
5058 #size-cells = <1>;
5062 pil-reloc@594c {
5063 compatible = "qcom,pil-reloc-info";
5069 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500";
5071 #iommu-cells = <2>;
5072 #global-interrupts = <1>;
5073 dma-coherent;
5157 intc: interrupt-controller@17a00000 {
5158 compatible = "arm,gic-v3";
5159 #address-cells = <2>;
5160 #size-cells = <2>;
5162 #interrupt-cells = <3>;
5163 interrupt-controller;
5168 gic-its@17a40000 {
5169 compatible = "arm,gic-v3-its";
5170 msi-controller;
5171 #msi-cells = <1>;
5178 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt";
5185 #address-cells = <1>;
5186 #size-cells = <1>;
5188 compatible = "arm,armv7-timer-mem";
5192 frame-number = <0>;
5200 frame-number = <1>;
5207 frame-number = <2>;
5214 frame-number = <3>;
5221 frame-number = <4>;
5228 frame-number = <5>;
5235 frame-number = <6>;
5243 compatible = "qcom,rpmh-rsc";
5247 reg-names = "drv-0", "drv-1", "drv-2";
5251 qcom,tcs-offset = <0xd00>;
5252 qcom,drv-id = <2>;
5253 qcom,tcs-config = <ACTIVE_TCS 2>,
5258 apps_bcm_voter: bcm-voter {
5259 compatible = "qcom,bcm-voter";
5262 rpmhpd: power-controller {
5263 compatible = "qcom,sc7280-rpmhpd";
5264 #power-domain-cells = <1>;
5265 operating-points-v2 = <&rpmhpd_opp_table>;
5267 rpmhpd_opp_table: opp-table {
5268 compatible = "operating-points-v2";
5271 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5275 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5279 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5283 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5287 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
5291 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5295 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5299 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5303 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5308 rpmhcc: clock-controller {
5309 compatible = "qcom,sc7280-rpmh-clk";
5311 clock-names = "xo";
5312 #clock-cells = <1>;
5317 compatible = "qcom,sc7280-epss-l3";
5320 clock-names = "xo", "alternate";
5321 #interconnect-cells = <1>;
5325 compatible = "qcom,cpufreq-epss";
5330 clock-names = "xo", "alternate";
5331 #freq-domain-cells = <1>;
5335 thermal_zones: thermal-zones {
5336 cpu0-thermal {
5337 polling-delay-passive = <250>;
5338 polling-delay = <0>;
5340 thermal-sensors = <&tsens0 1>;
5343 cpu0_alert0: trip-point0 {
5349 cpu0_alert1: trip-point1 {
5355 cpu0_crit: cpu-crit {
5362 cooling-maps {
5365 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5372 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5380 cpu1-thermal {
5381 polling-delay-passive = <250>;
5382 polling-delay = <0>;
5384 thermal-sensors = <&tsens0 2>;
5387 cpu1_alert0: trip-point0 {
5393 cpu1_alert1: trip-point1 {
5399 cpu1_crit: cpu-crit {
5406 cooling-maps {
5409 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5416 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5424 cpu2-thermal {
5425 polling-delay-passive = <250>;
5426 polling-delay = <0>;
5428 thermal-sensors = <&tsens0 3>;
5431 cpu2_alert0: trip-point0 {
5437 cpu2_alert1: trip-point1 {
5443 cpu2_crit: cpu-crit {
5450 cooling-maps {
5453 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5460 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5468 cpu3-thermal {
5469 polling-delay-passive = <250>;
5470 polling-delay = <0>;
5472 thermal-sensors = <&tsens0 4>;
5475 cpu3_alert0: trip-point0 {
5481 cpu3_alert1: trip-point1 {
5487 cpu3_crit: cpu-crit {
5494 cooling-maps {
5497 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5504 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5512 cpu4-thermal {
5513 polling-delay-passive = <250>;
5514 polling-delay = <0>;
5516 thermal-sensors = <&tsens0 7>;
5519 cpu4_alert0: trip-point0 {
5525 cpu4_alert1: trip-point1 {
5531 cpu4_crit: cpu-crit {
5538 cooling-maps {
5541 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5548 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5556 cpu5-thermal {
5557 polling-delay-passive = <250>;
5558 polling-delay = <0>;
5560 thermal-sensors = <&tsens0 8>;
5563 cpu5_alert0: trip-point0 {
5569 cpu5_alert1: trip-point1 {
5575 cpu5_crit: cpu-crit {
5582 cooling-maps {
5585 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5592 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5600 cpu6-thermal {
5601 polling-delay-passive = <250>;
5602 polling-delay = <0>;
5604 thermal-sensors = <&tsens0 9>;
5607 cpu6_alert0: trip-point0 {
5613 cpu6_alert1: trip-point1 {
5619 cpu6_crit: cpu-crit {
5626 cooling-maps {
5629 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5636 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5644 cpu7-thermal {
5645 polling-delay-passive = <250>;
5646 polling-delay = <0>;
5648 thermal-sensors = <&tsens0 10>;
5651 cpu7_alert0: trip-point0 {
5657 cpu7_alert1: trip-point1 {
5663 cpu7_crit: cpu-crit {
5670 cooling-maps {
5673 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5680 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5688 cpu8-thermal {
5689 polling-delay-passive = <250>;
5690 polling-delay = <0>;
5692 thermal-sensors = <&tsens0 11>;
5695 cpu8_alert0: trip-point0 {
5701 cpu8_alert1: trip-point1 {
5707 cpu8_crit: cpu-crit {
5714 cooling-maps {
5717 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5724 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5732 cpu9-thermal {
5733 polling-delay-passive = <250>;
5734 polling-delay = <0>;
5736 thermal-sensors = <&tsens0 12>;
5739 cpu9_alert0: trip-point0 {
5745 cpu9_alert1: trip-point1 {
5751 cpu9_crit: cpu-crit {
5758 cooling-maps {
5761 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5768 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5776 cpu10-thermal {
5777 polling-delay-passive = <250>;
5778 polling-delay = <0>;
5780 thermal-sensors = <&tsens0 13>;
5783 cpu10_alert0: trip-point0 {
5789 cpu10_alert1: trip-point1 {
5795 cpu10_crit: cpu-crit {
5802 cooling-maps {
5805 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5812 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5820 cpu11-thermal {
5821 polling-delay-passive = <250>;
5822 polling-delay = <0>;
5824 thermal-sensors = <&tsens0 14>;
5827 cpu11_alert0: trip-point0 {
5833 cpu11_alert1: trip-point1 {
5839 cpu11_crit: cpu-crit {
5846 cooling-maps {
5849 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5856 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5864 aoss0-thermal {
5865 polling-delay-passive = <0>;
5866 polling-delay = <0>;
5868 thermal-sensors = <&tsens0 0>;
5871 aoss0_alert0: trip-point0 {
5877 aoss0_crit: aoss0-crit {
5885 aoss1-thermal {
5886 polling-delay-passive = <0>;
5887 polling-delay = <0>;
5889 thermal-sensors = <&tsens1 0>;
5892 aoss1_alert0: trip-point0 {
5898 aoss1_crit: aoss1-crit {
5906 cpuss0-thermal {
5907 polling-delay-passive = <0>;
5908 polling-delay = <0>;
5910 thermal-sensors = <&tsens0 5>;
5913 cpuss0_alert0: trip-point0 {
5918 cpuss0_crit: cluster0-crit {
5926 cpuss1-thermal {
5927 polling-delay-passive = <0>;
5928 polling-delay = <0>;
5930 thermal-sensors = <&tsens0 6>;
5933 cpuss1_alert0: trip-point0 {
5938 cpuss1_crit: cluster0-crit {
5946 gpuss0-thermal {
5947 polling-delay-passive = <100>;
5948 polling-delay = <0>;
5950 thermal-sensors = <&tsens1 1>;
5953 gpuss0_alert0: trip-point0 {
5959 gpuss0_crit: gpuss0-crit {
5966 cooling-maps {
5969 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5974 gpuss1-thermal {
5975 polling-delay-passive = <100>;
5976 polling-delay = <0>;
5978 thermal-sensors = <&tsens1 2>;
5981 gpuss1_alert0: trip-point0 {
5987 gpuss1_crit: gpuss1-crit {
5994 cooling-maps {
5997 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6002 nspss0-thermal {
6003 polling-delay-passive = <0>;
6004 polling-delay = <0>;
6006 thermal-sensors = <&tsens1 3>;
6009 nspss0_alert0: trip-point0 {
6015 nspss0_crit: nspss0-crit {
6023 nspss1-thermal {
6024 polling-delay-passive = <0>;
6025 polling-delay = <0>;
6027 thermal-sensors = <&tsens1 4>;
6030 nspss1_alert0: trip-point0 {
6036 nspss1_crit: nspss1-crit {
6044 video-thermal {
6045 polling-delay-passive = <0>;
6046 polling-delay = <0>;
6048 thermal-sensors = <&tsens1 5>;
6051 video_alert0: trip-point0 {
6057 video_crit: video-crit {
6065 ddr-thermal {
6066 polling-delay-passive = <0>;
6067 polling-delay = <0>;
6069 thermal-sensors = <&tsens1 6>;
6072 ddr_alert0: trip-point0 {
6078 ddr_crit: ddr-crit {
6086 mdmss0-thermal {
6087 polling-delay-passive = <0>;
6088 polling-delay = <0>;
6090 thermal-sensors = <&tsens1 7>;
6093 mdmss0_alert0: trip-point0 {
6099 mdmss0_crit: mdmss0-crit {
6107 mdmss1-thermal {
6108 polling-delay-passive = <0>;
6109 polling-delay = <0>;
6111 thermal-sensors = <&tsens1 8>;
6114 mdmss1_alert0: trip-point0 {
6120 mdmss1_crit: mdmss1-crit {
6128 mdmss2-thermal {
6129 polling-delay-passive = <0>;
6130 polling-delay = <0>;
6132 thermal-sensors = <&tsens1 9>;
6135 mdmss2_alert0: trip-point0 {
6141 mdmss2_crit: mdmss2-crit {
6149 mdmss3-thermal {
6150 polling-delay-passive = <0>;
6151 polling-delay = <0>;
6153 thermal-sensors = <&tsens1 10>;
6156 mdmss3_alert0: trip-point0 {
6162 mdmss3_crit: mdmss3-crit {
6170 camera0-thermal {
6171 polling-delay-passive = <0>;
6172 polling-delay = <0>;
6174 thermal-sensors = <&tsens1 11>;
6177 camera0_alert0: trip-point0 {
6183 camera0_crit: camera0-crit {
6193 compatible = "arm,armv8-timer";