Lines Matching +full:1 +full:a98000
158 qcom,client-id = <1>;
262 qcom,freq-domain = <&cpufreq_hw 1>;
282 qcom,freq-domain = <&cpufreq_hw 1>;
302 qcom,freq-domain = <&cpufreq_hw 1>;
379 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
389 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
399 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
664 #qcom,smem-state-cells = <1>;
688 #qcom,smem-state-cells = <1>;
708 qcom,remote-pid = <1>;
712 #qcom,smem-state-cells = <1>;
723 #qcom,smem-state-cells = <1>;
747 #qcom,smem-state-cells = <1>;
829 #clock-cells = <1>;
830 #reset-cells = <1>;
831 #power-domain-cells = <1>;
853 #address-cells = <1>;
854 #size-cells = <1>;
856 gpu_speed_bin: gpu_speed_bin@1e9 {
866 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>;
894 mmc-ddr-1_8v;
895 mmc-hs200-1_8v;
896 mmc-hs400-1_8v;
963 #address-cells = <1>;
971 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
984 #address-cells = <1>;
992 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1021 #address-cells = <1>;
1028 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1029 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1042 #address-cells = <1>;
1049 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1050 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1079 #address-cells = <1>;
1087 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1100 #address-cells = <1>;
1108 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1137 #address-cells = <1>;
1145 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1158 #address-cells = <1>;
1166 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1195 #address-cells = <1>;
1203 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1216 #address-cells = <1>;
1224 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1253 #address-cells = <1>;
1261 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1274 #address-cells = <1>;
1282 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1311 #address-cells = <1>;
1319 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1332 #address-cells = <1>;
1340 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1369 #address-cells = <1>;
1377 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1390 #address-cells = <1>;
1398 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1462 #address-cells = <1>;
1470 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1483 #address-cells = <1>;
1491 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1520 #address-cells = <1>;
1527 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1528 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1541 #address-cells = <1>;
1548 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1549 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1578 #address-cells = <1>;
1586 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1599 #address-cells = <1>;
1607 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1636 #address-cells = <1>;
1644 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1657 #address-cells = <1>;
1665 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1694 #address-cells = <1>;
1702 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1715 #address-cells = <1>;
1723 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1752 #address-cells = <1>;
1760 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1773 #address-cells = <1>;
1781 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1802 i2c14: i2c@a98000 {
1810 #address-cells = <1>;
1818 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1823 spi14: spi@a98000 {
1831 #address-cells = <1>;
1839 <&gpi_dma1 1 6 QCOM_GPI_SPI>;
1844 uart14: serial@a98000 {
1868 #address-cells = <1>;
1876 <&gpi_dma1 1 7 QCOM_GPI_I2C>;
1889 #address-cells = <1>;
1897 <&gpi_dma1 1 7 QCOM_GPI_SPI>;
2009 pcie1: pci@1c08000 {
2019 linux,pci-domain = <1>;
2031 #interrupt-cells = <1>;
2033 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
2088 pcie1_phy: phy@1c0e000 {
2108 pcie1_lane: phy@1c0e200 {
2124 ipa: ipa@1e40000 {
2139 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
2156 <&ipa_smp2p_out 1>;
2163 tcsr_mutex: hwlock@1f40000 {
2166 #hwlock-cells = <1>;
2169 tcsr_1: syscon@1f60000 {
2174 tcsr_2: syscon@1fc0000 {
2186 #clock-cells = <1>;
2206 #sound-dai-cells = <1>;
2235 #sound-dai-cells = <1>;
2259 #sound-dai-cells = <1>;
2288 qcom,port-offset = <1>;
2290 #sound-dai-cells = <1>;
2305 #clock-cells = <1>;
2306 #power-domain-cells = <1>;
2307 #reset-cells = <1>;
2325 #sound-dai-cells = <1>;
2337 #clock-cells = <1>;
2338 #power-domain-cells = <1>;
2347 #clock-cells = <1>;
2348 #power-domain-cells = <1>;
2396 #sound-dai-cells = <1>;
2397 #address-cells = <1>;
2417 #clock-cells = <1>;
2418 #power-domain-cells = <1>;
2437 #clock-cells = <1>;
2564 opp-550000000-1 {
2657 #clock-cells = <1>;
2658 #reset-cells = <1>;
2659 #power-domain-cells = <1>;
2705 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2747 qcom,remote-pid = <1>;
2785 #address-cells = <1>;
2813 #address-cells = <1>;
2841 #address-cells = <1>;
2851 port@1 {
2852 reg = <1>;
2918 #address-cells = <1>;
3155 #address-cells = <1>;
3165 port@1 {
3166 reg = <1>;
3244 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>;
3357 #clock-cells = <1>;
3423 #address-cells = <1>;
3443 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3504 opp-1 {
3543 opp-1 {
3596 port@1 {
3755 #clock-cells = <1>;
3756 #reset-cells = <1>;
3757 #power-domain-cells = <1>;
3767 #clock-cells = <1>;
3768 #reset-cells = <1>;
3769 #power-domain-cells = <1>;
3778 <&mdss_dsi_phy 1>,
3780 <&dp_phy 1>,
3782 <&mdss_edp_phy 1>;
3791 #clock-cells = <1>;
3792 #reset-cells = <1>;
3793 #power-domain-cells = <1>;
3812 #interrupt-cells = <1>;
3856 #address-cells = <1>;
3866 port@1 {
3867 reg = <1>;
3933 #address-cells = <1>;
3939 #address-cells = <1>;
3949 port@1 {
3950 reg = <1>;
3985 #clock-cells = <1>;
4020 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
4031 #address-cells = <1>;
4041 port@1 {
4042 reg = <1>;
4085 #clock-cells = <1>;
4115 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
4127 #address-cells = <1>;
4137 port@1 {
4138 reg = <1>;
4172 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
4174 <64 434 2>, <66 438 3>, <69 86 1>,
4175 <70 520 54>, <124 609 31>, <155 63 1>,
4185 #reset-cells = <1>;
4196 #thermal-sensor-cells = <1>;
4207 #thermal-sensor-cells = <1>;
4213 #reset-cells = <1>;
4242 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4245 #address-cells = <1>;
4246 #size-cells = <1>;
5057 #address-cells = <1>;
5058 #size-cells = <1>;
5072 #global-interrupts = <1>;
5171 #msi-cells = <1>;
5185 #address-cells = <1>;
5186 #size-cells = <1>;
5200 frame-number = <1>;
5247 reg-names = "drv-0", "drv-1", "drv-2";
5256 <CONTROL_TCS 1>;
5264 #power-domain-cells = <1>;
5312 #clock-cells = <1>;
5321 #interconnect-cells = <1>;
5331 #freq-domain-cells = <1>;
5340 thermal-sensors = <&tsens0 1>;
5950 thermal-sensors = <&tsens1 1>;