Lines Matching +full:0 +full:x17a10040
77 #clock-cells = <0>;
83 #clock-cells = <0>;
94 reg = <0x0 0x004cd000 0x0 0x1000>;
98 reg = <0x0 0x80000000 0x0 0x600000>;
103 reg = <0x0 0x80600000 0x0 0x200000>;
108 reg = <0x0 0x80800000 0x0 0x60000>;
113 reg = <0x0 0x80860000 0x0 0x20000>;
119 reg = <0x0 0x80884000 0x0 0x10000>;
124 reg = <0x0 0x808ff000 0x0 0x1000>;
129 reg = <0x0 0x80900000 0x0 0x200000>;
135 reg = <0x0 0x80b00000 0x0 0x100000>;
139 reg = <0x0 0x80c00000 0x0 0xc00000>;
144 reg = <0x0 0x8b200000 0x0 0x500000>;
149 reg = <0 0x8b700000 0 0x10000>;
155 reg = <0x0 0x9c900000 0x0 0x280000>;
165 #size-cells = <0>;
167 CPU0: cpu@0 {
170 reg = <0x0 0x0>;
179 qcom,freq-domain = <&cpufreq_hw 0>;
193 reg = <0x0 0x100>;
202 qcom,freq-domain = <&cpufreq_hw 0>;
213 reg = <0x0 0x200>;
222 qcom,freq-domain = <&cpufreq_hw 0>;
233 reg = <0x0 0x300>;
242 qcom,freq-domain = <&cpufreq_hw 0>;
253 reg = <0x0 0x400>;
273 reg = <0x0 0x500>;
293 reg = <0x0 0x600>;
313 reg = <0x0 0x700>;
369 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
372 arm,psci-suspend-param = <0x40000003>;
379 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
382 arm,psci-suspend-param = <0x40000004>;
389 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
392 arm,psci-suspend-param = <0x40000003>;
402 arm,psci-suspend-param = <0x40000004>;
409 CLUSTER_SLEEP_0: cluster-sleep-0 {
412 arm,psci-suspend-param = <0x40003444>;
629 reg = <0 0x80000000 0 0>;
659 qcom,local-pid = <0>;
683 qcom,local-pid = <0>;
707 qcom,local-pid = <0>;
742 qcom,local-pid = <0>;
810 soc: soc@0 {
813 ranges = <0 0 0 0 0x10 0>;
814 dma-ranges = <0 0 0 0 0x10 0>;
819 reg = <0 0x00100000 0 0x1f0000>;
822 <0>, <&pcie1_lane>,
823 <0>, <0>, <0>, <0>;
837 reg = <0 0x00408000 0 0x1000>;
846 reg = <0 0x00784000 0 0xa20>,
847 <0 0x00780000 0 0xa20>,
848 <0 0x00782000 0 0x120>,
849 <0 0x00786000 0 0x1fff>;
857 reg = <0x1e9 0x2>;
865 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>;
869 reg = <0 0x007c4000 0 0x1000>,
870 <0 0x007c5000 0 0x1000>;
873 iommus = <&apps_smmu 0xc0 0x0>;
882 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>,
883 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>;
891 qcom,dll-config = <0x0007642c>;
892 qcom,ddr-config = <0x80040868>;
908 opp-avg-kBps = <100000 0>;
915 opp-avg-kBps = <390000 0>;
924 reg = <0 0x00900000 0 0x60000>;
938 dma-channel-mask = <0x7f>;
939 iommus = <&apps_smmu 0x0136 0x0>;
945 reg = <0 0x009c0000 0 0x2000>;
952 iommus = <&apps_smmu 0x123 0x0>;
957 reg = <0 0x00980000 0 0x4000>;
961 pinctrl-0 = <&qup_i2c0_data_clk>;
964 #size-cells = <0>;
965 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
966 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
967 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
970 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
971 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
978 reg = <0 0x00980000 0 0x4000>;
982 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
985 #size-cells = <0>;
988 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
989 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
991 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
992 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
999 reg = <0 0x00980000 0 0x4000>;
1003 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>;
1007 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1008 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1015 reg = <0 0x00984000 0 0x4000>;
1019 pinctrl-0 = <&qup_i2c1_data_clk>;
1022 #size-cells = <0>;
1023 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1024 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1025 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1028 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1036 reg = <0 0x00984000 0 0x4000>;
1040 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1043 #size-cells = <0>;
1046 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1047 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1049 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1057 reg = <0 0x00984000 0 0x4000>;
1061 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
1065 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1066 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1073 reg = <0 0x00988000 0 0x4000>;
1077 pinctrl-0 = <&qup_i2c2_data_clk>;
1080 #size-cells = <0>;
1081 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1082 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1083 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1086 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1094 reg = <0 0x00988000 0 0x4000>;
1098 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1101 #size-cells = <0>;
1104 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1105 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1107 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1115 reg = <0 0x00988000 0 0x4000>;
1119 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>;
1123 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1124 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1131 reg = <0 0x0098c000 0 0x4000>;
1135 pinctrl-0 = <&qup_i2c3_data_clk>;
1138 #size-cells = <0>;
1139 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1140 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1141 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1144 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1152 reg = <0 0x0098c000 0 0x4000>;
1156 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1159 #size-cells = <0>;
1162 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1163 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1165 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1173 reg = <0 0x0098c000 0 0x4000>;
1177 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>;
1181 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1182 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1189 reg = <0 0x00990000 0 0x4000>;
1193 pinctrl-0 = <&qup_i2c4_data_clk>;
1196 #size-cells = <0>;
1197 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1198 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1199 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1202 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1210 reg = <0 0x00990000 0 0x4000>;
1214 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1217 #size-cells = <0>;
1220 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1221 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1223 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1231 reg = <0 0x00990000 0 0x4000>;
1235 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>;
1239 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1240 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1247 reg = <0 0x00994000 0 0x4000>;
1251 pinctrl-0 = <&qup_i2c5_data_clk>;
1254 #size-cells = <0>;
1255 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1256 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1257 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1260 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1268 reg = <0 0x00994000 0 0x4000>;
1272 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1275 #size-cells = <0>;
1278 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1279 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1281 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1289 reg = <0 0x00994000 0 0x4000>;
1293 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>;
1297 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1298 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1305 reg = <0 0x00998000 0 0x4000>;
1309 pinctrl-0 = <&qup_i2c6_data_clk>;
1312 #size-cells = <0>;
1313 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1314 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1315 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1318 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1326 reg = <0 0x00998000 0 0x4000>;
1330 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1333 #size-cells = <0>;
1336 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1337 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1339 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1347 reg = <0 0x00998000 0 0x4000>;
1351 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>;
1355 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1356 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1363 reg = <0 0x0099c000 0 0x4000>;
1367 pinctrl-0 = <&qup_i2c7_data_clk>;
1370 #size-cells = <0>;
1371 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1372 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1373 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1376 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1384 reg = <0 0x0099c000 0 0x4000>;
1388 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
1391 #size-cells = <0>;
1394 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1395 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1397 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1405 reg = <0 0x0099c000 0 0x4000>;
1409 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>;
1413 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1414 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1423 reg = <0 0x00a00000 0 0x60000>;
1437 dma-channel-mask = <0x1e>;
1438 iommus = <&apps_smmu 0x56 0x0>;
1444 reg = <0 0x00ac0000 0 0x2000>;
1451 iommus = <&apps_smmu 0x43 0x0>;
1456 reg = <0 0x00a80000 0 0x4000>;
1460 pinctrl-0 = <&qup_i2c8_data_clk>;
1463 #size-cells = <0>;
1464 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1465 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1466 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1469 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1470 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1477 reg = <0 0x00a80000 0 0x4000>;
1481 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1484 #size-cells = <0>;
1487 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1488 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1490 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1491 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1498 reg = <0 0x00a80000 0 0x4000>;
1502 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>;
1506 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1507 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1514 reg = <0 0x00a84000 0 0x4000>;
1518 pinctrl-0 = <&qup_i2c9_data_clk>;
1521 #size-cells = <0>;
1522 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1523 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1524 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1527 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1535 reg = <0 0x00a84000 0 0x4000>;
1539 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1542 #size-cells = <0>;
1545 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1546 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1548 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1556 reg = <0 0x00a84000 0 0x4000>;
1560 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>;
1564 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1565 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1572 reg = <0 0x00a88000 0 0x4000>;
1576 pinctrl-0 = <&qup_i2c10_data_clk>;
1579 #size-cells = <0>;
1580 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1581 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1582 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1585 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1593 reg = <0 0x00a88000 0 0x4000>;
1597 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1600 #size-cells = <0>;
1603 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1604 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1606 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1614 reg = <0 0x00a88000 0 0x4000>;
1618 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>;
1622 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1623 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1630 reg = <0 0x00a8c000 0 0x4000>;
1634 pinctrl-0 = <&qup_i2c11_data_clk>;
1637 #size-cells = <0>;
1638 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1639 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1640 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1643 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1651 reg = <0 0x00a8c000 0 0x4000>;
1655 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1658 #size-cells = <0>;
1661 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1662 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1664 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1672 reg = <0 0x00a8c000 0 0x4000>;
1676 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>;
1680 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1681 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1688 reg = <0 0x00a90000 0 0x4000>;
1692 pinctrl-0 = <&qup_i2c12_data_clk>;
1695 #size-cells = <0>;
1696 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1697 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1698 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1701 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1709 reg = <0 0x00a90000 0 0x4000>;
1713 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1716 #size-cells = <0>;
1719 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1720 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1722 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1730 reg = <0 0x00a90000 0 0x4000>;
1734 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>;
1738 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1739 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1746 reg = <0 0x00a94000 0 0x4000>;
1750 pinctrl-0 = <&qup_i2c13_data_clk>;
1753 #size-cells = <0>;
1754 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1755 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1756 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1759 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1767 reg = <0 0x00a94000 0 0x4000>;
1771 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1774 #size-cells = <0>;
1777 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1778 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1780 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1788 reg = <0 0x00a94000 0 0x4000>;
1792 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>;
1796 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1797 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1804 reg = <0 0x00a98000 0 0x4000>;
1808 pinctrl-0 = <&qup_i2c14_data_clk>;
1811 #size-cells = <0>;
1812 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1813 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1814 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1817 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1825 reg = <0 0x00a98000 0 0x4000>;
1829 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1832 #size-cells = <0>;
1835 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1836 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1838 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1846 reg = <0 0x00a98000 0 0x4000>;
1850 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>;
1854 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1855 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1862 reg = <0 0x00a9c000 0 0x4000>;
1866 pinctrl-0 = <&qup_i2c15_data_clk>;
1869 #size-cells = <0>;
1870 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1871 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1872 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1875 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
1883 reg = <0 0x00a9c000 0 0x4000>;
1887 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1890 #size-cells = <0>;
1893 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1894 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1896 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
1904 reg = <0 0x00a9c000 0 0x4000>;
1908 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>;
1912 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1913 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1920 reg = <0 0x01500000 0 0x1000>;
1927 reg = <0 0x01502000 0 0x1000>;
1934 reg = <0 0x01580000 0 0x4>;
1941 reg = <0 0x01680000 0 0x15480>;
1949 reg = <0 0x016e0000 0 0x1c080>;
1955 reg = <0 0x01700000 0 0x2b080>;
1962 reg = <0 0x01740000 0 0x1e080>;
1970 reg = <0 0x17a10040 0 0x0>;
1971 iommus = <&apps_smmu 0x1c00 0x1>;
2011 reg = <0 0x01c08000 0 0x3000>,
2012 <0 0x40000000 0 0xf1d>,
2013 <0 0x40000f20 0 0xa8>,
2014 <0 0x40001000 0 0x1000>,
2015 <0 0x40100000 0 0x100000>;
2020 bus-range = <0x00 0xff>;
2026 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
2027 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2032 interrupt-map-mask = <0 0 0 0x7>;
2033 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
2034 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>,
2035 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>,
2036 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>;
2078 pinctrl-0 = <&pcie1_clkreq_n>;
2080 iommus = <&apps_smmu 0x1c80 0x1>;
2082 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2083 <0x100 &apps_smmu 0x1c81 0x1>;
2090 reg = <0 0x01c0e000 0 0x1c0>;
2109 reg = <0 0x01c0e200 0 0x170>,
2110 <0 0x01c0e400 0 0x200>,
2111 <0 0x01c0ea00 0 0x1f0>,
2112 <0 0x01c0e600 0 0x170>,
2113 <0 0x01c0e800 0 0x200>,
2114 <0 0x01c0ee00 0 0xf4>;
2118 #phy-cells = <0>;
2119 #clock-cells = <0>;
2127 iommus = <&apps_smmu 0x480 0x0>,
2128 <&apps_smmu 0x482 0x0>;
2129 reg = <0 0x1e40000 0 0x8000>,
2130 <0 0x1e50000 0 0x4ad0>,
2131 <0 0x1e04000 0 0x23000>;
2138 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2148 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
2149 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>;
2155 qcom,smem-states = <&ipa_smp2p_out 0>,
2165 reg = <0 0x01f40000 0 0x20000>;
2171 reg = <0 0x01f60000 0 0x20000>;
2176 reg = <0 0x01fc0000 0 0x30000>;
2181 reg = <0 0x03000000 0 0x40>,
2182 <0 0x03c04000 0 0x4>;
2191 reg = <0 0x03200000 0 0x1000>;
2194 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>;
2205 #clock-cells = <0>;
2213 reg = <0 0x03210000 0 0x2000>;
2219 qcom,din-ports = <0>;
2225 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2226 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>;
2227 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>;
2228 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2229 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2230 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2231 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2232 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2233 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2237 #size-cells = <0>;
2244 reg = <0 0x03220000 0 0x1000>;
2247 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>;
2258 #clock-cells = <0>;
2266 reg = <0 0x03230000 0 0x2000>;
2274 qcom,dout-ports = <0>;
2279 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>;
2280 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>;
2281 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>;
2282 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>;
2283 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>;
2284 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>;
2285 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>;
2286 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>;
2287 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>;
2292 #size-cells = <0>;
2299 reg = <0 0x03300000 0 0x30000>,
2300 <0 0x032a9000 0 0x1000>;
2312 reg = <0 0x03370000 0 0x1000>;
2315 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>;
2324 #clock-cells = <0>;
2332 reg = <0 0x03380000 0 0x30000>;
2343 reg = <0 0x03900000 0 0x50000>;
2354 reg = <0 0x03987000 0 0x68000>,
2355 <0 0x03b00000 0 0x29000>,
2356 <0 0x03260000 0 0xc000>,
2357 <0 0x03280000 0 0x29000>,
2358 <0 0x03340000 0 0x29000>,
2359 <0 0x0336c000 0 0x3000>;
2367 iommus = <&apps_smmu 0x1820 0>,
2368 <&apps_smmu 0x1821 0>,
2369 <&apps_smmu 0x1832 0>;
2398 #size-cells = <0>;
2414 reg = <0 0x3c00000 0 0x28>;
2422 reg = <0 0x03c40000 0 0xf080>;
2430 reg = <0 0x033c0000 0x0 0x20000>,
2431 <0 0x03550000 0x0 0x10000>;
2435 gpio-ranges = <&lpass_tlmm 0 0 15>;
2522 reg = <0 0x03d00000 0 0x40000>,
2523 <0 0x03d9e000 0 0x1000>,
2524 <0 0x03d61000 0 0x800>;
2529 iommus = <&adreno_smmu 0 0x401>;
2532 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
2546 opp-supported-hw = <0x03>;
2553 opp-supported-hw = <0x03>;
2557 opp-550000000-0 {
2561 opp-supported-hw = <0x01>;
2568 opp-supported-hw = <0x02>;
2575 opp-supported-hw = <0x02>;
2582 opp-supported-hw = <0x02>;
2589 opp-supported-hw = <0x02>;
2596 opp-supported-hw = <0x02>;
2603 opp-supported-hw = <0x02>;
2610 reg = <0 0x03d6a000 0 0x34000>,
2611 <0 0x3de0000 0 0x10000>,
2612 <0 0x0b290000 0 0x10000>;
2635 iommus = <&adreno_smmu 5 0x400>;
2650 reg = <0 0x03d90000 0 0x9000>;
2664 reg = <0 0x03da0000 0 0x20000>;
2700 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>;
2704 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2727 qcom,smem-states = <&modem_smp2p_out 0>;
2734 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x8000 0x13000>;
2735 qcom,ext-regs = <&tcsr_2 0x10000 0x10004 &tcsr_1 0x6004 0x6008>;
2736 qcom,qaccept-regs = <&tcsr_1 0x3030 0x3040 0x3020>;
2753 reg = <0 0x06002000 0 0x1000>,
2754 <0 0x16280000 0 0x180000>;
2771 reg = <0 0x06041000 0 0x1000>;
2786 #size-cells = <0>;
2799 reg = <0 0x06042000 0 0x1000>;
2814 #size-cells = <0>;
2827 reg = <0 0x06045000 0 0x1000>;
2842 #size-cells = <0>;
2844 port@0 {
2845 reg = <0>;
2862 reg = <0 0x06046000 0 0x1000>;
2886 reg = <0 0x06048000 0 0x1000>;
2887 iommus = <&apps_smmu 0x04c0 0>;
2904 reg = <0 0x06b04000 0 0x1000>;
2919 #size-cells = <0>;
2932 reg = <0 0x06b05000 0 0x1000>;
2956 reg = <0 0x06b06000 0 0x1000>;
2981 reg = <0 0x07040000 0 0x1000>;
3001 reg = <0 0x07140000 0 0x1000>;
3021 reg = <0 0x07240000 0 0x1000>;
3041 reg = <0 0x07340000 0 0x1000>;
3061 reg = <0 0x07440000 0 0x1000>;
3081 reg = <0 0x07540000 0 0x1000>;
3101 reg = <0 0x07640000 0 0x1000>;
3121 reg = <0 0x07740000 0 0x1000>;
3141 reg = <0 0x07800000 0 0x1000>;
3156 #size-cells = <0>;
3158 port@0 {
3159 reg = <0>;
3218 reg = <0 0x07810000 0 0x1000>;
3243 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>;
3247 reg = <0 0x08804000 0 0x1000>;
3249 iommus = <&apps_smmu 0x100 0x0>;
3258 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
3259 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>;
3266 qcom,dll-config = <0x0007642c>;
3277 opp-avg-kBps = <100000 0>;
3284 opp-avg-kBps = <200000 0>;
3293 reg = <0 0x088e3000 0 0x400>;
3295 #phy-cells = <0>;
3306 reg = <0 0x088e4000 0 0x400>;
3308 #phy-cells = <0>;
3319 reg = <0 0x088e9000 0 0x200>,
3320 <0 0x088e8000 0 0x40>,
3321 <0 0x088ea000 0 0x200>;
3337 reg = <0 0x088e9200 0 0x200>,
3338 <0 0x088e9400 0 0x200>,
3339 <0 0x088e9c00 0 0x400>,
3340 <0 0x088e9600 0 0x200>,
3341 <0 0x088e9800 0 0x200>,
3342 <0 0x088e9a00 0 0x100>;
3343 #clock-cells = <0>;
3344 #phy-cells = <0>;
3351 reg = <0 0x088ea200 0 0x200>,
3352 <0 0x088ea400 0 0x200>,
3353 <0 0x088eaa00 0 0x200>,
3354 <0 0x088ea600 0 0x200>,
3355 <0 0x088ea800 0 0x200>;
3356 #phy-cells = <0>;
3363 reg = <0 0x08cf8800 0 0x400>;
3397 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>,
3398 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>;
3403 reg = <0 0x08c00000 0 0xe000>;
3405 iommus = <&apps_smmu 0xa0 0x0>;
3422 reg = <0 0x088dc000 0 0x1000>;
3424 #size-cells = <0>;
3429 interconnects = <&gem_noc MASTER_APPSS_PROC 0
3430 &cnoc2 SLAVE_QSPI_0 0>;
3439 reg = <0 0x08a00000 0 0x10000>;
3442 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3465 qcom,smem-states = <&wpss_smp2p_out 0>;
3472 qcom,halt-regs = <&tcsr_1 0x17000>;
3490 reg = <0 0x9091000 0 0x1000>;
3501 opp-0 {
3530 reg = <0 0x090b6400 0 0x600>;
3540 opp-0 {
3565 reg = <0 0x090e0000 0 0x5080>;
3572 reg = <0 0x9100000 0 0xe2200>;
3580 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>;
3587 reg = <0 0x88e0000 0 0x2000>,
3588 <0 0x88e2000 0 0x1000>;
3591 port@0 {
3607 port@0 {
3616 reg = <0 0x0a0c0000 0 0x10000>;
3624 reg = <0 0x0a6f8800 0 0x400>;
3660 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
3661 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>;
3668 reg = <0 0x0a600000 0 0xe000>;
3670 iommus = <&apps_smmu 0xe0 0x0>;
3681 reg = <0 0x0aa00000 0 0xd0600>;
3698 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>,
3699 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>;
3702 iommus = <&apps_smmu 0x2180 0x20>,
3703 <&apps_smmu 0x2184 0x20>;
3715 iommus = <&apps_smmu 0x21a2 0x0>;
3751 reg = <0 0xaaf0000 0 0x10000>;
3762 reg = <0 0x0ad00000 0 0x10000>;
3774 reg = <0 0xaf00000 0 0x20000>;
3777 <&mdss_dsi_phy 0>,
3779 <&dp_phy 0>,
3781 <&mdss_edp_phy 0>,
3798 reg = <0 0x0ae00000 0 0x1000>;
3814 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
3817 iommus = <&apps_smmu 0x900 0x402>;
3827 reg = <0 0x0ae01000 0 0x8f030>,
3828 <0 0x0aeb0000 0 0x2008>;
3851 interrupts = <0>;
3857 #size-cells = <0>;
3859 port@0 {
3860 reg = <0>;
3908 reg = <0 0x0ae94000 0 0x400>;
3934 #size-cells = <0>;
3940 #size-cells = <0>;
3942 port@0 {
3943 reg = <0>;
3978 reg = <0 0x0ae94400 0 0x200>,
3979 <0 0x0ae94600 0 0x280>,
3980 <0 0x0ae94900 0 0x280>;
3986 #phy-cells = <0>;
3998 pinctrl-0 = <&edp_hot_plug_det>;
4000 reg = <0 0xaea0000 0 0x200>,
4001 <0 0xaea0200 0 0x200>,
4002 <0 0xaea0400 0 0xc00>,
4003 <0 0xaea1000 0 0x400>;
4020 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
4032 #size-cells = <0>;
4034 port@0 {
4035 reg = <0>;
4075 reg = <0 0xaec2a00 0 0x19c>,
4076 <0 0xaec2200 0 0xa0>,
4077 <0 0xaec2600 0 0xa0>,
4078 <0 0xaec2000 0 0x1c0>;
4086 #phy-cells = <0>;
4094 reg = <0 0xae90000 0 0x200>,
4095 <0 0xae90200 0 0x200>,
4096 <0 0xae90400 0 0xc00>,
4097 <0 0xae91000 0 0x400>,
4098 <0 0xae91400 0 0x400>;
4115 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
4122 #sound-dai-cells = <0>;
4128 #size-cells = <0>;
4130 port@0 {
4131 reg = <0>;
4171 reg = <0 0x0b220000 0 0x30000>;
4172 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
4184 reg = <0 0x0b5e0000 0 0x20000>;
4190 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4191 <0 0x0c222000 0 0x1ff>; /* SROT */
4201 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4202 <0 0x0c223000 0 0x1ff>; /* SROT */
4212 reg = <0 0x0c2a0000 0 0x31000>;
4218 reg = <0 0x0c300000 0 0x400>;
4225 #clock-cells = <0>;
4230 reg = <0 0x0c3f0000 0 0x400>;
4235 reg = <0 0x0c440000 0 0x1100>,
4236 <0 0x0c600000 0 0x2000000>,
4237 <0 0x0e600000 0 0x100000>,
4238 <0 0x0e700000 0 0xa0000>,
4239 <0 0x0c40a000 0 0x26000>;
4243 qcom,ee = <0>;
4244 qcom,channel = <0>;
4253 reg = <0 0x0f100000 0 0x300000>;
4259 gpio-ranges = <&tlmm 0 0 175>;
5055 reg = <0 0x146a5000 0 0x6000>;
5060 ranges = <0 0 0x146a5000 0x6000>;
5064 reg = <0x594c 0xc8>;
5070 reg = <0 0x15000000 0 0x100000>;
5164 reg = <0 0x17a00000 0 0x10000>, /* GICD */
5165 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
5172 reg = <0 0x17a40000 0 0x20000>;
5179 reg = <0 0x17c10000 0 0x1000>;
5181 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
5187 ranges = <0 0 0 0x20000000>;
5189 reg = <0 0x17c20000 0 0x1000>;
5192 frame-number = <0>;
5195 reg = <0x17c21000 0x1000>,
5196 <0x17c22000 0x1000>;
5202 reg = <0x17c23000 0x1000>;
5209 reg = <0x17c25000 0x1000>;
5216 reg = <0x17c27000 0x1000>;
5223 reg = <0x17c29000 0x1000>;
5230 reg = <0x17c2b000 0x1000>;
5237 reg = <0x17c2d000 0x1000>;
5244 reg = <0 0x18200000 0 0x10000>,
5245 <0 0x18210000 0 0x10000>,
5246 <0 0x18220000 0 0x10000>;
5247 reg-names = "drv-0", "drv-1", "drv-2";
5251 qcom,tcs-offset = <0xd00>;
5318 reg = <0 0x18590000 0 0x1000>;
5326 reg = <0 0x18591000 0 0x1000>,
5327 <0 0x18592000 0 0x1000>,
5328 <0 0x18593000 0 0x1000>;
5338 polling-delay = <0>;
5357 hysteresis = <0>;
5382 polling-delay = <0>;
5401 hysteresis = <0>;
5426 polling-delay = <0>;
5445 hysteresis = <0>;
5470 polling-delay = <0>;
5489 hysteresis = <0>;
5514 polling-delay = <0>;
5533 hysteresis = <0>;
5558 polling-delay = <0>;
5577 hysteresis = <0>;
5602 polling-delay = <0>;
5621 hysteresis = <0>;
5646 polling-delay = <0>;
5665 hysteresis = <0>;
5690 polling-delay = <0>;
5709 hysteresis = <0>;
5734 polling-delay = <0>;
5753 hysteresis = <0>;
5778 polling-delay = <0>;
5797 hysteresis = <0>;
5822 polling-delay = <0>;
5841 hysteresis = <0>;
5865 polling-delay-passive = <0>;
5866 polling-delay = <0>;
5868 thermal-sensors = <&tsens0 0>;
5879 hysteresis = <0>;
5886 polling-delay-passive = <0>;
5887 polling-delay = <0>;
5889 thermal-sensors = <&tsens1 0>;
5900 hysteresis = <0>;
5907 polling-delay-passive = <0>;
5908 polling-delay = <0>;
5920 hysteresis = <0>;
5927 polling-delay-passive = <0>;
5928 polling-delay = <0>;
5940 hysteresis = <0>;
5948 polling-delay = <0>;
5961 hysteresis = <0>;
5976 polling-delay = <0>;
5989 hysteresis = <0>;
6003 polling-delay-passive = <0>;
6004 polling-delay = <0>;
6017 hysteresis = <0>;
6024 polling-delay-passive = <0>;
6025 polling-delay = <0>;
6038 hysteresis = <0>;
6045 polling-delay-passive = <0>;
6046 polling-delay = <0>;
6059 hysteresis = <0>;
6066 polling-delay-passive = <0>;
6067 polling-delay = <0>;
6080 hysteresis = <0>;
6087 polling-delay-passive = <0>;
6088 polling-delay = <0>;
6101 hysteresis = <0>;
6108 polling-delay-passive = <0>;
6109 polling-delay = <0>;
6122 hysteresis = <0>;
6129 polling-delay-passive = <0>;
6130 polling-delay = <0>;
6143 hysteresis = <0>;
6150 polling-delay-passive = <0>;
6151 polling-delay = <0>;
6164 hysteresis = <0>;
6171 polling-delay-passive = <0>;
6172 polling-delay = <0>;
6185 hysteresis = <0>;