Lines Matching +full:opp +full:- +full:160000000
1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
11 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
12 #include <dt-bindings/clock/qcom,rpmh.h>
13 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
15 #include <dt-bindings/interconnect/qcom,sc7180.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/phy/phy-qcom-qusb2.h>
18 #include <dt-bindings/power/qcom-rpmpd.h>
19 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
20 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
21 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
22 #include <dt-bindings/thermal/thermal.h>
25 interrupt-parent = <&intc>;
27 #address-cells = <2>;
28 #size-cells = <2>;
58 xo_board: xo-board {
59 compatible = "fixed-clock";
60 clock-frequency = <38400000>;
61 #clock-cells = <0>;
64 sleep_clk: sleep-clk {
65 compatible = "fixed-clock";
66 clock-frequency = <32764>;
67 #clock-cells = <0>;
71 reserved_memory: reserved-memory {
72 #address-cells = <2>;
73 #size-cells = <2>;
78 no-map;
83 no-map;
88 no-map;
93 compatible = "qcom,cmd-db";
94 no-map;
99 no-map;
104 no-map;
109 no-map;
114 no-map;
118 compatible = "qcom,rmtfs-mem";
120 no-map;
122 qcom,client-id = <1>;
128 #address-cells = <2>;
129 #size-cells = <0>;
135 enable-method = "psci";
136 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
139 capacity-dmips-mhz = <415>;
140 dynamic-power-coefficient = <137>;
141 operating-points-v2 = <&cpu0_opp_table>;
144 next-level-cache = <&L2_0>;
145 #cooling-cells = <2>;
146 qcom,freq-domain = <&cpufreq_hw 0>;
147 L2_0: l2-cache {
149 next-level-cache = <&L3_0>;
150 L3_0: l3-cache {
160 enable-method = "psci";
161 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
164 capacity-dmips-mhz = <415>;
165 dynamic-power-coefficient = <137>;
166 next-level-cache = <&L2_100>;
167 operating-points-v2 = <&cpu0_opp_table>;
170 #cooling-cells = <2>;
171 qcom,freq-domain = <&cpufreq_hw 0>;
172 L2_100: l2-cache {
174 next-level-cache = <&L3_0>;
182 enable-method = "psci";
183 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
186 capacity-dmips-mhz = <415>;
187 dynamic-power-coefficient = <137>;
188 next-level-cache = <&L2_200>;
189 operating-points-v2 = <&cpu0_opp_table>;
192 #cooling-cells = <2>;
193 qcom,freq-domain = <&cpufreq_hw 0>;
194 L2_200: l2-cache {
196 next-level-cache = <&L3_0>;
204 enable-method = "psci";
205 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
208 capacity-dmips-mhz = <415>;
209 dynamic-power-coefficient = <137>;
210 next-level-cache = <&L2_300>;
211 operating-points-v2 = <&cpu0_opp_table>;
214 #cooling-cells = <2>;
215 qcom,freq-domain = <&cpufreq_hw 0>;
216 L2_300: l2-cache {
218 next-level-cache = <&L3_0>;
226 enable-method = "psci";
227 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
230 capacity-dmips-mhz = <415>;
231 dynamic-power-coefficient = <137>;
232 next-level-cache = <&L2_400>;
233 operating-points-v2 = <&cpu0_opp_table>;
236 #cooling-cells = <2>;
237 qcom,freq-domain = <&cpufreq_hw 0>;
238 L2_400: l2-cache {
240 next-level-cache = <&L3_0>;
248 enable-method = "psci";
249 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
252 capacity-dmips-mhz = <415>;
253 dynamic-power-coefficient = <137>;
254 next-level-cache = <&L2_500>;
255 operating-points-v2 = <&cpu0_opp_table>;
258 #cooling-cells = <2>;
259 qcom,freq-domain = <&cpufreq_hw 0>;
260 L2_500: l2-cache {
262 next-level-cache = <&L3_0>;
270 enable-method = "psci";
271 cpu-idle-states = <&BIG_CPU_SLEEP_0
274 capacity-dmips-mhz = <1024>;
275 dynamic-power-coefficient = <480>;
276 next-level-cache = <&L2_600>;
277 operating-points-v2 = <&cpu6_opp_table>;
280 #cooling-cells = <2>;
281 qcom,freq-domain = <&cpufreq_hw 1>;
282 L2_600: l2-cache {
284 next-level-cache = <&L3_0>;
292 enable-method = "psci";
293 cpu-idle-states = <&BIG_CPU_SLEEP_0
296 capacity-dmips-mhz = <1024>;
297 dynamic-power-coefficient = <480>;
298 next-level-cache = <&L2_700>;
299 operating-points-v2 = <&cpu6_opp_table>;
302 #cooling-cells = <2>;
303 qcom,freq-domain = <&cpufreq_hw 1>;
304 L2_700: l2-cache {
306 next-level-cache = <&L3_0>;
310 cpu-map {
346 idle-states {
347 entry-method = "psci";
349 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
350 compatible = "arm,idle-state";
351 idle-state-name = "little-power-down";
352 arm,psci-suspend-param = <0x40000003>;
353 entry-latency-us = <549>;
354 exit-latency-us = <901>;
355 min-residency-us = <1774>;
356 local-timer-stop;
359 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
360 compatible = "arm,idle-state";
361 idle-state-name = "little-rail-power-down";
362 arm,psci-suspend-param = <0x40000004>;
363 entry-latency-us = <702>;
364 exit-latency-us = <915>;
365 min-residency-us = <4001>;
366 local-timer-stop;
369 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
370 compatible = "arm,idle-state";
371 idle-state-name = "big-power-down";
372 arm,psci-suspend-param = <0x40000003>;
373 entry-latency-us = <523>;
374 exit-latency-us = <1244>;
375 min-residency-us = <2207>;
376 local-timer-stop;
379 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
380 compatible = "arm,idle-state";
381 idle-state-name = "big-rail-power-down";
382 arm,psci-suspend-param = <0x40000004>;
383 entry-latency-us = <526>;
384 exit-latency-us = <1854>;
385 min-residency-us = <5555>;
386 local-timer-stop;
389 CLUSTER_SLEEP_0: cluster-sleep-0 {
390 compatible = "arm,idle-state";
391 idle-state-name = "cluster-power-down";
392 arm,psci-suspend-param = <0x40003444>;
393 entry-latency-us = <3263>;
394 exit-latency-us = <6562>;
395 min-residency-us = <9926>;
396 local-timer-stop;
401 cpu0_opp_table: opp-table-cpu0 {
402 compatible = "operating-points-v2";
403 opp-shared;
405 cpu0_opp1: opp-300000000 {
406 opp-hz = /bits/ 64 <300000000>;
407 opp-peak-kBps = <1200000 4800000>;
410 cpu0_opp2: opp-576000000 {
411 opp-hz = /bits/ 64 <576000000>;
412 opp-peak-kBps = <1200000 4800000>;
415 cpu0_opp3: opp-768000000 {
416 opp-hz = /bits/ 64 <768000000>;
417 opp-peak-kBps = <1200000 4800000>;
420 cpu0_opp4: opp-1017600000 {
421 opp-hz = /bits/ 64 <1017600000>;
422 opp-peak-kBps = <1804000 8908800>;
425 cpu0_opp5: opp-1248000000 {
426 opp-hz = /bits/ 64 <1248000000>;
427 opp-peak-kBps = <2188000 12902400>;
430 cpu0_opp6: opp-1324800000 {
431 opp-hz = /bits/ 64 <1324800000>;
432 opp-peak-kBps = <2188000 12902400>;
435 cpu0_opp7: opp-1516800000 {
436 opp-hz = /bits/ 64 <1516800000>;
437 opp-peak-kBps = <3072000 15052800>;
440 cpu0_opp8: opp-1612800000 {
441 opp-hz = /bits/ 64 <1612800000>;
442 opp-peak-kBps = <3072000 15052800>;
445 cpu0_opp9: opp-1708800000 {
446 opp-hz = /bits/ 64 <1708800000>;
447 opp-peak-kBps = <3072000 15052800>;
450 cpu0_opp10: opp-1804800000 {
451 opp-hz = /bits/ 64 <1804800000>;
452 opp-peak-kBps = <4068000 22425600>;
456 cpu6_opp_table: opp-table-cpu6 {
457 compatible = "operating-points-v2";
458 opp-shared;
460 cpu6_opp1: opp-300000000 {
461 opp-hz = /bits/ 64 <300000000>;
462 opp-peak-kBps = <2188000 8908800>;
465 cpu6_opp2: opp-652800000 {
466 opp-hz = /bits/ 64 <652800000>;
467 opp-peak-kBps = <2188000 8908800>;
470 cpu6_opp3: opp-825600000 {
471 opp-hz = /bits/ 64 <825600000>;
472 opp-peak-kBps = <2188000 8908800>;
475 cpu6_opp4: opp-979200000 {
476 opp-hz = /bits/ 64 <979200000>;
477 opp-peak-kBps = <2188000 8908800>;
480 cpu6_opp5: opp-1113600000 {
481 opp-hz = /bits/ 64 <1113600000>;
482 opp-peak-kBps = <2188000 8908800>;
485 cpu6_opp6: opp-1267200000 {
486 opp-hz = /bits/ 64 <1267200000>;
487 opp-peak-kBps = <4068000 12902400>;
490 cpu6_opp7: opp-1555200000 {
491 opp-hz = /bits/ 64 <1555200000>;
492 opp-peak-kBps = <4068000 15052800>;
495 cpu6_opp8: opp-1708800000 {
496 opp-hz = /bits/ 64 <1708800000>;
497 opp-peak-kBps = <6220000 19353600>;
500 cpu6_opp9: opp-1843200000 {
501 opp-hz = /bits/ 64 <1843200000>;
502 opp-peak-kBps = <6220000 19353600>;
505 cpu6_opp10: opp-1900800000 {
506 opp-hz = /bits/ 64 <1900800000>;
507 opp-peak-kBps = <6220000 22425600>;
510 cpu6_opp11: opp-1996800000 {
511 opp-hz = /bits/ 64 <1996800000>;
512 opp-peak-kBps = <6220000 22425600>;
515 cpu6_opp12: opp-2112000000 {
516 opp-hz = /bits/ 64 <2112000000>;
517 opp-peak-kBps = <6220000 22425600>;
520 cpu6_opp13: opp-2208000000 {
521 opp-hz = /bits/ 64 <2208000000>;
522 opp-peak-kBps = <7216000 22425600>;
525 cpu6_opp14: opp-2323200000 {
526 opp-hz = /bits/ 64 <2323200000>;
527 opp-peak-kBps = <7216000 22425600>;
530 cpu6_opp15: opp-2400000000 {
531 opp-hz = /bits/ 64 <2400000000>;
532 opp-peak-kBps = <8532000 23347200>;
535 cpu6_opp16: opp-2553600000 {
536 opp-hz = /bits/ 64 <2553600000>;
537 opp-peak-kBps = <8532000 23347200>;
548 compatible = "arm,armv8-pmuv3";
554 compatible = "qcom,scm-sc7180", "qcom,scm";
560 memory-region = <&smem_mem>;
564 smp2p-cdsp {
572 qcom,local-pid = <0>;
573 qcom,remote-pid = <5>;
575 cdsp_smp2p_out: master-kernel {
576 qcom,entry-name = "master-kernel";
577 #qcom,smem-state-cells = <1>;
580 cdsp_smp2p_in: slave-kernel {
581 qcom,entry-name = "slave-kernel";
583 interrupt-controller;
584 #interrupt-cells = <2>;
588 smp2p-lpass {
596 qcom,local-pid = <0>;
597 qcom,remote-pid = <2>;
599 adsp_smp2p_out: master-kernel {
600 qcom,entry-name = "master-kernel";
601 #qcom,smem-state-cells = <1>;
604 adsp_smp2p_in: slave-kernel {
605 qcom,entry-name = "slave-kernel";
607 interrupt-controller;
608 #interrupt-cells = <2>;
612 smp2p-mpss {
617 qcom,local-pid = <0>;
618 qcom,remote-pid = <1>;
620 modem_smp2p_out: master-kernel {
621 qcom,entry-name = "master-kernel";
622 #qcom,smem-state-cells = <1>;
625 modem_smp2p_in: slave-kernel {
626 qcom,entry-name = "slave-kernel";
627 interrupt-controller;
628 #interrupt-cells = <2>;
631 ipa_smp2p_out: ipa-ap-to-modem {
632 qcom,entry-name = "ipa";
633 #qcom,smem-state-cells = <1>;
636 ipa_smp2p_in: ipa-modem-to-ap {
637 qcom,entry-name = "ipa";
638 interrupt-controller;
639 #interrupt-cells = <2>;
644 compatible = "arm,psci-1.0";
649 #address-cells = <2>;
650 #size-cells = <2>;
652 dma-ranges = <0 0 0 0 0x10 0>;
653 compatible = "simple-bus";
655 gcc: clock-controller@100000 {
656 compatible = "qcom,gcc-sc7180";
661 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
662 #clock-cells = <1>;
663 #reset-cells = <1>;
664 #power-domain-cells = <1>;
668 compatible = "qcom,sc7180-qfprom", "qcom,qfprom";
675 clock-names = "core";
676 #address-cells = <1>;
677 #size-cells = <1>;
679 qusb2p_hstx_trim: hstx-trim-primary@25b {
691 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
694 reg-names = "hc", "cqhci";
699 interrupt-names = "hc_irq", "pwr_irq";
704 clock-names = "iface", "core", "xo";
707 interconnect-names = "sdhc-ddr","cpu-sdhc";
708 power-domains = <&rpmhpd SC7180_CX>;
709 operating-points-v2 = <&sdhc1_opp_table>;
711 bus-width = <8>;
712 non-removable;
713 supports-cqe;
715 mmc-ddr-1_8v;
716 mmc-hs200-1_8v;
717 mmc-hs400-1_8v;
718 mmc-hs400-enhanced-strobe;
722 sdhc1_opp_table: opp-table {
723 compatible = "operating-points-v2";
725 opp-100000000 {
726 opp-hz = /bits/ 64 <100000000>;
727 required-opps = <&rpmhpd_opp_low_svs>;
728 opp-peak-kBps = <1800000 600000>;
729 opp-avg-kBps = <100000 0>;
732 opp-384000000 {
733 opp-hz = /bits/ 64 <384000000>;
734 required-opps = <&rpmhpd_opp_nom>;
735 opp-peak-kBps = <5400000 1600000>;
736 opp-avg-kBps = <390000 0>;
741 qup_opp_table: opp-table-qup {
742 compatible = "operating-points-v2";
744 opp-75000000 {
745 opp-hz = /bits/ 64 <75000000>;
746 required-opps = <&rpmhpd_opp_low_svs>;
749 opp-100000000 {
750 opp-hz = /bits/ 64 <100000000>;
751 required-opps = <&rpmhpd_opp_svs>;
754 opp-128000000 {
755 opp-hz = /bits/ 64 <128000000>;
756 required-opps = <&rpmhpd_opp_nom>;
761 compatible = "qcom,geni-se-qup";
763 clock-names = "m-ahb", "s-ahb";
766 #address-cells = <2>;
767 #size-cells = <2>;
773 compatible = "qcom,geni-i2c";
775 clock-names = "se";
777 pinctrl-names = "default";
778 pinctrl-0 = <&qup_i2c0_default>;
780 #address-cells = <1>;
781 #size-cells = <0>;
785 interconnect-names = "qup-core", "qup-config",
786 "qup-memory";
787 power-domains = <&rpmhpd SC7180_CX>;
788 required-opps = <&rpmhpd_opp_low_svs>;
793 compatible = "qcom,geni-spi";
795 clock-names = "se";
797 pinctrl-names = "default";
798 pinctrl-0 = <&qup_spi0_default>;
800 #address-cells = <1>;
801 #size-cells = <0>;
802 power-domains = <&rpmhpd SC7180_CX>;
803 operating-points-v2 = <&qup_opp_table>;
806 interconnect-names = "qup-core", "qup-config";
811 compatible = "qcom,geni-uart";
813 clock-names = "se";
815 pinctrl-names = "default";
816 pinctrl-0 = <&qup_uart0_default>;
818 power-domains = <&rpmhpd SC7180_CX>;
819 operating-points-v2 = <&qup_opp_table>;
822 interconnect-names = "qup-core", "qup-config";
827 compatible = "qcom,geni-i2c";
829 clock-names = "se";
831 pinctrl-names = "default";
832 pinctrl-0 = <&qup_i2c1_default>;
834 #address-cells = <1>;
835 #size-cells = <0>;
839 interconnect-names = "qup-core", "qup-config",
840 "qup-memory";
841 power-domains = <&rpmhpd SC7180_CX>;
842 required-opps = <&rpmhpd_opp_low_svs>;
847 compatible = "qcom,geni-spi";
849 clock-names = "se";
851 pinctrl-names = "default";
852 pinctrl-0 = <&qup_spi1_default>;
854 #address-cells = <1>;
855 #size-cells = <0>;
856 power-domains = <&rpmhpd SC7180_CX>;
857 operating-points-v2 = <&qup_opp_table>;
860 interconnect-names = "qup-core", "qup-config";
865 compatible = "qcom,geni-uart";
867 clock-names = "se";
869 pinctrl-names = "default";
870 pinctrl-0 = <&qup_uart1_default>;
872 power-domains = <&rpmhpd SC7180_CX>;
873 operating-points-v2 = <&qup_opp_table>;
876 interconnect-names = "qup-core", "qup-config";
881 compatible = "qcom,geni-i2c";
883 clock-names = "se";
885 pinctrl-names = "default";
886 pinctrl-0 = <&qup_i2c2_default>;
888 #address-cells = <1>;
889 #size-cells = <0>;
893 interconnect-names = "qup-core", "qup-config",
894 "qup-memory";
895 power-domains = <&rpmhpd SC7180_CX>;
896 required-opps = <&rpmhpd_opp_low_svs>;
901 compatible = "qcom,geni-uart";
903 clock-names = "se";
905 pinctrl-names = "default";
906 pinctrl-0 = <&qup_uart2_default>;
908 power-domains = <&rpmhpd SC7180_CX>;
909 operating-points-v2 = <&qup_opp_table>;
912 interconnect-names = "qup-core", "qup-config";
917 compatible = "qcom,geni-i2c";
919 clock-names = "se";
921 pinctrl-names = "default";
922 pinctrl-0 = <&qup_i2c3_default>;
924 #address-cells = <1>;
925 #size-cells = <0>;
929 interconnect-names = "qup-core", "qup-config",
930 "qup-memory";
931 power-domains = <&rpmhpd SC7180_CX>;
932 required-opps = <&rpmhpd_opp_low_svs>;
937 compatible = "qcom,geni-spi";
939 clock-names = "se";
941 pinctrl-names = "default";
942 pinctrl-0 = <&qup_spi3_default>;
944 #address-cells = <1>;
945 #size-cells = <0>;
946 power-domains = <&rpmhpd SC7180_CX>;
947 operating-points-v2 = <&qup_opp_table>;
950 interconnect-names = "qup-core", "qup-config";
955 compatible = "qcom,geni-uart";
957 clock-names = "se";
959 pinctrl-names = "default";
960 pinctrl-0 = <&qup_uart3_default>;
962 power-domains = <&rpmhpd SC7180_CX>;
963 operating-points-v2 = <&qup_opp_table>;
966 interconnect-names = "qup-core", "qup-config";
971 compatible = "qcom,geni-i2c";
973 clock-names = "se";
975 pinctrl-names = "default";
976 pinctrl-0 = <&qup_i2c4_default>;
978 #address-cells = <1>;
979 #size-cells = <0>;
983 interconnect-names = "qup-core", "qup-config",
984 "qup-memory";
985 power-domains = <&rpmhpd SC7180_CX>;
986 required-opps = <&rpmhpd_opp_low_svs>;
991 compatible = "qcom,geni-uart";
993 clock-names = "se";
995 pinctrl-names = "default";
996 pinctrl-0 = <&qup_uart4_default>;
998 power-domains = <&rpmhpd SC7180_CX>;
999 operating-points-v2 = <&qup_opp_table>;
1002 interconnect-names = "qup-core", "qup-config";
1007 compatible = "qcom,geni-i2c";
1009 clock-names = "se";
1011 pinctrl-names = "default";
1012 pinctrl-0 = <&qup_i2c5_default>;
1014 #address-cells = <1>;
1015 #size-cells = <0>;
1019 interconnect-names = "qup-core", "qup-config",
1020 "qup-memory";
1021 power-domains = <&rpmhpd SC7180_CX>;
1022 required-opps = <&rpmhpd_opp_low_svs>;
1027 compatible = "qcom,geni-spi";
1029 clock-names = "se";
1031 pinctrl-names = "default";
1032 pinctrl-0 = <&qup_spi5_default>;
1034 #address-cells = <1>;
1035 #size-cells = <0>;
1036 power-domains = <&rpmhpd SC7180_CX>;
1037 operating-points-v2 = <&qup_opp_table>;
1040 interconnect-names = "qup-core", "qup-config";
1045 compatible = "qcom,geni-uart";
1047 clock-names = "se";
1049 pinctrl-names = "default";
1050 pinctrl-0 = <&qup_uart5_default>;
1052 power-domains = <&rpmhpd SC7180_CX>;
1053 operating-points-v2 = <&qup_opp_table>;
1056 interconnect-names = "qup-core", "qup-config";
1062 compatible = "qcom,geni-se-qup";
1064 clock-names = "m-ahb", "s-ahb";
1067 #address-cells = <2>;
1068 #size-cells = <2>;
1074 compatible = "qcom,geni-i2c";
1076 clock-names = "se";
1078 pinctrl-names = "default";
1079 pinctrl-0 = <&qup_i2c6_default>;
1081 #address-cells = <1>;
1082 #size-cells = <0>;
1086 interconnect-names = "qup-core", "qup-config",
1087 "qup-memory";
1088 power-domains = <&rpmhpd SC7180_CX>;
1089 required-opps = <&rpmhpd_opp_low_svs>;
1094 compatible = "qcom,geni-spi";
1096 clock-names = "se";
1098 pinctrl-names = "default";
1099 pinctrl-0 = <&qup_spi6_default>;
1101 #address-cells = <1>;
1102 #size-cells = <0>;
1103 power-domains = <&rpmhpd SC7180_CX>;
1104 operating-points-v2 = <&qup_opp_table>;
1107 interconnect-names = "qup-core", "qup-config";
1112 compatible = "qcom,geni-uart";
1114 clock-names = "se";
1116 pinctrl-names = "default";
1117 pinctrl-0 = <&qup_uart6_default>;
1119 power-domains = <&rpmhpd SC7180_CX>;
1120 operating-points-v2 = <&qup_opp_table>;
1123 interconnect-names = "qup-core", "qup-config";
1128 compatible = "qcom,geni-i2c";
1130 clock-names = "se";
1132 pinctrl-names = "default";
1133 pinctrl-0 = <&qup_i2c7_default>;
1135 #address-cells = <1>;
1136 #size-cells = <0>;
1140 interconnect-names = "qup-core", "qup-config",
1141 "qup-memory";
1142 power-domains = <&rpmhpd SC7180_CX>;
1143 required-opps = <&rpmhpd_opp_low_svs>;
1148 compatible = "qcom,geni-uart";
1150 clock-names = "se";
1152 pinctrl-names = "default";
1153 pinctrl-0 = <&qup_uart7_default>;
1155 power-domains = <&rpmhpd SC7180_CX>;
1156 operating-points-v2 = <&qup_opp_table>;
1159 interconnect-names = "qup-core", "qup-config";
1164 compatible = "qcom,geni-i2c";
1166 clock-names = "se";
1168 pinctrl-names = "default";
1169 pinctrl-0 = <&qup_i2c8_default>;
1171 #address-cells = <1>;
1172 #size-cells = <0>;
1176 interconnect-names = "qup-core", "qup-config",
1177 "qup-memory";
1178 power-domains = <&rpmhpd SC7180_CX>;
1179 required-opps = <&rpmhpd_opp_low_svs>;
1184 compatible = "qcom,geni-spi";
1186 clock-names = "se";
1188 pinctrl-names = "default";
1189 pinctrl-0 = <&qup_spi8_default>;
1191 #address-cells = <1>;
1192 #size-cells = <0>;
1193 power-domains = <&rpmhpd SC7180_CX>;
1194 operating-points-v2 = <&qup_opp_table>;
1197 interconnect-names = "qup-core", "qup-config";
1202 compatible = "qcom,geni-debug-uart";
1204 clock-names = "se";
1206 pinctrl-names = "default";
1207 pinctrl-0 = <&qup_uart8_default>;
1209 power-domains = <&rpmhpd SC7180_CX>;
1210 operating-points-v2 = <&qup_opp_table>;
1213 interconnect-names = "qup-core", "qup-config";
1218 compatible = "qcom,geni-i2c";
1220 clock-names = "se";
1222 pinctrl-names = "default";
1223 pinctrl-0 = <&qup_i2c9_default>;
1225 #address-cells = <1>;
1226 #size-cells = <0>;
1230 interconnect-names = "qup-core", "qup-config",
1231 "qup-memory";
1232 power-domains = <&rpmhpd SC7180_CX>;
1233 required-opps = <&rpmhpd_opp_low_svs>;
1238 compatible = "qcom,geni-uart";
1240 clock-names = "se";
1242 pinctrl-names = "default";
1243 pinctrl-0 = <&qup_uart9_default>;
1245 power-domains = <&rpmhpd SC7180_CX>;
1246 operating-points-v2 = <&qup_opp_table>;
1249 interconnect-names = "qup-core", "qup-config";
1254 compatible = "qcom,geni-i2c";
1256 clock-names = "se";
1258 pinctrl-names = "default";
1259 pinctrl-0 = <&qup_i2c10_default>;
1261 #address-cells = <1>;
1262 #size-cells = <0>;
1266 interconnect-names = "qup-core", "qup-config",
1267 "qup-memory";
1268 power-domains = <&rpmhpd SC7180_CX>;
1269 required-opps = <&rpmhpd_opp_low_svs>;
1274 compatible = "qcom,geni-spi";
1276 clock-names = "se";
1278 pinctrl-names = "default";
1279 pinctrl-0 = <&qup_spi10_default>;
1281 #address-cells = <1>;
1282 #size-cells = <0>;
1283 power-domains = <&rpmhpd SC7180_CX>;
1284 operating-points-v2 = <&qup_opp_table>;
1287 interconnect-names = "qup-core", "qup-config";
1292 compatible = "qcom,geni-uart";
1294 clock-names = "se";
1296 pinctrl-names = "default";
1297 pinctrl-0 = <&qup_uart10_default>;
1299 power-domains = <&rpmhpd SC7180_CX>;
1300 operating-points-v2 = <&qup_opp_table>;
1303 interconnect-names = "qup-core", "qup-config";
1308 compatible = "qcom,geni-i2c";
1310 clock-names = "se";
1312 pinctrl-names = "default";
1313 pinctrl-0 = <&qup_i2c11_default>;
1315 #address-cells = <1>;
1316 #size-cells = <0>;
1320 interconnect-names = "qup-core", "qup-config",
1321 "qup-memory";
1322 power-domains = <&rpmhpd SC7180_CX>;
1323 required-opps = <&rpmhpd_opp_low_svs>;
1328 compatible = "qcom,geni-spi";
1330 clock-names = "se";
1332 pinctrl-names = "default";
1333 pinctrl-0 = <&qup_spi11_default>;
1335 #address-cells = <1>;
1336 #size-cells = <0>;
1337 power-domains = <&rpmhpd SC7180_CX>;
1338 operating-points-v2 = <&qup_opp_table>;
1341 interconnect-names = "qup-core", "qup-config";
1346 compatible = "qcom,geni-uart";
1348 clock-names = "se";
1350 pinctrl-names = "default";
1351 pinctrl-0 = <&qup_uart11_default>;
1353 power-domains = <&rpmhpd SC7180_CX>;
1354 operating-points-v2 = <&qup_opp_table>;
1357 interconnect-names = "qup-core", "qup-config";
1363 compatible = "qcom,sc7180-config-noc";
1365 #interconnect-cells = <2>;
1366 qcom,bcm-voters = <&apps_bcm_voter>;
1370 compatible = "qcom,sc7180-system-noc";
1372 #interconnect-cells = <2>;
1373 qcom,bcm-voters = <&apps_bcm_voter>;
1377 compatible = "qcom,sc7180-mc-virt";
1379 #interconnect-cells = <2>;
1380 qcom,bcm-voters = <&apps_bcm_voter>;
1384 compatible = "qcom,sc7180-qup-virt";
1386 #interconnect-cells = <2>;
1387 qcom,bcm-voters = <&apps_bcm_voter>;
1391 compatible = "qcom,sc7180-aggre1-noc";
1393 #interconnect-cells = <2>;
1394 qcom,bcm-voters = <&apps_bcm_voter>;
1398 compatible = "qcom,sc7180-aggre2-noc";
1400 #interconnect-cells = <2>;
1401 qcom,bcm-voters = <&apps_bcm_voter>;
1405 compatible = "qcom,sc7180-compute-noc";
1407 #interconnect-cells = <2>;
1408 qcom,bcm-voters = <&apps_bcm_voter>;
1412 compatible = "qcom,sc7180-mmss-noc";
1414 #interconnect-cells = <2>;
1415 qcom,bcm-voters = <&apps_bcm_voter>;
1419 compatible = "qcom,sc7180-ipa";
1426 reg-names = "ipa-reg",
1427 "ipa-shared",
1430 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
1434 interrupt-names = "ipa",
1436 "ipa-clock-query",
1437 "ipa-setup-ready";
1440 clock-names = "core";
1445 interconnect-names = "memory",
1451 qcom,smem-states = <&ipa_smp2p_out 0>,
1453 qcom,smem-state-names = "ipa-clock-enabled-valid",
1454 "ipa-clock-enabled";
1460 compatible = "qcom,tcsr-mutex";
1462 #hwlock-cells = <1>;
1466 compatible = "qcom,sc7180-tcsr", "syscon";
1471 compatible = "qcom,sc7180-tcsr", "syscon";
1476 compatible = "qcom,sc7180-pinctrl";
1480 reg-names = "west", "north", "south";
1482 gpio-controller;
1483 #gpio-cells = <2>;
1484 interrupt-controller;
1485 #interrupt-cells = <2>;
1486 gpio-ranges = <&tlmm 0 0 120>;
1487 wakeup-parent = <&pdc>;
1489 dp_hot_plug_det: dp-hot-plug-det {
1496 qspi_clk: qspi-clk {
1503 qspi_cs0: qspi-cs0 {
1510 qspi_cs1: qspi-cs1 {
1517 qspi_data01: qspi-data01 {
1518 pinmux-data {
1524 qspi_data12: qspi-data12 {
1525 pinmux-data {
1531 qup_i2c0_default: qup-i2c0-default {
1538 qup_i2c1_default: qup-i2c1-default {
1545 qup_i2c2_default: qup-i2c2-default {
1552 qup_i2c3_default: qup-i2c3-default {
1559 qup_i2c4_default: qup-i2c4-default {
1566 qup_i2c5_default: qup-i2c5-default {
1573 qup_i2c6_default: qup-i2c6-default {
1580 qup_i2c7_default: qup-i2c7-default {
1587 qup_i2c8_default: qup-i2c8-default {
1594 qup_i2c9_default: qup-i2c9-default {
1601 qup_i2c10_default: qup-i2c10-default {
1608 qup_i2c11_default: qup-i2c11-default {
1615 qup_spi0_default: qup-spi0-default {
1623 qup_spi0_cs_gpio: qup-spi0-cs-gpio {
1630 pinmux-cs {
1636 qup_spi1_default: qup-spi1-default {
1644 qup_spi1_cs_gpio: qup-spi1-cs-gpio {
1651 pinmux-cs {
1657 qup_spi3_default: qup-spi3-default {
1665 qup_spi3_cs_gpio: qup-spi3-cs-gpio {
1672 pinmux-cs {
1678 qup_spi5_default: qup-spi5-default {
1686 qup_spi5_cs_gpio: qup-spi5-cs-gpio {
1693 pinmux-cs {
1699 qup_spi6_default: qup-spi6-default {
1707 qup_spi6_cs_gpio: qup-spi6-cs-gpio {
1714 pinmux-cs {
1720 qup_spi8_default: qup-spi8-default {
1728 qup_spi8_cs_gpio: qup-spi8-cs-gpio {
1735 pinmux-cs {
1741 qup_spi10_default: qup-spi10-default {
1749 qup_spi10_cs_gpio: qup-spi10-cs-gpio {
1756 pinmux-cs {
1762 qup_spi11_default: qup-spi11-default {
1770 qup_spi11_cs_gpio: qup-spi11-cs-gpio {
1777 pinmux-cs {
1783 qup_uart0_default: qup-uart0-default {
1791 qup_uart1_default: qup-uart1-default {
1799 qup_uart2_default: qup-uart2-default {
1806 qup_uart3_default: qup-uart3-default {
1814 qup_uart4_default: qup-uart4-default {
1821 qup_uart5_default: qup-uart5-default {
1829 qup_uart6_default: qup-uart6-default {
1837 qup_uart7_default: qup-uart7-default {
1844 qup_uart8_default: qup-uart8-default {
1851 qup_uart9_default: qup-uart9-default {
1858 qup_uart10_default: qup-uart10-default {
1866 qup_uart11_default: qup-uart11-default {
1874 sec_mi2s_active: sec-mi2s-active {
1881 pri_mi2s_active: pri-mi2s-active {
1888 pri_mi2s_mclk_active: pri-mi2s-mclk-active {
1897 compatible = "qcom,sc7180-mpss-pas";
1899 reg-names = "qdsp6", "rmb";
1901 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
1907 interrupt-names = "wdog", "fatal", "ready", "handover",
1908 "stop-ack", "shutdown-ack";
1916 clock-names = "iface", "bus", "nav", "snoc_axi",
1919 power-domains = <&rpmhpd SC7180_CX>,
1922 power-domain-names = "cx", "mx", "mss";
1924 memory-region = <&mpss_mem>;
1928 qcom,smem-states = <&modem_smp2p_out 0>;
1929 qcom,smem-state-names = "stop";
1933 reset-names = "mss_restart", "pdc_reset";
1935 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
1936 qcom,spare-regs = <&tcsr_regs_2 0xb3e4>;
1940 glink-edge {
1943 qcom,remote-pid = <1>;
1949 compatible = "qcom,adreno-618.0", "qcom,adreno";
1952 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
1955 operating-points-v2 = <&gpu_opp_table>;
1958 #cooling-cells = <2>;
1960 nvmem-cells = <&gpu_speed_bin>;
1961 nvmem-cell-names = "speed_bin";
1964 interconnect-names = "gfx-mem";
1966 gpu_opp_table: opp-table {
1967 compatible = "operating-points-v2";
1969 opp-825000000 {
1970 opp-hz = /bits/ 64 <825000000>;
1971 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1972 opp-peak-kBps = <8532000>;
1973 opp-supported-hw = <0x04>;
1976 opp-800000000 {
1977 opp-hz = /bits/ 64 <800000000>;
1978 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1979 opp-peak-kBps = <8532000>;
1980 opp-supported-hw = <0x07>;
1983 opp-650000000 {
1984 opp-hz = /bits/ 64 <650000000>;
1985 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1986 opp-peak-kBps = <7216000>;
1987 opp-supported-hw = <0x07>;
1990 opp-565000000 {
1991 opp-hz = /bits/ 64 <565000000>;
1992 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1993 opp-peak-kBps = <5412000>;
1994 opp-supported-hw = <0x07>;
1997 opp-430000000 {
1998 opp-hz = /bits/ 64 <430000000>;
1999 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2000 opp-peak-kBps = <5412000>;
2001 opp-supported-hw = <0x07>;
2004 opp-355000000 {
2005 opp-hz = /bits/ 64 <355000000>;
2006 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2007 opp-peak-kBps = <3072000>;
2008 opp-supported-hw = <0x07>;
2011 opp-267000000 {
2012 opp-hz = /bits/ 64 <267000000>;
2013 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2014 opp-peak-kBps = <3072000>;
2015 opp-supported-hw = <0x07>;
2018 opp-180000000 {
2019 opp-hz = /bits/ 64 <180000000>;
2020 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2021 opp-peak-kBps = <1804000>;
2022 opp-supported-hw = <0x07>;
2028 compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2030 #iommu-cells = <1>;
2031 #global-interrupts = <2>;
2045 clock-names = "bus", "iface";
2047 power-domains = <&gpucc CX_GDSC>;
2051 compatible = "qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
2054 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2057 interrupt-names = "hfi", "gmu";
2062 clock-names = "gmu", "cxo", "axi", "memnoc";
2063 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>;
2064 power-domain-names = "cx", "gx";
2066 operating-points-v2 = <&gmu_opp_table>;
2068 gmu_opp_table: opp-table {
2069 compatible = "operating-points-v2";
2071 opp-200000000 {
2072 opp-hz = /bits/ 64 <200000000>;
2073 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2078 gpucc: clock-controller@5090000 {
2079 compatible = "qcom,sc7180-gpucc";
2084 clock-names = "bi_tcxo",
2087 #clock-cells = <1>;
2088 #reset-cells = <1>;
2089 #power-domain-cells = <1>;
2093 compatible = "arm,coresight-stm", "arm,primecell";
2096 reg-names = "stm-base", "stm-stimulus-base";
2099 clock-names = "apb_pclk";
2101 out-ports {
2104 remote-endpoint = <&funnel0_in7>;
2111 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2115 clock-names = "apb_pclk";
2117 out-ports {
2120 remote-endpoint = <&merge_funnel_in0>;
2125 in-ports {
2126 #address-cells = <1>;
2127 #size-cells = <0>;
2132 remote-endpoint = <&stm_out>;
2139 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2143 clock-names = "apb_pclk";
2145 out-ports {
2148 remote-endpoint = <&merge_funnel_in1>;
2153 in-ports {
2154 #address-cells = <1>;
2155 #size-cells = <0>;
2160 remote-endpoint = <&apss_merge_funnel_out>;
2167 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2171 clock-names = "apb_pclk";
2173 out-ports {
2176 remote-endpoint = <&swao_funnel_in>;
2181 in-ports {
2182 #address-cells = <1>;
2183 #size-cells = <0>;
2188 remote-endpoint = <&funnel0_out>;
2195 remote-endpoint = <&funnel1_out>;
2202 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2206 clock-names = "apb_pclk";
2208 out-ports {
2211 remote-endpoint = <&etr_in>;
2216 in-ports {
2219 remote-endpoint = <&swao_replicator_out>;
2226 compatible = "arm,coresight-tmc", "arm,primecell";
2231 clock-names = "apb_pclk";
2232 arm,scatter-gather;
2234 in-ports {
2237 remote-endpoint = <&replicator_out>;
2244 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2248 clock-names = "apb_pclk";
2250 out-ports {
2253 remote-endpoint = <&etf_in>;
2258 in-ports {
2259 #address-cells = <1>;
2260 #size-cells = <0>;
2265 remote-endpoint = <&merge_funnel_out>;
2272 compatible = "arm,coresight-tmc", "arm,primecell";
2276 clock-names = "apb_pclk";
2278 out-ports {
2281 remote-endpoint = <&swao_replicator_in>;
2286 in-ports {
2289 remote-endpoint = <&swao_funnel_out>;
2296 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2300 clock-names = "apb_pclk";
2301 qcom,replicator-loses-context;
2303 out-ports {
2306 remote-endpoint = <&replicator_in>;
2311 in-ports {
2314 remote-endpoint = <&etf_out>;
2321 compatible = "arm,coresight-etm4x", "arm,primecell";
2327 clock-names = "apb_pclk";
2328 arm,coresight-loses-context-with-cpu;
2329 qcom,skip-power-up;
2331 out-ports {
2334 remote-endpoint = <&apss_funnel_in0>;
2341 compatible = "arm,coresight-etm4x", "arm,primecell";
2347 clock-names = "apb_pclk";
2348 arm,coresight-loses-context-with-cpu;
2349 qcom,skip-power-up;
2351 out-ports {
2354 remote-endpoint = <&apss_funnel_in1>;
2361 compatible = "arm,coresight-etm4x", "arm,primecell";
2367 clock-names = "apb_pclk";
2368 arm,coresight-loses-context-with-cpu;
2369 qcom,skip-power-up;
2371 out-ports {
2374 remote-endpoint = <&apss_funnel_in2>;
2381 compatible = "arm,coresight-etm4x", "arm,primecell";
2387 clock-names = "apb_pclk";
2388 arm,coresight-loses-context-with-cpu;
2389 qcom,skip-power-up;
2391 out-ports {
2394 remote-endpoint = <&apss_funnel_in3>;
2401 compatible = "arm,coresight-etm4x", "arm,primecell";
2407 clock-names = "apb_pclk";
2408 arm,coresight-loses-context-with-cpu;
2409 qcom,skip-power-up;
2411 out-ports {
2414 remote-endpoint = <&apss_funnel_in4>;
2421 compatible = "arm,coresight-etm4x", "arm,primecell";
2427 clock-names = "apb_pclk";
2428 arm,coresight-loses-context-with-cpu;
2429 qcom,skip-power-up;
2431 out-ports {
2434 remote-endpoint = <&apss_funnel_in5>;
2441 compatible = "arm,coresight-etm4x", "arm,primecell";
2447 clock-names = "apb_pclk";
2448 arm,coresight-loses-context-with-cpu;
2449 qcom,skip-power-up;
2451 out-ports {
2454 remote-endpoint = <&apss_funnel_in6>;
2461 compatible = "arm,coresight-etm4x", "arm,primecell";
2467 clock-names = "apb_pclk";
2468 arm,coresight-loses-context-with-cpu;
2469 qcom,skip-power-up;
2471 out-ports {
2474 remote-endpoint = <&apss_funnel_in7>;
2481 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2485 clock-names = "apb_pclk";
2487 out-ports {
2490 remote-endpoint = <&apss_merge_funnel_in>;
2495 in-ports {
2496 #address-cells = <1>;
2497 #size-cells = <0>;
2502 remote-endpoint = <&etm0_out>;
2509 remote-endpoint = <&etm1_out>;
2516 remote-endpoint = <&etm2_out>;
2523 remote-endpoint = <&etm3_out>;
2530 remote-endpoint = <&etm4_out>;
2537 remote-endpoint = <&etm5_out>;
2544 remote-endpoint = <&etm6_out>;
2551 remote-endpoint = <&etm7_out>;
2558 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2562 clock-names = "apb_pclk";
2564 out-ports {
2567 remote-endpoint = <&funnel1_in4>;
2572 in-ports {
2575 remote-endpoint = <&apss_funnel_out>;
2582 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
2588 interrupt-names = "hc_irq", "pwr_irq";
2593 clock-names = "iface", "core", "xo";
2597 interconnect-names = "sdhc-ddr","cpu-sdhc";
2598 power-domains = <&rpmhpd SC7180_CX>;
2599 operating-points-v2 = <&sdhc2_opp_table>;
2601 bus-width = <4>;
2605 sdhc2_opp_table: opp-table {
2606 compatible = "operating-points-v2";
2608 opp-100000000 {
2609 opp-hz = /bits/ 64 <100000000>;
2610 required-opps = <&rpmhpd_opp_low_svs>;
2611 opp-peak-kBps = <1800000 600000>;
2612 opp-avg-kBps = <100000 0>;
2615 opp-202000000 {
2616 opp-hz = /bits/ 64 <202000000>;
2617 required-opps = <&rpmhpd_opp_nom>;
2618 opp-peak-kBps = <5400000 1600000>;
2619 opp-avg-kBps = <200000 0>;
2624 qspi_opp_table: opp-table-qspi {
2625 compatible = "operating-points-v2";
2627 opp-75000000 {
2628 opp-hz = /bits/ 64 <75000000>;
2629 required-opps = <&rpmhpd_opp_low_svs>;
2632 opp-150000000 {
2633 opp-hz = /bits/ 64 <150000000>;
2634 required-opps = <&rpmhpd_opp_svs>;
2637 opp-300000000 {
2638 opp-hz = /bits/ 64 <300000000>;
2639 required-opps = <&rpmhpd_opp_nom>;
2644 compatible = "qcom,sc7180-qspi", "qcom,qspi-v1";
2646 #address-cells = <1>;
2647 #size-cells = <0>;
2651 clock-names = "iface", "core";
2654 interconnect-names = "qspi-config";
2655 power-domains = <&rpmhpd SC7180_CX>;
2656 operating-points-v2 = <&qspi_opp_table>;
2661 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy";
2664 #phy-cells = <0>;
2667 clock-names = "cfg_ahb", "ref";
2670 nvmem-cells = <&qusb2p_hstx_trim>;
2673 usb_1_qmpphy: phy-wrapper@88e9000 {
2674 compatible = "qcom,sc7180-qmp-usb3-dp-phy";
2679 #address-cells = <2>;
2680 #size-cells = <2>;
2687 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
2691 reset-names = "phy", "common";
2693 usb_1_ssphy: usb3-phy@88e9200 {
2700 #clock-cells = <0>;
2701 #phy-cells = <0>;
2703 clock-names = "pipe0";
2704 clock-output-names = "usb3_phy_pipe_clk_src";
2707 dp_phy: dp-phy@88ea200 {
2713 #clock-cells = <1>;
2714 #phy-cells = <0>;
2719 compatible = "qcom,sc7180-dc-noc";
2721 #interconnect-cells = <2>;
2722 qcom,bcm-voters = <&apps_bcm_voter>;
2725 system-cache-controller@9200000 {
2726 compatible = "qcom,sc7180-llcc";
2728 reg-names = "llcc_base", "llcc_broadcast_base";
2733 compatible = "qcom,sc7180-gem-noc";
2735 #interconnect-cells = <2>;
2736 qcom,bcm-voters = <&apps_bcm_voter>;
2740 compatible = "qcom,sc7180-npu-noc";
2742 #interconnect-cells = <2>;
2743 qcom,bcm-voters = <&apps_bcm_voter>;
2747 compatible = "qcom,sc7180-dwc3", "qcom,dwc3";
2750 #address-cells = <2>;
2751 #size-cells = <2>;
2753 dma-ranges;
2760 clock-names = "cfg_noc",
2766 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2768 assigned-clock-rates = <19200000>, <150000000>;
2770 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2774 interrupt-names = "hs_phy_irq", "ss_phy_irq",
2777 power-domains = <&gcc USB30_PRIM_GDSC>;
2783 interconnect-names = "usb-ddr", "apps-usb";
2793 phy-names = "usb2-phy", "usb3-phy";
2794 maximum-speed = "super-speed";
2798 venus: video-codec@aa00000 {
2799 compatible = "qcom,sc7180-venus";
2802 power-domains = <&videocc VENUS_GDSC>,
2805 power-domain-names = "venus", "vcodec0", "cx";
2806 operating-points-v2 = <&venus_opp_table>;
2812 clock-names = "core", "iface", "bus",
2815 memory-region = <&venus_mem>;
2818 interconnect-names = "video-mem", "cpu-cfg";
2820 video-decoder {
2821 compatible = "venus-decoder";
2824 video-encoder {
2825 compatible = "venus-encoder";
2828 venus_opp_table: opp-table {
2829 compatible = "operating-points-v2";
2831 opp-150000000 {
2832 opp-hz = /bits/ 64 <150000000>;
2833 required-opps = <&rpmhpd_opp_low_svs>;
2836 opp-270000000 {
2837 opp-hz = /bits/ 64 <270000000>;
2838 required-opps = <&rpmhpd_opp_svs>;
2841 opp-340000000 {
2842 opp-hz = /bits/ 64 <340000000>;
2843 required-opps = <&rpmhpd_opp_svs_l1>;
2846 opp-434000000 {
2847 opp-hz = /bits/ 64 <434000000>;
2848 required-opps = <&rpmhpd_opp_nom>;
2851 opp-500000097 {
2852 opp-hz = /bits/ 64 <500000097>;
2853 required-opps = <&rpmhpd_opp_turbo>;
2858 videocc: clock-controller@ab00000 {
2859 compatible = "qcom,sc7180-videocc";
2862 clock-names = "bi_tcxo";
2863 #clock-cells = <1>;
2864 #reset-cells = <1>;
2865 #power-domain-cells = <1>;
2869 compatible = "qcom,sc7180-camnoc-virt";
2871 #interconnect-cells = <2>;
2872 qcom,bcm-voters = <&apps_bcm_voter>;
2875 camcc: clock-controller@ad00000 {
2876 compatible = "qcom,sc7180-camcc";
2881 clock-names = "bi_tcxo", "iface", "xo";
2882 #clock-cells = <1>;
2883 #reset-cells = <1>;
2884 #power-domain-cells = <1>;
2888 compatible = "qcom,sc7180-mdss";
2890 reg-names = "mdss";
2892 power-domains = <&dispcc MDSS_GDSC>;
2897 clock-names = "iface", "ahb", "core";
2900 interrupt-controller;
2901 #interrupt-cells = <1>;
2904 interconnect-names = "mdp0-mem";
2908 #address-cells = <2>;
2909 #size-cells = <2>;
2914 mdp: display-controller@ae01000 {
2915 compatible = "qcom,sc7180-dpu";
2918 reg-names = "mdp", "vbif";
2926 clock-names = "bus", "iface", "rot", "lut", "core",
2928 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
2931 assigned-clock-rates = <19200000>,
2934 operating-points-v2 = <&mdp_opp_table>;
2935 power-domains = <&rpmhpd SC7180_CX>;
2937 interrupt-parent = <&mdss>;
2943 #address-cells = <1>;
2944 #size-cells = <0>;
2949 remote-endpoint = <&dsi0_in>;
2956 remote-endpoint = <&dp_in>;
2961 mdp_opp_table: opp-table {
2962 compatible = "operating-points-v2";
2964 opp-200000000 {
2965 opp-hz = /bits/ 64 <200000000>;
2966 required-opps = <&rpmhpd_opp_low_svs>;
2969 opp-300000000 {
2970 opp-hz = /bits/ 64 <300000000>;
2971 required-opps = <&rpmhpd_opp_svs>;
2974 opp-345000000 {
2975 opp-hz = /bits/ 64 <345000000>;
2976 required-opps = <&rpmhpd_opp_svs_l1>;
2979 opp-460000000 {
2980 opp-hz = /bits/ 64 <460000000>;
2981 required-opps = <&rpmhpd_opp_nom>;
2988 compatible = "qcom,mdss-dsi-ctrl";
2990 reg-names = "dsi_ctrl";
2992 interrupt-parent = <&mdss>;
3001 clock-names = "byte",
3008 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3009 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
3011 operating-points-v2 = <&dsi_opp_table>;
3012 power-domains = <&rpmhpd SC7180_CX>;
3015 phy-names = "dsi";
3017 #address-cells = <1>;
3018 #size-cells = <0>;
3023 #address-cells = <1>;
3024 #size-cells = <0>;
3029 remote-endpoint = <&dpu_intf1_out>;
3040 dsi_opp_table: opp-table {
3041 compatible = "operating-points-v2";
3043 opp-187500000 {
3044 opp-hz = /bits/ 64 <187500000>;
3045 required-opps = <&rpmhpd_opp_low_svs>;
3048 opp-300000000 {
3049 opp-hz = /bits/ 64 <300000000>;
3050 required-opps = <&rpmhpd_opp_svs>;
3053 opp-358000000 {
3054 opp-hz = /bits/ 64 <358000000>;
3055 required-opps = <&rpmhpd_opp_svs_l1>;
3060 dsi_phy: dsi-phy@ae94400 {
3061 compatible = "qcom,dsi-phy-10nm";
3065 reg-names = "dsi_phy",
3069 #clock-cells = <1>;
3070 #phy-cells = <0>;
3074 clock-names = "iface", "ref";
3079 mdss_dp: displayport-controller@ae90000 {
3080 compatible = "qcom,sc7180-dp";
3089 interrupt-parent = <&mdss>;
3097 clock-names = "core_iface", "core_aux", "ctrl_link",
3099 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
3101 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
3103 phy-names = "dp";
3105 operating-points-v2 = <&dp_opp_table>;
3106 power-domains = <&rpmhpd SC7180_CX>;
3108 #sound-dai-cells = <0>;
3111 #address-cells = <1>;
3112 #size-cells = <0>;
3116 remote-endpoint = <&dpu_intf0_out>;
3126 dp_opp_table: opp-table {
3127 compatible = "operating-points-v2";
3129 opp-160000000 {
3130 opp-hz = /bits/ 64 <160000000>;
3131 required-opps = <&rpmhpd_opp_low_svs>;
3134 opp-270000000 {
3135 opp-hz = /bits/ 64 <270000000>;
3136 required-opps = <&rpmhpd_opp_svs>;
3139 opp-540000000 {
3140 opp-hz = /bits/ 64 <540000000>;
3141 required-opps = <&rpmhpd_opp_svs_l1>;
3144 opp-810000000 {
3145 opp-hz = /bits/ 64 <810000000>;
3146 required-opps = <&rpmhpd_opp_nom>;
3152 dispcc: clock-controller@af00000 {
3153 compatible = "qcom,sc7180-dispcc";
3161 clock-names = "bi_tcxo",
3167 #clock-cells = <1>;
3168 #reset-cells = <1>;
3169 #power-domain-cells = <1>;
3172 pdc: interrupt-controller@b220000 {
3173 compatible = "qcom,sc7180-pdc", "qcom,pdc";
3175 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
3176 #interrupt-cells = <2>;
3177 interrupt-parent = <&intc>;
3178 interrupt-controller;
3181 pdc_reset: reset-controller@b2e0000 {
3182 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global";
3184 #reset-cells = <1>;
3187 tsens0: thermal-sensor@c263000 {
3188 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3194 interrupt-names = "uplow","critical";
3195 #thermal-sensor-cells = <1>;
3198 tsens1: thermal-sensor@c265000 {
3199 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3205 interrupt-names = "uplow","critical";
3206 #thermal-sensor-cells = <1>;
3209 aoss_reset: reset-controller@c2a0000 {
3210 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc";
3212 #reset-cells = <1>;
3215 aoss_qmp: power-controller@c300000 {
3216 compatible = "qcom,sc7180-aoss-qmp", "qcom,aoss-qmp";
3221 #clock-cells = <0>;
3225 compatible = "qcom,rpmh-stats";
3230 compatible = "qcom,spmi-pmic-arb";
3236 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3237 interrupt-names = "periph_irq";
3238 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3241 #address-cells = <1>;
3242 #size-cells = <1>;
3243 interrupt-controller;
3244 #interrupt-cells = <4>;
3245 cell-index = <0>;
3249 compatible = "qcom,sc7180-imem", "syscon", "simple-mfd";
3252 #address-cells = <1>;
3253 #size-cells = <1>;
3257 pil-reloc@94c {
3258 compatible = "qcom,pil-reloc-info";
3264 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
3266 #iommu-cells = <2>;
3267 #global-interrupts = <1>;
3351 intc: interrupt-controller@17a00000 {
3352 compatible = "arm,gic-v3";
3353 #address-cells = <2>;
3354 #size-cells = <2>;
3356 #interrupt-cells = <3>;
3357 interrupt-controller;
3362 msi-controller@17a40000 {
3363 compatible = "arm,gic-v3-its";
3364 msi-controller;
3365 #msi-cells = <1>;
3372 compatible = "qcom,sc7180-apss-shared";
3374 #mbox-cells = <1>;
3378 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
3385 #address-cells = <1>;
3386 #size-cells = <1>;
3388 compatible = "arm,armv7-timer-mem";
3392 frame-number = <0>;
3400 frame-number = <1>;
3407 frame-number = <2>;
3414 frame-number = <3>;
3421 frame-number = <4>;
3428 frame-number = <5>;
3435 frame-number = <6>;
3443 compatible = "qcom,rpmh-rsc";
3447 reg-names = "drv-0", "drv-1", "drv-2";
3451 qcom,tcs-offset = <0xd00>;
3452 qcom,drv-id = <2>;
3453 qcom,tcs-config = <ACTIVE_TCS 2>,
3458 rpmhcc: clock-controller {
3459 compatible = "qcom,sc7180-rpmh-clk";
3461 clock-names = "xo";
3462 #clock-cells = <1>;
3465 rpmhpd: power-controller {
3466 compatible = "qcom,sc7180-rpmhpd";
3467 #power-domain-cells = <1>;
3468 operating-points-v2 = <&rpmhpd_opp_table>;
3470 rpmhpd_opp_table: opp-table {
3471 compatible = "operating-points-v2";
3474 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3478 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3482 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3486 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3490 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3494 opp-level = <224>;
3498 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3502 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3506 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3510 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3514 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3519 apps_bcm_voter: bcm-voter {
3520 compatible = "qcom,bcm-voter";
3525 compatible = "qcom,sc7180-osm-l3";
3529 clock-names = "xo", "alternate";
3531 #interconnect-cells = <1>;
3535 compatible = "qcom,cpufreq-hw";
3537 reg-names = "freq-domain0", "freq-domain1";
3540 clock-names = "xo", "alternate";
3542 #freq-domain-cells = <1>;
3546 compatible = "qcom,wcn3990-wifi";
3548 reg-names = "membase";
3563 memory-region = <&wlan_mem>;
3564 qcom,msa-fixed-perm;
3568 lpasscc: clock-controller@62d00000 {
3569 compatible = "qcom,sc7180-lpasscorecc";
3572 reg-names = "lpass_core_cc", "lpass_audio_cc";
3575 clock-names = "iface", "bi_tcxo";
3576 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3577 #clock-cells = <1>;
3578 #power-domain-cells = <1>;
3582 compatible = "qcom,sc7180-lpass-cpu";
3585 reg-names = "lpass-hdmiif", "lpass-lpaif";
3591 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3602 clock-names = "pcnoc-sway-clk", "audio-core",
3603 "mclk0", "pcnoc-mport-clk",
3604 "mi2s-bit-clk0", "mi2s-bit-clk1";
3607 #sound-dai-cells = <1>;
3608 #address-cells = <1>;
3609 #size-cells = <0>;
3613 interrupt-names = "lpass-irq-lpaif", "lpass-irq-hdmi";
3616 lpass_hm: clock-controller@63000000 {
3617 compatible = "qcom,sc7180-lpasshm";
3621 clock-names = "iface", "bi_tcxo";
3622 #clock-cells = <1>;
3623 #power-domain-cells = <1>;
3627 thermal-zones {
3628 cpu0_thermal: cpu0-thermal {
3629 polling-delay-passive = <250>;
3630 polling-delay = <0>;
3632 thermal-sensors = <&tsens0 1>;
3633 sustainable-power = <1052>;
3636 cpu0_alert0: trip-point0 {
3642 cpu0_alert1: trip-point1 {
3655 cooling-maps {
3658 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3667 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3677 cpu1_thermal: cpu1-thermal {
3678 polling-delay-passive = <250>;
3679 polling-delay = <0>;
3681 thermal-sensors = <&tsens0 2>;
3682 sustainable-power = <1052>;
3685 cpu1_alert0: trip-point0 {
3691 cpu1_alert1: trip-point1 {
3704 cooling-maps {
3707 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3716 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3726 cpu2_thermal: cpu2-thermal {
3727 polling-delay-passive = <250>;
3728 polling-delay = <0>;
3730 thermal-sensors = <&tsens0 3>;
3731 sustainable-power = <1052>;
3734 cpu2_alert0: trip-point0 {
3740 cpu2_alert1: trip-point1 {
3753 cooling-maps {
3756 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3765 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3775 cpu3_thermal: cpu3-thermal {
3776 polling-delay-passive = <250>;
3777 polling-delay = <0>;
3779 thermal-sensors = <&tsens0 4>;
3780 sustainable-power = <1052>;
3783 cpu3_alert0: trip-point0 {
3789 cpu3_alert1: trip-point1 {
3802 cooling-maps {
3805 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3814 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3824 cpu4_thermal: cpu4-thermal {
3825 polling-delay-passive = <250>;
3826 polling-delay = <0>;
3828 thermal-sensors = <&tsens0 5>;
3829 sustainable-power = <1052>;
3832 cpu4_alert0: trip-point0 {
3838 cpu4_alert1: trip-point1 {
3851 cooling-maps {
3854 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3863 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3873 cpu5_thermal: cpu5-thermal {
3874 polling-delay-passive = <250>;
3875 polling-delay = <0>;
3877 thermal-sensors = <&tsens0 6>;
3878 sustainable-power = <1052>;
3881 cpu5_alert0: trip-point0 {
3887 cpu5_alert1: trip-point1 {
3900 cooling-maps {
3903 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3912 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3922 cpu6_thermal: cpu6-thermal {
3923 polling-delay-passive = <250>;
3924 polling-delay = <0>;
3926 thermal-sensors = <&tsens0 9>;
3927 sustainable-power = <1425>;
3930 cpu6_alert0: trip-point0 {
3936 cpu6_alert1: trip-point1 {
3949 cooling-maps {
3952 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3957 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3963 cpu7_thermal: cpu7-thermal {
3964 polling-delay-passive = <250>;
3965 polling-delay = <0>;
3967 thermal-sensors = <&tsens0 10>;
3968 sustainable-power = <1425>;
3971 cpu7_alert0: trip-point0 {
3977 cpu7_alert1: trip-point1 {
3990 cooling-maps {
3993 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3998 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4004 cpu8_thermal: cpu8-thermal {
4005 polling-delay-passive = <250>;
4006 polling-delay = <0>;
4008 thermal-sensors = <&tsens0 11>;
4009 sustainable-power = <1425>;
4012 cpu8_alert0: trip-point0 {
4018 cpu8_alert1: trip-point1 {
4031 cooling-maps {
4034 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4039 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4045 cpu9_thermal: cpu9-thermal {
4046 polling-delay-passive = <250>;
4047 polling-delay = <0>;
4049 thermal-sensors = <&tsens0 12>;
4050 sustainable-power = <1425>;
4053 cpu9_alert0: trip-point0 {
4059 cpu9_alert1: trip-point1 {
4072 cooling-maps {
4075 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4080 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4086 aoss0-thermal {
4087 polling-delay-passive = <250>;
4088 polling-delay = <0>;
4090 thermal-sensors = <&tsens0 0>;
4093 aoss0_alert0: trip-point0 {
4107 cpuss0-thermal {
4108 polling-delay-passive = <250>;
4109 polling-delay = <0>;
4111 thermal-sensors = <&tsens0 7>;
4114 cpuss0_alert0: trip-point0 {
4127 cpuss1-thermal {
4128 polling-delay-passive = <250>;
4129 polling-delay = <0>;
4131 thermal-sensors = <&tsens0 8>;
4134 cpuss1_alert0: trip-point0 {
4147 gpuss0-thermal {
4148 polling-delay-passive = <250>;
4149 polling-delay = <0>;
4151 thermal-sensors = <&tsens0 13>;
4154 gpuss0_alert0: trip-point0 {
4167 cooling-maps {
4170 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4175 gpuss1-thermal {
4176 polling-delay-passive = <250>;
4177 polling-delay = <0>;
4179 thermal-sensors = <&tsens0 14>;
4182 gpuss1_alert0: trip-point0 {
4195 cooling-maps {
4198 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4203 aoss1-thermal {
4204 polling-delay-passive = <250>;
4205 polling-delay = <0>;
4207 thermal-sensors = <&tsens1 0>;
4210 aoss1_alert0: trip-point0 {
4224 cwlan-thermal {
4225 polling-delay-passive = <250>;
4226 polling-delay = <0>;
4228 thermal-sensors = <&tsens1 1>;
4231 cwlan_alert0: trip-point0 {
4245 audio-thermal {
4246 polling-delay-passive = <250>;
4247 polling-delay = <0>;
4249 thermal-sensors = <&tsens1 2>;
4252 audio_alert0: trip-point0 {
4266 ddr-thermal {
4267 polling-delay-passive = <250>;
4268 polling-delay = <0>;
4270 thermal-sensors = <&tsens1 3>;
4273 ddr_alert0: trip-point0 {
4287 q6-hvx-thermal {
4288 polling-delay-passive = <250>;
4289 polling-delay = <0>;
4291 thermal-sensors = <&tsens1 4>;
4294 q6_hvx_alert0: trip-point0 {
4308 camera-thermal {
4309 polling-delay-passive = <250>;
4310 polling-delay = <0>;
4312 thermal-sensors = <&tsens1 5>;
4315 camera_alert0: trip-point0 {
4329 mdm-core-thermal {
4330 polling-delay-passive = <250>;
4331 polling-delay = <0>;
4333 thermal-sensors = <&tsens1 6>;
4336 mdm_alert0: trip-point0 {
4350 mdm-dsp-thermal {
4351 polling-delay-passive = <250>;
4352 polling-delay = <0>;
4354 thermal-sensors = <&tsens1 7>;
4357 mdm_dsp_alert0: trip-point0 {
4371 npu-thermal {
4372 polling-delay-passive = <250>;
4373 polling-delay = <0>;
4375 thermal-sensors = <&tsens1 8>;
4378 npu_alert0: trip-point0 {
4392 video-thermal {
4393 polling-delay-passive = <250>;
4394 polling-delay = <0>;
4396 thermal-sensors = <&tsens1 9>;
4399 video_alert0: trip-point0 {
4415 compatible = "arm,armv8-timer";