Lines Matching +full:0 +full:x62d87000
61 #clock-cells = <0>;
67 #clock-cells = <0>;
77 reg = <0x0 0x80000000 0x0 0x600000>;
82 reg = <0x0 0x80600000 0x0 0x200000>;
87 reg = <0x0 0x80800000 0x0 0x20000>;
92 reg = <0x0 0x80820000 0x0 0x20000>;
98 reg = <0x0 0x808ff000 0x0 0x1000>;
103 reg = <0x0 0x80900000 0x0 0x200000>;
108 reg = <0x0 0x80b00000 0x0 0x3900000>;
113 reg = <0 0x8b700000 0 0x10000>;
119 reg = <0x0 0x94600000 0x0 0x200000>;
129 #size-cells = <0>;
131 CPU0: cpu@0 {
134 reg = <0x0 0x0>;
146 qcom,freq-domain = <&cpufreq_hw 0>;
159 reg = <0x0 0x100>;
171 qcom,freq-domain = <&cpufreq_hw 0>;
181 reg = <0x0 0x200>;
193 qcom,freq-domain = <&cpufreq_hw 0>;
203 reg = <0x0 0x300>;
215 qcom,freq-domain = <&cpufreq_hw 0>;
225 reg = <0x0 0x400>;
237 qcom,freq-domain = <&cpufreq_hw 0>;
247 reg = <0x0 0x500>;
259 qcom,freq-domain = <&cpufreq_hw 0>;
269 reg = <0x0 0x600>;
291 reg = <0x0 0x700>;
349 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
352 arm,psci-suspend-param = <0x40000003>;
359 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
362 arm,psci-suspend-param = <0x40000004>;
369 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
372 arm,psci-suspend-param = <0x40000003>;
382 arm,psci-suspend-param = <0x40000004>;
389 CLUSTER_SLEEP_0: cluster-sleep-0 {
392 arm,psci-suspend-param = <0x40003444>;
544 reg = <0 0x80000000 0 0>;
572 qcom,local-pid = <0>;
596 qcom,local-pid = <0>;
617 qcom,local-pid = <0>;
648 soc: soc@0 {
651 ranges = <0 0 0 0 0x10 0>;
652 dma-ranges = <0 0 0 0 0x10 0>;
657 reg = <0 0x00100000 0 0x1f0000>;
669 reg = <0 0x00784000 0 0x7a0>,
670 <0 0x00780000 0 0x7a0>,
671 <0 0x00782000 0 0x100>,
672 <0 0x00786000 0 0x1fff>;
680 reg = <0x25b 0x1>;
685 reg = <0x1d2 0x2>;
692 reg = <0 0x7c4000 0 0x1000>,
693 <0 0x07c5000 0 0x1000>;
696 iommus = <&apps_smmu 0x60 0x0>;
705 interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>,
706 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>;
729 opp-avg-kBps = <100000 0>;
736 opp-avg-kBps = <390000 0>;
762 reg = <0 0x008c0000 0 0x6000>;
769 iommus = <&apps_smmu 0x43 0x0>;
774 reg = <0 0x00880000 0 0x4000>;
778 pinctrl-0 = <&qup_i2c0_default>;
781 #size-cells = <0>;
782 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
783 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
784 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
794 reg = <0 0x00880000 0 0x4000>;
798 pinctrl-0 = <&qup_spi0_default>;
801 #size-cells = <0>;
804 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
805 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
812 reg = <0 0x00880000 0 0x4000>;
816 pinctrl-0 = <&qup_uart0_default>;
820 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
821 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
828 reg = <0 0x00884000 0 0x4000>;
832 pinctrl-0 = <&qup_i2c1_default>;
835 #size-cells = <0>;
836 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
837 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
838 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
848 reg = <0 0x00884000 0 0x4000>;
852 pinctrl-0 = <&qup_spi1_default>;
855 #size-cells = <0>;
858 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
859 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
866 reg = <0 0x00884000 0 0x4000>;
870 pinctrl-0 = <&qup_uart1_default>;
874 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
875 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
882 reg = <0 0x00888000 0 0x4000>;
886 pinctrl-0 = <&qup_i2c2_default>;
889 #size-cells = <0>;
890 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
891 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
892 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
902 reg = <0 0x00888000 0 0x4000>;
906 pinctrl-0 = <&qup_uart2_default>;
910 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
911 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
918 reg = <0 0x0088c000 0 0x4000>;
922 pinctrl-0 = <&qup_i2c3_default>;
925 #size-cells = <0>;
926 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
927 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
928 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
938 reg = <0 0x0088c000 0 0x4000>;
942 pinctrl-0 = <&qup_spi3_default>;
945 #size-cells = <0>;
948 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
949 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
956 reg = <0 0x0088c000 0 0x4000>;
960 pinctrl-0 = <&qup_uart3_default>;
964 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
965 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
972 reg = <0 0x00890000 0 0x4000>;
976 pinctrl-0 = <&qup_i2c4_default>;
979 #size-cells = <0>;
980 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
981 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
982 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
992 reg = <0 0x00890000 0 0x4000>;
996 pinctrl-0 = <&qup_uart4_default>;
1000 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1001 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1008 reg = <0 0x00894000 0 0x4000>;
1012 pinctrl-0 = <&qup_i2c5_default>;
1015 #size-cells = <0>;
1016 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1017 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1018 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1028 reg = <0 0x00894000 0 0x4000>;
1032 pinctrl-0 = <&qup_spi5_default>;
1035 #size-cells = <0>;
1038 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1039 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1046 reg = <0 0x00894000 0 0x4000>;
1050 pinctrl-0 = <&qup_uart5_default>;
1054 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1055 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1063 reg = <0 0x00ac0000 0 0x6000>;
1070 iommus = <&apps_smmu 0x4c3 0x0>;
1075 reg = <0 0x00a80000 0 0x4000>;
1079 pinctrl-0 = <&qup_i2c6_default>;
1082 #size-cells = <0>;
1083 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1084 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1085 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1095 reg = <0 0x00a80000 0 0x4000>;
1099 pinctrl-0 = <&qup_spi6_default>;
1102 #size-cells = <0>;
1105 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1106 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1113 reg = <0 0x00a80000 0 0x4000>;
1117 pinctrl-0 = <&qup_uart6_default>;
1121 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1122 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1129 reg = <0 0x00a84000 0 0x4000>;
1133 pinctrl-0 = <&qup_i2c7_default>;
1136 #size-cells = <0>;
1137 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1138 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1139 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1149 reg = <0 0x00a84000 0 0x4000>;
1153 pinctrl-0 = <&qup_uart7_default>;
1157 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1158 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1165 reg = <0 0x00a88000 0 0x4000>;
1169 pinctrl-0 = <&qup_i2c8_default>;
1172 #size-cells = <0>;
1173 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1174 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1175 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1185 reg = <0 0x00a88000 0 0x4000>;
1189 pinctrl-0 = <&qup_spi8_default>;
1192 #size-cells = <0>;
1195 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1196 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1203 reg = <0 0x00a88000 0 0x4000>;
1207 pinctrl-0 = <&qup_uart8_default>;
1211 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1212 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1219 reg = <0 0x00a8c000 0 0x4000>;
1223 pinctrl-0 = <&qup_i2c9_default>;
1226 #size-cells = <0>;
1227 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1228 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1229 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1239 reg = <0 0x00a8c000 0 0x4000>;
1243 pinctrl-0 = <&qup_uart9_default>;
1247 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1248 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1255 reg = <0 0x00a90000 0 0x4000>;
1259 pinctrl-0 = <&qup_i2c10_default>;
1262 #size-cells = <0>;
1263 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1264 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1265 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1275 reg = <0 0x00a90000 0 0x4000>;
1279 pinctrl-0 = <&qup_spi10_default>;
1282 #size-cells = <0>;
1285 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1286 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1293 reg = <0 0x00a90000 0 0x4000>;
1297 pinctrl-0 = <&qup_uart10_default>;
1301 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1302 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1309 reg = <0 0x00a94000 0 0x4000>;
1313 pinctrl-0 = <&qup_i2c11_default>;
1316 #size-cells = <0>;
1317 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1318 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1319 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1329 reg = <0 0x00a94000 0 0x4000>;
1333 pinctrl-0 = <&qup_spi11_default>;
1336 #size-cells = <0>;
1339 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1340 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1347 reg = <0 0x00a94000 0 0x4000>;
1351 pinctrl-0 = <&qup_uart11_default>;
1355 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1356 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1364 reg = <0 0x01500000 0 0x28000>;
1371 reg = <0 0x01620000 0 0x17080>;
1378 reg = <0 0x01638000 0 0x1000>;
1385 reg = <0 0x01650000 0 0x1000>;
1392 reg = <0 0x016e0000 0 0x15080>;
1399 reg = <0 0x01705000 0 0x9000>;
1406 reg = <0 0x0170e000 0 0x6000>;
1413 reg = <0 0x01740000 0 0x1c100>;
1421 iommus = <&apps_smmu 0x440 0x0>,
1422 <&apps_smmu 0x442 0x0>;
1423 reg = <0 0x1e40000 0 0x7000>,
1424 <0 0x1e47000 0 0x2000>,
1425 <0 0x1e04000 0 0x2c000>;
1432 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1442 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
1443 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
1444 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
1451 qcom,smem-states = <&ipa_smp2p_out 0>,
1461 reg = <0 0x01f40000 0 0x20000>;
1467 reg = <0 0x01f60000 0 0x20000>;
1472 reg = <0 0x01fc0000 0 0x40000>;
1477 reg = <0 0x03500000 0 0x300000>,
1478 <0 0x03900000 0 0x300000>,
1479 <0 0x03d00000 0 0x300000>;
1486 gpio-ranges = <&tlmm 0 0 120>;
1898 reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>;
1902 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1928 qcom,smem-states = <&modem_smp2p_out 0>;
1935 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
1936 qcom,spare-regs = <&tcsr_regs_2 0xb3e4>;
1950 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>,
1951 <0 0x05061000 0 0x800>;
1954 iommus = <&adreno_smmu 0>;
1963 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
1973 opp-supported-hw = <0x04>;
1980 opp-supported-hw = <0x07>;
1987 opp-supported-hw = <0x07>;
1994 opp-supported-hw = <0x07>;
2001 opp-supported-hw = <0x07>;
2008 opp-supported-hw = <0x07>;
2015 opp-supported-hw = <0x07>;
2022 opp-supported-hw = <0x07>;
2029 reg = <0 0x05040000 0 0x10000>;
2052 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>,
2053 <0 0x0b490000 0 0x10000>;
2080 reg = <0 0x05090000 0 0x9000>;
2094 reg = <0 0x06002000 0 0x1000>,
2095 <0 0x16280000 0 0x180000>;
2112 reg = <0 0x06041000 0 0x1000>;
2127 #size-cells = <0>;
2140 reg = <0 0x06042000 0 0x1000>;
2155 #size-cells = <0>;
2168 reg = <0 0x06045000 0 0x1000>;
2183 #size-cells = <0>;
2185 port@0 {
2186 reg = <0>;
2203 reg = <0 0x06046000 0 0x1000>;
2227 reg = <0 0x06048000 0 0x1000>;
2228 iommus = <&apps_smmu 0x04a0 0x20>;
2245 reg = <0 0x06b04000 0 0x1000>;
2260 #size-cells = <0>;
2273 reg = <0 0x06b05000 0 0x1000>;
2297 reg = <0 0x06b06000 0 0x1000>;
2322 reg = <0 0x07040000 0 0x1000>;
2342 reg = <0 0x07140000 0 0x1000>;
2362 reg = <0 0x07240000 0 0x1000>;
2382 reg = <0 0x07340000 0 0x1000>;
2402 reg = <0 0x07440000 0 0x1000>;
2422 reg = <0 0x07540000 0 0x1000>;
2442 reg = <0 0x07640000 0 0x1000>;
2462 reg = <0 0x07740000 0 0x1000>;
2482 reg = <0 0x07800000 0 0x1000>;
2497 #size-cells = <0>;
2499 port@0 {
2500 reg = <0>;
2559 reg = <0 0x07810000 0 0x1000>;
2583 reg = <0 0x08804000 0 0x1000>;
2585 iommus = <&apps_smmu 0x80 0>;
2595 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2596 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2612 opp-avg-kBps = <100000 0>;
2619 opp-avg-kBps = <200000 0>;
2645 reg = <0 0x088dc000 0 0x600>;
2647 #size-cells = <0>;
2652 interconnects = <&gem_noc MASTER_APPSS_PROC 0
2653 &config_noc SLAVE_QSPI_0 0>;
2662 reg = <0 0x088e3000 0 0x400>;
2664 #phy-cells = <0>;
2675 reg = <0 0x088e9000 0 0x18c>,
2676 <0 0x088e8000 0 0x3c>,
2677 <0 0x088ea000 0 0x18c>;
2694 reg = <0 0x088e9200 0 0x128>,
2695 <0 0x088e9400 0 0x200>,
2696 <0 0x088e9c00 0 0x218>,
2697 <0 0x088e9600 0 0x128>,
2698 <0 0x088e9800 0 0x200>,
2699 <0 0x088e9a00 0 0x18>;
2700 #clock-cells = <0>;
2701 #phy-cells = <0>;
2708 reg = <0 0x088ea200 0 0x200>,
2709 <0 0x088ea400 0 0x200>,
2710 <0 0x088eaa00 0 0x200>,
2711 <0 0x088ea600 0 0x200>,
2712 <0 0x088ea800 0 0x200>;
2714 #phy-cells = <0>;
2720 reg = <0 0x09160000 0 0x03200>;
2727 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
2734 reg = <0 0x09680000 0 0x3e200>;
2741 reg = <0 0x09990000 0 0x1600>;
2748 reg = <0 0x0a6f8800 0 0x400>;
2781 interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>,
2782 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>;
2787 reg = <0 0x0a600000 0 0xe000>;
2789 iommus = <&apps_smmu 0x540 0>;
2800 reg = <0 0x0aa00000 0 0xff000>;
2814 iommus = <&apps_smmu 0x0c00 0x60>;
2816 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>,
2817 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
2860 reg = <0 0x0ab00000 0 0x10000>;
2870 reg = <0 0x0ac00000 0 0x1000>;
2877 reg = <0 0x0ad00000 0 0x10000>;
2889 reg = <0 0x0ae00000 0 0x1000>;
2903 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
2906 iommus = <&apps_smmu 0x800 0x2>;
2916 reg = <0 0x0ae01000 0 0x8f000>,
2917 <0 0x0aeb0000 0 0x2008>;
2938 interrupts = <0>;
2944 #size-cells = <0>;
2946 port@0 {
2947 reg = <0>;
2989 reg = <0 0x0ae94000 0 0x400>;
3009 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
3018 #size-cells = <0>;
3024 #size-cells = <0>;
3026 port@0 {
3027 reg = <0>;
3062 reg = <0 0x0ae94400 0 0x200>,
3063 <0 0x0ae94600 0 0x280>,
3064 <0 0x0ae94a00 0 0x1e0>;
3070 #phy-cells = <0>;
3083 reg = <0 0xae90000 0 0x200>,
3084 <0 0xae90200 0 0x200>,
3085 <0 0xae90400 0 0xc00>,
3086 <0 0xae91000 0 0x400>,
3087 <0 0xae91400 0 0x400>;
3101 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
3108 #sound-dai-cells = <0>;
3112 #size-cells = <0>;
3113 port@0 {
3114 reg = <0>;
3154 reg = <0 0x0af00000 0 0x200000>;
3157 <&dsi_phy 0>,
3159 <&dp_phy 0>,
3174 reg = <0 0x0b220000 0 0x30000>;
3175 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
3183 reg = <0 0x0b2e0000 0 0x20000>;
3189 reg = <0 0x0c263000 0 0x1ff>, /* TM */
3190 <0 0x0c222000 0 0x1ff>; /* SROT */
3200 reg = <0 0x0c265000 0 0x1ff>, /* TM */
3201 <0 0x0c223000 0 0x1ff>; /* SROT */
3211 reg = <0 0x0c2a0000 0 0x31000>;
3217 reg = <0 0x0c300000 0 0x400>;
3219 mboxes = <&apss_shared 0>;
3221 #clock-cells = <0>;
3226 reg = <0 0x0c3f0000 0 0x400>;
3231 reg = <0 0x0c440000 0 0x1100>,
3232 <0 0x0c600000 0 0x2000000>,
3233 <0 0x0e600000 0 0x100000>,
3234 <0 0x0e700000 0 0xa0000>,
3235 <0 0x0c40a000 0 0x26000>;
3239 qcom,ee = <0>;
3240 qcom,channel = <0>;
3245 cell-index = <0>;
3250 reg = <0 0x146aa000 0 0x2000>;
3255 ranges = <0 0 0x146aa000 0x2000>;
3259 reg = <0x94c 0xc8>;
3265 reg = <0 0x15000000 0 0x100000>;
3358 reg = <0 0x17a00000 0 0x10000>, /* GICD */
3359 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
3366 reg = <0 0x17a40000 0 0x20000>;
3373 reg = <0 0x17c00000 0 0x10000>;
3379 reg = <0 0x17c10000 0 0x1000>;
3381 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
3387 ranges = <0 0 0 0x20000000>;
3389 reg = <0 0x17c20000 0 0x1000>;
3392 frame-number = <0>;
3395 reg = <0x17c21000 0x1000>,
3396 <0x17c22000 0x1000>;
3402 reg = <0x17c23000 0x1000>;
3409 reg = <0x17c25000 0x1000>;
3416 reg = <0x17c27000 0x1000>;
3423 reg = <0x17c29000 0x1000>;
3430 reg = <0x17c2b000 0x1000>;
3437 reg = <0x17c2d000 0x1000>;
3444 reg = <0 0x18200000 0 0x10000>,
3445 <0 0x18210000 0 0x10000>,
3446 <0 0x18220000 0 0x10000>;
3447 reg-names = "drv-0", "drv-1", "drv-2";
3451 qcom,tcs-offset = <0xd00>;
3526 reg = <0 0x18321000 0 0x1400>;
3536 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
3547 reg = <0 0x18800000 0 0x800000>;
3549 iommus = <&apps_smmu 0xc0 0x1>;
3570 reg = <0 0x62d00000 0 0x50000>,
3571 <0 0x62780000 0 0x30000>;
3584 reg = <0 0x62d87000 0 0x68000>, <0 0x62f00000 0 0x29000>;
3587 iommus = <&apps_smmu 0x1020 0>,
3588 <&apps_smmu 0x1021 0>,
3589 <&apps_smmu 0x1032 0>;
3609 #size-cells = <0>;
3618 reg = <0 0x63000000 0 0x28>;
3630 polling-delay = <0>;
3679 polling-delay = <0>;
3728 polling-delay = <0>;
3777 polling-delay = <0>;
3826 polling-delay = <0>;
3875 polling-delay = <0>;
3924 polling-delay = <0>;
3965 polling-delay = <0>;
4006 polling-delay = <0>;
4047 polling-delay = <0>;
4088 polling-delay = <0>;
4090 thermal-sensors = <&tsens0 0>;
4109 polling-delay = <0>;
4129 polling-delay = <0>;
4149 polling-delay = <0>;
4177 polling-delay = <0>;
4205 polling-delay = <0>;
4207 thermal-sensors = <&tsens1 0>;
4226 polling-delay = <0>;
4247 polling-delay = <0>;
4268 polling-delay = <0>;
4289 polling-delay = <0>;
4310 polling-delay = <0>;
4331 polling-delay = <0>;
4352 polling-delay = <0>;
4373 polling-delay = <0>;
4394 polling-delay = <0>;
4419 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;