Lines Matching refs:gcc
5 #include <dt-bindings/clock/qcom,gcc-qcs404.h>
307 clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>;
325 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
326 <&gcc GCC_USB3_PHY_PIPE_CLK>;
328 resets = <&gcc GCC_USB3_PHY_BCR>,
329 <&gcc GCC_USB3PHY_PHY_BCR>;
339 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
340 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
342 resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>,
343 <&gcc GCC_USB2A_PHY_BCR>;
353 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
354 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
356 resets = <&gcc GCC_QUSB2_PHY_BCR>,
357 <&gcc GCC_USB2_HS_PHY_ONLY_BCR>;
431 clocks = <&gcc GCC_PRNG_AHB_CLK>;
487 <&gcc GCC_CDSP_CFG_AHB_CLK>,
488 <&gcc GCC_CDSP_TBU_CLK>,
489 <&gcc GCC_BIMC_CDSP_CLK>,
503 resets = <&gcc GCC_CDSP_RESTART>;
531 clocks = <&gcc GCC_USB30_MASTER_CLK>,
532 <&gcc GCC_SYS_NOC_USB3_CLK>,
533 <&gcc GCC_USB30_SLEEP_CLK>,
534 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
536 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
537 <&gcc GCC_USB30_MASTER_CLK>;
560 clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>,
561 <&gcc GCC_PCNOC_USB2_CLK>,
562 <&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>,
563 <&gcc GCC_USB20_MOCK_UTMI_CLK>;
565 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
566 <&gcc GCC_USB_HS_SYSTEM_CLK>;
713 gcc: clock-controller@1800000 { label
714 compatible = "qcom,gcc-qcs404";
719 assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>;
793 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
794 resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
795 <&gcc 21>;
813 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
814 <&gcc GCC_SDCC1_APPS_CLK>,
825 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
836 clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
849 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
862 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
877 clocks = <&gcc GCC_ETH_AXI_CLK>,
878 <&gcc GCC_ETH_SLAVE_AHB_CLK>,
879 <&gcc GCC_ETH_PTP_CLK>,
880 <&gcc GCC_ETH_RGMII_CLK>;
916 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
929 clocks = <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>,
930 <&gcc GCC_BLSP1_AHB_CLK>;
943 clocks = <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>,
944 <&gcc GCC_BLSP1_AHB_CLK>;
957 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
958 <&gcc GCC_BLSP1_AHB_CLK>;
971 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
972 <&gcc GCC_BLSP1_AHB_CLK>;
985 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
986 <&gcc GCC_BLSP1_AHB_CLK>;
999 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
1000 <&gcc GCC_BLSP1_AHB_CLK>;
1013 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
1014 <&gcc GCC_BLSP1_AHB_CLK>;
1027 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
1028 <&gcc GCC_BLSP1_AHB_CLK>;
1041 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
1042 <&gcc GCC_BLSP1_AHB_CLK>;
1055 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
1056 <&gcc GCC_BLSP1_AHB_CLK>;
1069 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
1080 clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
1093 clocks = <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>,
1094 <&gcc GCC_BLSP2_AHB_CLK>;
1107 clocks = <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>,
1108 <&gcc GCC_BLSP2_AHB_CLK>;
1144 clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>;
1319 clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1320 <&gcc GCC_PCIE_0_AUX_CLK>,
1321 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1322 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
1325 resets = <&gcc 18>,
1326 <&gcc 17>,
1327 <&gcc 15>,
1328 <&gcc 19>,
1329 <&gcc GCC_PCIE_0_BCR>,
1330 <&gcc 16>;