Lines Matching +full:msm +full:- +full:uartdm +full:- +full:v1
1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-qcs404.h>
6 #include <dt-bindings/clock/qcom,turingcc-qcs404.h>
7 #include <dt-bindings/clock/qcom,rpmcc.h>
8 #include <dt-bindings/power/qcom-rpmpd.h>
9 #include <dt-bindings/thermal/thermal.h>
12 interrupt-parent = <&intc>;
14 #address-cells = <2>;
15 #size-cells = <2>;
20 xo_board: xo-board {
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
23 clock-frequency = <19200000>;
26 sleep_clk: sleep-clk {
27 compatible = "fixed-clock";
28 #clock-cells = <0>;
29 clock-frequency = <32768>;
34 #address-cells = <1>;
35 #size-cells = <0>;
39 compatible = "arm,cortex-a53";
41 enable-method = "psci";
42 cpu-idle-states = <&CPU_SLEEP_0>;
43 next-level-cache = <&L2_0>;
44 #cooling-cells = <2>;
46 operating-points-v2 = <&cpu_opp_table>;
47 power-domains = <&cpr>;
48 power-domain-names = "cpr";
53 compatible = "arm,cortex-a53";
55 enable-method = "psci";
56 cpu-idle-states = <&CPU_SLEEP_0>;
57 next-level-cache = <&L2_0>;
58 #cooling-cells = <2>;
60 operating-points-v2 = <&cpu_opp_table>;
61 power-domains = <&cpr>;
62 power-domain-names = "cpr";
67 compatible = "arm,cortex-a53";
69 enable-method = "psci";
70 cpu-idle-states = <&CPU_SLEEP_0>;
71 next-level-cache = <&L2_0>;
72 #cooling-cells = <2>;
74 operating-points-v2 = <&cpu_opp_table>;
75 power-domains = <&cpr>;
76 power-domain-names = "cpr";
81 compatible = "arm,cortex-a53";
83 enable-method = "psci";
84 cpu-idle-states = <&CPU_SLEEP_0>;
85 next-level-cache = <&L2_0>;
86 #cooling-cells = <2>;
88 operating-points-v2 = <&cpu_opp_table>;
89 power-domains = <&cpr>;
90 power-domain-names = "cpr";
93 L2_0: l2-cache {
95 cache-level = <2>;
98 idle-states {
99 entry-method = "psci";
101 CPU_SLEEP_0: cpu-sleep-0 {
102 compatible = "arm,idle-state";
103 idle-state-name = "standalone-power-collapse";
104 arm,psci-suspend-param = <0x40000003>;
105 entry-latency-us = <125>;
106 exit-latency-us = <180>;
107 min-residency-us = <595>;
108 local-timer-stop;
113 cpu_opp_table: opp-table-cpu {
114 compatible = "operating-points-v2-kryo-cpu";
115 opp-shared;
117 opp-1094400000 {
118 opp-hz = /bits/ 64 <1094400000>;
119 required-opps = <&cpr_opp1>;
121 opp-1248000000 {
122 opp-hz = /bits/ 64 <1248000000>;
123 required-opps = <&cpr_opp2>;
125 opp-1401600000 {
126 opp-hz = /bits/ 64 <1401600000>;
127 required-opps = <&cpr_opp3>;
131 cpr_opp_table: opp-table-cpr {
132 compatible = "operating-points-v2-qcom-level";
135 opp-level = <1>;
136 qcom,opp-fuse-level = <1>;
139 opp-level = <2>;
140 qcom,opp-fuse-level = <2>;
143 opp-level = <3>;
144 qcom,opp-fuse-level = <3>;
150 compatible = "qcom,scm-qcs404", "qcom,scm";
151 #reset-cells = <1>;
162 compatible = "arm,psci-1.0";
166 reserved-memory {
167 #address-cells = <2>;
168 #size-cells = <2>;
173 no-map;
178 no-map;
183 no-map;
188 no-map;
193 no-map;
198 no-map;
203 no-map;
208 no-map;
213 no-map;
217 rpm-glink {
218 compatible = "qcom,glink-rpm";
221 qcom,rpm-msg-ram = <&rpm_msg_ram>;
224 rpm_requests: glink-channel {
225 compatible = "qcom,rpm-qcs404";
226 qcom,glink-channels = "rpm_requests";
228 rpmcc: clock-controller {
229 compatible = "qcom,rpmcc-qcs404", "qcom,rpmcc";
230 #clock-cells = <1>;
233 rpmpd: power-controller {
234 compatible = "qcom,qcs404-rpmpd";
235 #power-domain-cells = <1>;
236 operating-points-v2 = <&rpmpd_opp_table>;
238 rpmpd_opp_table: opp-table {
239 compatible = "operating-points-v2";
242 opp-level = <16>;
246 opp-level = <32>;
250 opp-level = <48>;
254 opp-level = <64>;
258 opp-level = <128>;
262 opp-level = <192>;
266 opp-level = <256>;
270 opp-level = <320>;
274 opp-level = <384>;
278 opp-level = <416>;
282 opp-level = <512>;
292 memory-region = <&smem_region>;
293 qcom,rpm-msg-ram = <&rpm_msg_ram>;
299 #address-cells = <1>;
300 #size-cells = <1>;
302 compatible = "simple-bus";
304 turingcc: clock-controller@800000 {
305 compatible = "qcom,qcs404-turingcc";
309 #clock-cells = <1>;
310 #reset-cells = <1>;
316 compatible = "qcom,rpm-msg-ram";
321 compatible = "qcom,usb-ss-28nm-phy";
323 #phy-cells = <0>;
327 clock-names = "ref", "ahb", "pipe";
330 reset-names = "com", "phy";
335 compatible = "qcom,usb-hs-28nm-femtophy";
337 #phy-cells = <0>;
341 clock-names = "ref", "ahb", "sleep";
344 reset-names = "phy", "por";
349 compatible = "qcom,usb-hs-28nm-femtophy";
351 #phy-cells = <0>;
355 clock-names = "ref", "ahb", "sleep";
358 reset-names = "phy", "por";
363 compatible = "qcom,qcs404-qfprom", "qcom,qfprom";
365 #address-cells = <1>;
366 #size-cells = <1>;
429 compatible = "qcom,prng-ee";
432 clock-names = "core";
437 compatible = "qcom,qcs404-bimc";
438 #interconnect-cells = <1>;
439 clock-names = "bus", "bus_a";
444 tsens: thermal-sensor@4a9000 {
445 compatible = "qcom,qcs404-tsens", "qcom,tsens-v1";
448 nvmem-cells = <&tsens_caldata>;
449 nvmem-cell-names = "calib";
452 interrupt-names = "uplow";
453 #thermal-sensor-cells = <1>;
458 compatible = "qcom,qcs404-pcnoc";
459 #interconnect-cells = <1>;
460 clock-names = "bus", "bus_a";
467 compatible = "qcom,qcs404-snoc";
468 #interconnect-cells = <1>;
469 clock-names = "bus", "bus_a";
475 compatible = "qcom,qcs404-cdsp-pas";
478 interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
483 interrupt-names = "wdog", "fatal", "ready",
484 "handover", "stop-ack";
494 clock-names = "xo",
504 reset-names = "restart";
506 qcom,halt-regs = <&tcsr 0x19004>;
508 memory-region = <&cdsp_fw_mem>;
510 qcom,smem-states = <&cdsp_smp2p_out 0>;
511 qcom,smem-state-names = "stop";
515 glink-edge {
518 qcom,remote-pid = <5>;
526 compatible = "qcom,qcs404-dwc3", "qcom,dwc3";
528 #address-cells = <1>;
529 #size-cells = <1>;
535 clock-names = "core", "iface", "sleep", "mock_utmi";
536 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
538 assigned-clock-rates = <19200000>, <200000000>;
546 phy-names = "usb2-phy", "usb3-phy";
547 snps,has-lpm-erratum;
548 snps,hird-threshold = /bits/ 8 <0x10>;
555 compatible = "qcom,qcs404-dwc3", "qcom,dwc3";
557 #address-cells = <1>;
558 #size-cells = <1>;
564 clock-names = "core", "iface", "sleep", "mock_utmi";
565 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
567 assigned-clock-rates = <19200000>, <133333333>;
575 phy-names = "usb2-phy";
576 snps,has-lpm-erratum;
577 snps,hird-threshold = /bits/ 8 <0x10>;
584 compatible = "qcom,qcs404-pinctrl";
588 reg-names = "south", "north", "east";
590 gpio-ranges = <&tlmm 0 0 120>;
591 gpio-controller;
592 #gpio-cells = <2>;
593 interrupt-controller;
594 #interrupt-cells = <2>;
596 blsp1_i2c0_default: blsp1-i2c0-default {
601 blsp1_i2c1_default: blsp1-i2c1-default {
606 blsp1_i2c2_default: blsp1-i2c2-default {
618 blsp1_i2c3_default: blsp1-i2c3-default {
623 blsp1_i2c4_default: blsp1-i2c4-default {
628 blsp1_uart0_default: blsp1-uart0-default {
633 blsp1_uart1_default: blsp1-uart1-default {
638 blsp1_uart2_default: blsp1-uart2-default {
650 blsp1_uart3_default: blsp1-uart3-default {
655 blsp2_i2c0_default: blsp2-i2c0-default {
660 blsp1_spi0_default: blsp1-spi0-default {
665 blsp1_spi1_default: blsp1-spi1-default {
687 blsp1_spi2_default: blsp1-spi2-default {
692 blsp1_spi3_default: blsp1-spi3-default {
697 blsp1_spi4_default: blsp1-spi4-default {
702 blsp2_spi0_default: blsp2-spi0-default {
707 blsp2_uart0_default: blsp2-uart0-default {
713 gcc: clock-controller@1800000 {
714 compatible = "qcom,gcc-qcs404";
716 #clock-cells = <1>;
717 #reset-cells = <1>;
719 assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>;
720 assigned-clock-rates = <19200000>;
724 compatible = "qcom,tcsr-mutex";
726 #hwlock-cells = <1>;
730 compatible = "qcom,qcs404-tcsr", "syscon";
735 compatible = "qcom,rpm-stats";
740 compatible = "qcom,spmi-pmic-arb";
746 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
747 interrupt-names = "periph_irq";
751 #address-cells = <2>;
752 #size-cells = <0>;
753 interrupt-controller;
754 #interrupt-cells = <4>;
758 compatible = "qcom,qcs404-wcss-pas";
761 interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>,
766 interrupt-names = "wdog", "fatal", "ready",
767 "handover", "stop-ack";
770 clock-names = "xo";
772 memory-region = <&wlan_fw_mem>;
774 qcom,smem-states = <&wcss_smp2p_out 0>;
775 qcom,smem-state-names = "stop";
779 glink-edge {
782 qcom,remote-pid = <1>;
790 compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
796 reset-names = "phy", "pipe";
798 clock-output-names = "pcie_0_pipe_clk";
799 #phy-cells = <0>;
805 compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5";
807 reg-names = "hc", "cqhci";
811 interrupt-names = "hc_irq", "pwr_irq";
816 clock-names = "iface", "core", "xo";
821 blsp1_dma: dma-controller@7884000 {
822 compatible = "qcom,bam-v1.7.0";
826 clock-names = "bam_clk";
827 #dma-cells = <1>;
833 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
837 clock-names = "core", "iface";
839 dma-names = "tx", "rx";
840 pinctrl-names = "default";
841 pinctrl-0 = <&blsp1_uart0_default>;
846 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
850 clock-names = "core", "iface";
852 dma-names = "tx", "rx";
853 pinctrl-names = "default";
854 pinctrl-0 = <&blsp1_uart1_default>;
859 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
863 clock-names = "core", "iface";
865 dma-names = "tx", "rx";
866 pinctrl-names = "default";
867 pinctrl-0 = <&blsp1_uart2_default>;
872 compatible = "qcom,qcs404-ethqos";
875 reg-names = "stmmaceth", "rgmii";
876 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
883 interrupt-names = "macirq", "eth_lpi";
886 rx-fifo-depth = <4096>;
887 tx-fifo-depth = <4096>;
893 compatible = "qcom,wcn3990-wifi";
895 reg-names = "membase";
896 memory-region = <&wlan_msa_mem>;
913 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
917 clock-names = "core", "iface";
919 dma-names = "tx", "rx";
920 pinctrl-names = "default";
921 pinctrl-0 = <&blsp1_uart3_default>;
926 compatible = "qcom,i2c-qup-v2.2.1";
931 clock-names = "core", "iface";
932 pinctrl-names = "default";
933 pinctrl-0 = <&blsp1_i2c0_default>;
934 #address-cells = <1>;
935 #size-cells = <0>;
940 compatible = "qcom,spi-qup-v2.2.1";
945 clock-names = "core", "iface";
946 pinctrl-names = "default";
947 pinctrl-0 = <&blsp1_spi0_default>;
948 #address-cells = <1>;
949 #size-cells = <0>;
954 compatible = "qcom,i2c-qup-v2.2.1";
959 clock-names = "core", "iface";
960 pinctrl-names = "default";
961 pinctrl-0 = <&blsp1_i2c1_default>;
962 #address-cells = <1>;
963 #size-cells = <0>;
968 compatible = "qcom,spi-qup-v2.2.1";
973 clock-names = "core", "iface";
974 pinctrl-names = "default";
975 pinctrl-0 = <&blsp1_spi1_default>;
976 #address-cells = <1>;
977 #size-cells = <0>;
982 compatible = "qcom,i2c-qup-v2.2.1";
987 clock-names = "core", "iface";
988 pinctrl-names = "default";
989 pinctrl-0 = <&blsp1_i2c2_default>;
990 #address-cells = <1>;
991 #size-cells = <0>;
996 compatible = "qcom,spi-qup-v2.2.1";
1001 clock-names = "core", "iface";
1002 pinctrl-names = "default";
1003 pinctrl-0 = <&blsp1_spi2_default>;
1004 #address-cells = <1>;
1005 #size-cells = <0>;
1010 compatible = "qcom,i2c-qup-v2.2.1";
1015 clock-names = "core", "iface";
1016 pinctrl-names = "default";
1017 pinctrl-0 = <&blsp1_i2c3_default>;
1018 #address-cells = <1>;
1019 #size-cells = <0>;
1024 compatible = "qcom,spi-qup-v2.2.1";
1029 clock-names = "core", "iface";
1030 pinctrl-names = "default";
1031 pinctrl-0 = <&blsp1_spi3_default>;
1032 #address-cells = <1>;
1033 #size-cells = <0>;
1038 compatible = "qcom,i2c-qup-v2.2.1";
1043 clock-names = "core", "iface";
1044 pinctrl-names = "default";
1045 pinctrl-0 = <&blsp1_i2c4_default>;
1046 #address-cells = <1>;
1047 #size-cells = <0>;
1052 compatible = "qcom,spi-qup-v2.2.1";
1057 clock-names = "core", "iface";
1058 pinctrl-names = "default";
1059 pinctrl-0 = <&blsp1_spi4_default>;
1060 #address-cells = <1>;
1061 #size-cells = <0>;
1065 blsp2_dma: dma-controller@7ac4000 {
1066 compatible = "qcom,bam-v1.7.0";
1070 clock-names = "bam_clk";
1071 #dma-cells = <1>;
1077 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1081 clock-names = "core", "iface";
1083 dma-names = "tx", "rx";
1084 pinctrl-names = "default";
1085 pinctrl-0 = <&blsp2_uart0_default>;
1090 compatible = "qcom,i2c-qup-v2.2.1";
1095 clock-names = "core", "iface";
1096 pinctrl-names = "default";
1097 pinctrl-0 = <&blsp2_i2c0_default>;
1098 #address-cells = <1>;
1099 #size-cells = <0>;
1104 compatible = "qcom,spi-qup-v2.2.1";
1109 clock-names = "core", "iface";
1110 pinctrl-names = "default";
1111 pinctrl-0 = <&blsp2_spi0_default>;
1112 #address-cells = <1>;
1113 #size-cells = <0>;
1118 compatible = "qcom,qcs404-imem", "syscon", "simple-mfd";
1121 #address-cells = <1>;
1122 #size-cells = <1>;
1126 pil-reloc@94c {
1127 compatible = "qcom,pil-reloc-info";
1132 intc: interrupt-controller@b000000 {
1133 compatible = "qcom,msm-qgic2";
1134 interrupt-controller;
1135 #interrupt-cells = <3>;
1141 compatible = "qcom,qcs404-apcs-apps-global", "syscon";
1143 #mbox-cells = <1>;
1145 clock-names = "pll", "aux";
1146 #clock-cells = <0>;
1149 apcs_hfpll: clock-controller@b016000 {
1152 #clock-cells = <0>;
1153 clock-output-names = "apcs_hfpll";
1155 clock-names = "xo";
1159 compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt";
1164 cpr: power-controller@b018000 {
1165 compatible = "qcom,qcs404-cpr", "qcom,cpr";
1169 clock-names = "ref";
1170 vdd-apc-supply = <&pms405_s3>;
1171 #power-domain-cells = <0>;
1172 operating-points-v2 = <&cpr_opp_table>;
1173 acc-syscon = <&tcsr>;
1175 nvmem-cells = <&cpr_efuse_quot_offset1>,
1188 nvmem-cell-names = "cpr_quotient_offset1",
1204 #address-cells = <1>;
1205 #size-cells = <1>;
1207 compatible = "arm,armv7-timer-mem";
1209 clock-frequency = <19200000>;
1212 frame-number = <0>;
1220 frame-number = <1>;
1227 frame-number = <2>;
1234 frame-number = <3>;
1241 frame-number = <4>;
1248 frame-number = <5>;
1255 frame-number = <6>;
1263 compatible = "qcom,qcs404-adsp-pas";
1266 interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>,
1271 interrupt-names = "wdog", "fatal", "ready",
1272 "handover", "stop-ack";
1275 clock-names = "xo";
1277 memory-region = <&adsp_fw_mem>;
1279 qcom,smem-states = <&adsp_smp2p_out 0>;
1280 qcom,smem-state-names = "stop";
1284 glink-edge {
1287 qcom,remote-pid = <2>;
1295 compatible = "qcom,pcie-qcs404";
1300 reg-names = "dbi", "elbi", "parf", "config";
1302 linux,pci-domain = <0>;
1303 bus-range = <0x00 0xff>;
1304 num-lanes = <1>;
1305 #address-cells = <3>;
1306 #size-cells = <2>;
1312 interrupt-names = "msi";
1313 #interrupt-cells = <1>;
1314 interrupt-map-mask = <0 0 0 0x7>;
1315 interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1323 clock-names = "iface", "aux", "master_bus", "slave_bus";
1331 reset-names = "axi_m",
1339 phy-names = "pciephy";
1346 compatible = "arm,armv8-timer";
1353 smp2p-adsp {
1358 qcom,local-pid = <0>;
1359 qcom,remote-pid = <2>;
1361 adsp_smp2p_out: master-kernel {
1362 qcom,entry-name = "master-kernel";
1363 #qcom,smem-state-cells = <1>;
1366 adsp_smp2p_in: slave-kernel {
1367 qcom,entry-name = "slave-kernel";
1368 interrupt-controller;
1369 #interrupt-cells = <2>;
1373 smp2p-cdsp {
1378 qcom,local-pid = <0>;
1379 qcom,remote-pid = <5>;
1381 cdsp_smp2p_out: master-kernel {
1382 qcom,entry-name = "master-kernel";
1383 #qcom,smem-state-cells = <1>;
1386 cdsp_smp2p_in: slave-kernel {
1387 qcom,entry-name = "slave-kernel";
1388 interrupt-controller;
1389 #interrupt-cells = <2>;
1393 smp2p-wcss {
1398 qcom,local-pid = <0>;
1399 qcom,remote-pid = <1>;
1401 wcss_smp2p_out: master-kernel {
1402 qcom,entry-name = "master-kernel";
1403 #qcom,smem-state-cells = <1>;
1406 wcss_smp2p_in: slave-kernel {
1407 qcom,entry-name = "slave-kernel";
1408 interrupt-controller;
1409 #interrupt-cells = <2>;
1413 thermal-zones {
1414 aoss-thermal {
1415 polling-delay-passive = <250>;
1416 polling-delay = <1000>;
1418 thermal-sensors = <&tsens 0>;
1421 aoss_alert0: trip-point0 {
1429 q6-hvx-thermal {
1430 polling-delay-passive = <250>;
1431 polling-delay = <1000>;
1433 thermal-sensors = <&tsens 1>;
1436 q6_hvx_alert0: trip-point0 {
1444 lpass-thermal {
1445 polling-delay-passive = <250>;
1446 polling-delay = <1000>;
1448 thermal-sensors = <&tsens 2>;
1451 lpass_alert0: trip-point0 {
1459 wlan-thermal {
1460 polling-delay-passive = <250>;
1461 polling-delay = <1000>;
1463 thermal-sensors = <&tsens 3>;
1466 wlan_alert0: trip-point0 {
1474 cluster-thermal {
1475 polling-delay-passive = <250>;
1476 polling-delay = <1000>;
1478 thermal-sensors = <&tsens 4>;
1481 cluster_alert0: trip-point0 {
1486 cluster_alert1: trip-point1 {
1497 cooling-maps {
1500 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1508 cpu0-thermal {
1509 polling-delay-passive = <250>;
1510 polling-delay = <1000>;
1512 thermal-sensors = <&tsens 5>;
1515 cpu0_alert0: trip-point0 {
1520 cpu0_alert1: trip-point1 {
1531 cooling-maps {
1534 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1542 cpu1-thermal {
1543 polling-delay-passive = <250>;
1544 polling-delay = <1000>;
1546 thermal-sensors = <&tsens 6>;
1549 cpu1_alert0: trip-point0 {
1554 cpu1_alert1: trip-point1 {
1565 cooling-maps {
1568 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1576 cpu2-thermal {
1577 polling-delay-passive = <250>;
1578 polling-delay = <1000>;
1580 thermal-sensors = <&tsens 7>;
1583 cpu2_alert0: trip-point0 {
1588 cpu2_alert1: trip-point1 {
1599 cooling-maps {
1602 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1610 cpu3-thermal {
1611 polling-delay-passive = <250>;
1612 polling-delay = <1000>;
1614 thermal-sensors = <&tsens 8>;
1617 cpu3_alert0: trip-point0 {
1622 cpu3_alert1: trip-point1 {
1633 cooling-maps {
1636 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1644 gpu-thermal {
1645 polling-delay-passive = <250>;
1646 polling-delay = <1000>;
1648 thermal-sensors = <&tsens 9>;
1651 gpu_alert0: trip-point0 {