Lines Matching +full:0 +full:x02c00000
22 #clock-cells = <0>;
28 #clock-cells = <0>;
35 #size-cells = <0>;
40 reg = <0x100>;
54 reg = <0x101>;
68 reg = <0x102>;
82 reg = <0x103>;
101 CPU_SLEEP_0: cpu-sleep-0 {
104 arm,psci-suspend-param = <0x40000003>;
158 reg = <0 0x80000000 0 0>;
172 reg = <0 0x85900000 0 0x500000>;
177 reg = <0 0x85e00000 0 0x100000>;
182 reg = <0 0x85f00000 0 0x200000>;
187 reg = <0 0x86100000 0 0x300000>;
192 reg = <0 0x86400000 0 0x1100000>;
197 reg = <0 0x87500000 0 0x1a00000>;
202 reg = <0 0x88f00000 0 0x600000>;
207 reg = <0 0x89500000 0 0x100000>;
212 reg = <0 0x9f800000 0 0x800000>;
222 mboxes = <&apcs_glb 0>;
298 soc: soc@0 {
301 ranges = <0 0 0 0xffffffff>;
306 reg = <0x00800000 0x30000>;
317 reg = <0x00060000 0x6000>;
322 reg = <0x00078000 0x400>;
323 #phy-cells = <0>;
336 reg = <0x0007a000 0x200>;
337 #phy-cells = <0>;
350 reg = <0x0007c000 0x200>;
351 #phy-cells = <0>;
364 reg = <0x000a4000 0x1000>;
368 reg = <0x1f8 0x14>;
371 reg = <0x13c 0x4>;
375 reg = <0x231 0x4>;
379 reg = <0x232 0x4>;
383 reg = <0x233 0x4>;
387 reg = <0x229 0x4>;
391 reg = <0x22a 0x4>;
395 reg = <0x22b 0x4>;
396 bits = <0 6>;
399 reg = <0x22b 0x4>;
403 reg = <0x22d 0x4>;
407 reg = <0x230 0x4>;
408 bits = <0 12>;
411 reg = <0x228 0x4>;
412 bits = <0 3>;
415 reg = <0x228 0x4>;
419 reg = <0x229 0x4>;
420 bits = <0 3>;
423 reg = <0x218 0x4>;
430 reg = <0x000e3000 0x1000>;
436 reg = <0x00400000 0x80000>;
446 reg = <0x004a9000 0x1000>, /* TM */
447 <0x004a8000 0x1000>; /* SROT */
457 reg = <0x00500000 0x15080>;
466 reg = <0x00580000 0x23080>;
476 reg = <0x00b00000 0x4040>;
479 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
506 qcom,halt-regs = <&tcsr 0x19004>;
510 qcom,smem-states = <&cdsp_smp2p_out 0>;
527 reg = <0x07678800 0x400>;
543 reg = <0x07580000 0xcd00>;
548 snps,hird-threshold = /bits/ 8 <0x10>;
556 reg = <0x079b8800 0x400>;
572 reg = <0x078c0000 0xcc00>;
577 snps,hird-threshold = /bits/ 8 <0x10>;
585 reg = <0x01000000 0x200000>,
586 <0x01300000 0x200000>,
587 <0x07b00000 0x200000>;
590 gpio-ranges = <&tlmm 0 0 120>;
715 reg = <0x01800000 0x80000>;
725 reg = <0x01905000 0x20000>;
731 reg = <0x01937000 0x25000>;
736 reg = <0x00290000 0x10000>;
741 reg = <0x0200f000 0x001000>,
742 <0x02400000 0x800000>,
743 <0x02c00000 0x800000>,
744 <0x03800000 0x200000>,
745 <0x0200a000 0x002100>;
749 qcom,ee = <0>;
750 qcom,channel = <0>;
752 #size-cells = <0>;
759 reg = <0x07400000 0x4040>;
762 <&wcss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
774 qcom,smem-states = <&wcss_smp2p_out 0>;
791 reg = <0x07786000 0xb8>;
799 #phy-cells = <0>;
806 reg = <0x07804000 0x1000>, <0x7805000 0x1000>;
823 reg = <0x07884000 0x25000>;
828 qcom,ee = <0>;
834 reg = <0x078af000 0x200>;
838 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>;
841 pinctrl-0 = <&blsp1_uart0_default>;
847 reg = <0x078b0000 0x200>;
854 pinctrl-0 = <&blsp1_uart1_default>;
860 reg = <0x078b1000 0x200>;
867 pinctrl-0 = <&blsp1_uart2_default>;
873 reg = <0x07a80000 0x10000>,
874 <0x07a96000 0x100>;
894 reg = <0xa000000 0x800000>;
914 reg = <0x078b2000 0x200>;
921 pinctrl-0 = <&blsp1_uart3_default>;
927 reg = <0x078b5000 0x600>;
933 pinctrl-0 = <&blsp1_i2c0_default>;
935 #size-cells = <0>;
941 reg = <0x078b5000 0x600>;
947 pinctrl-0 = <&blsp1_spi0_default>;
949 #size-cells = <0>;
955 reg = <0x078b6000 0x600>;
961 pinctrl-0 = <&blsp1_i2c1_default>;
963 #size-cells = <0>;
969 reg = <0x078b6000 0x600>;
975 pinctrl-0 = <&blsp1_spi1_default>;
977 #size-cells = <0>;
983 reg = <0x078b7000 0x600>;
989 pinctrl-0 = <&blsp1_i2c2_default>;
991 #size-cells = <0>;
997 reg = <0x078b7000 0x600>;
1003 pinctrl-0 = <&blsp1_spi2_default>;
1005 #size-cells = <0>;
1011 reg = <0x078b8000 0x600>;
1017 pinctrl-0 = <&blsp1_i2c3_default>;
1019 #size-cells = <0>;
1025 reg = <0x078b8000 0x600>;
1031 pinctrl-0 = <&blsp1_spi3_default>;
1033 #size-cells = <0>;
1039 reg = <0x078b9000 0x600>;
1045 pinctrl-0 = <&blsp1_i2c4_default>;
1047 #size-cells = <0>;
1053 reg = <0x078b9000 0x600>;
1059 pinctrl-0 = <&blsp1_spi4_default>;
1061 #size-cells = <0>;
1067 reg = <0x07ac4000 0x17000>;
1072 qcom,ee = <0>;
1078 reg = <0x07aef000 0x200>;
1082 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
1085 pinctrl-0 = <&blsp2_uart0_default>;
1091 reg = <0x07af5000 0x600>;
1097 pinctrl-0 = <&blsp2_i2c0_default>;
1099 #size-cells = <0>;
1105 reg = <0x07af5000 0x600>;
1111 pinctrl-0 = <&blsp2_spi0_default>;
1113 #size-cells = <0>;
1119 reg = <0x08600000 0x1000>;
1124 ranges = <0 0x08600000 0x1000>;
1128 reg = <0x94c 0xc8>;
1136 reg = <0x0b000000 0x1000>,
1137 <0x0b002000 0x1000>;
1142 reg = <0x0b011000 0x1000>;
1146 #clock-cells = <0>;
1151 reg = <0x0b016000 0x30>;
1152 #clock-cells = <0>;
1160 reg = <0x0b017000 0x1000>;
1166 reg = <0x0b018000 0x1000>;
1167 interrupts = <0 15 IRQ_TYPE_EDGE_RISING>;
1171 #power-domain-cells = <0>;
1208 reg = <0x0b120000 0x1000>;
1212 frame-number = <0>;
1215 reg = <0x0b121000 0x1000>,
1216 <0x0b122000 0x1000>;
1222 reg = <0x0b123000 0x1000>;
1229 reg = <0x0b124000 0x1000>;
1236 reg = <0x0b125000 0x1000>;
1243 reg = <0x0b126000 0x1000>;
1250 reg = <0xb127000 0x1000>;
1257 reg = <0x0b128000 0x1000>;
1264 reg = <0x0c700000 0x4040>;
1267 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1279 qcom,smem-states = <&adsp_smp2p_out 0>;
1296 reg = <0x10000000 0xf1d>,
1297 <0x10000f20 0xa8>,
1298 <0x07780000 0x2000>,
1299 <0x10001000 0x2000>;
1302 linux,pci-domain = <0>;
1303 bus-range = <0x00 0xff>;
1308 ranges = <0x81000000 0 0 0x10003000 0 0x00010000>, /* I/O */
1309 <0x82000000 0 0x10013000 0x10013000 0 0x007ed000>; /* memory */
1314 interrupt-map-mask = <0 0 0 0x7>;
1315 interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1316 <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1317 <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1318 <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1347 interrupts = <GIC_PPI 2 0xff08>,
1348 <GIC_PPI 3 0xff08>,
1349 <GIC_PPI 4 0xff08>,
1350 <GIC_PPI 1 0xff08>;
1358 qcom,local-pid = <0>;
1378 qcom,local-pid = <0>;
1398 qcom,local-pid = <0>;
1418 thermal-sensors = <&tsens 0>;