Lines Matching refs:gcc
5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
803 gcc: clock-controller@100000 { label
804 compatible = "qcom,gcc-msm8998";
931 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
932 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
933 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
934 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
935 <&gcc GCC_PCIE_0_AUX_CLK>;
938 power-domains = <&gcc PCIE_0_GDSC>;
951 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
952 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
953 <&gcc GCC_PCIE_CLKREF_CLK>;
956 resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
966 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
980 power-domains = <&gcc UFS_GDSC>;
994 <&gcc GCC_UFS_AXI_CLK>,
995 <&gcc GCC_AGGRE1_UFS_AXI_CLK>,
996 <&gcc GCC_UFS_AHB_CLK>,
997 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
999 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
1000 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>,
1001 <&gcc GCC_UFS_RX_SYMBOL_1_CLK>;
1012 resets = <&gcc GCC_UFS_BCR>;
1028 <&gcc GCC_UFS_CLKREF_CLK>,
1029 <&gcc GCC_UFS_PHY_AUX_CLK>;
1326 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1327 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>,
1328 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1329 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
1330 <&gcc GCC_MSS_SNOC_AXI_CLK>,
1331 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
1340 resets = <&gcc GCC_MSS_RESTART>;
1372 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1374 <&gcc GCC_BIMC_GFX_CLK>,
1375 <&gcc GCC_GPU_BIMC_GFX_CLK>,
1440 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1441 <&gcc GCC_BIMC_GFX_CLK>,
1442 <&gcc GCC_GPU_BIMC_GFX_CLK>;
1471 <&gcc GPLL0_OUT_MAIN>;
1996 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
1997 <&gcc GCC_USB30_MASTER_CLK>,
1998 <&gcc GCC_AGGRE1_USB3_AXI_CLK>,
1999 <&gcc GCC_USB30_SLEEP_CLK>,
2000 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
2007 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2008 <&gcc GCC_USB30_MASTER_CLK>;
2015 power-domains = <&gcc USB_30_GDSC>;
2017 resets = <&gcc GCC_USB_30_BCR>;
2040 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
2041 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2042 <&gcc GCC_USB3_CLKREF_CLK>;
2045 resets = <&gcc GCC_USB3_PHY_BCR>,
2046 <&gcc GCC_USB3PHY_PHY_BCR>;
2057 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
2069 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2070 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
2073 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2088 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2089 <&gcc GCC_SDCC2_APPS_CLK>,
2099 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
2112 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
2113 <&gcc GCC_BLSP1_AHB_CLK>;
2127 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
2128 <&gcc GCC_BLSP1_AHB_CLK>;
2147 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
2148 <&gcc GCC_BLSP1_AHB_CLK>;
2167 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
2168 <&gcc GCC_BLSP1_AHB_CLK>;
2187 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
2188 <&gcc GCC_BLSP1_AHB_CLK>;
2207 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
2208 <&gcc GCC_BLSP1_AHB_CLK>;
2227 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
2228 <&gcc GCC_BLSP1_AHB_CLK>;
2246 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
2259 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
2260 <&gcc GCC_BLSP2_AHB_CLK>;
2270 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
2271 <&gcc GCC_BLSP2_AHB_CLK>;
2290 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
2291 <&gcc GCC_BLSP2_AHB_CLK>;
2310 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
2311 <&gcc GCC_BLSP2_AHB_CLK>;
2330 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
2331 <&gcc GCC_BLSP2_AHB_CLK>;
2350 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
2351 <&gcc GCC_BLSP2_AHB_CLK>;
2370 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
2371 <&gcc GCC_BLSP2_AHB_CLK>;
2403 <&gcc GCC_MMSS_GPLL0_CLK>,