Lines Matching +full:redistributor +full:- +full:stride
1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
6 #include <dt-bindings/clock/qcom,gpucc-msm8998.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/power/qcom-rpmpd.h>
10 #include <dt-bindings/gpio/gpio.h>
13 interrupt-parent = <&intc>;
15 qcom,msm-id = <292 0x0>;
17 #address-cells = <2>;
18 #size-cells = <2>;
28 reserved-memory {
29 #address-cells = <2>;
30 #size-cells = <2>;
35 no-map;
40 no-map;
43 smem_mem: smem-mem@86000000 {
45 no-map;
50 no-map;
54 compatible = "qcom,rmtfs-mem";
56 no-map;
58 qcom,client-id = <1>;
64 no-map;
69 no-map;
74 no-map;
79 no-map;
84 no-map;
89 no-map;
94 no-map;
99 no-map;
104 no-map;
109 no-map;
114 xo: xo-board {
115 compatible = "fixed-clock";
116 #clock-cells = <0>;
117 clock-frequency = <19200000>;
118 clock-output-names = "xo_board";
121 sleep_clk: sleep-clk {
122 compatible = "fixed-clock";
123 #clock-cells = <0>;
124 clock-frequency = <32764>;
129 #address-cells = <2>;
130 #size-cells = <0>;
136 enable-method = "psci";
137 capacity-dmips-mhz = <1024>;
138 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
139 next-level-cache = <&L2_0>;
140 L2_0: l2-cache {
142 cache-level = <2>;
150 enable-method = "psci";
151 capacity-dmips-mhz = <1024>;
152 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
153 next-level-cache = <&L2_0>;
160 enable-method = "psci";
161 capacity-dmips-mhz = <1024>;
162 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
163 next-level-cache = <&L2_0>;
170 enable-method = "psci";
171 capacity-dmips-mhz = <1024>;
172 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
173 next-level-cache = <&L2_0>;
180 enable-method = "psci";
181 capacity-dmips-mhz = <1536>;
182 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
183 next-level-cache = <&L2_1>;
184 L2_1: l2-cache {
186 cache-level = <2>;
194 enable-method = "psci";
195 capacity-dmips-mhz = <1536>;
196 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
197 next-level-cache = <&L2_1>;
204 enable-method = "psci";
205 capacity-dmips-mhz = <1536>;
206 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
207 next-level-cache = <&L2_1>;
214 enable-method = "psci";
215 capacity-dmips-mhz = <1536>;
216 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
217 next-level-cache = <&L2_1>;
220 cpu-map {
258 idle-states {
259 entry-method = "psci";
261 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
262 compatible = "arm,idle-state";
263 idle-state-name = "little-retention";
265 arm,psci-suspend-param = <0x00000002>;
266 entry-latency-us = <81>;
267 exit-latency-us = <86>;
268 min-residency-us = <504>;
271 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
272 compatible = "arm,idle-state";
273 idle-state-name = "little-power-collapse";
275 arm,psci-suspend-param = <0x40000003>;
276 entry-latency-us = <814>;
277 exit-latency-us = <4562>;
278 min-residency-us = <9183>;
279 local-timer-stop;
282 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
283 compatible = "arm,idle-state";
284 idle-state-name = "big-retention";
286 arm,psci-suspend-param = <0x00000002>;
287 entry-latency-us = <79>;
288 exit-latency-us = <82>;
289 min-residency-us = <1302>;
292 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
293 compatible = "arm,idle-state";
294 idle-state-name = "big-power-collapse";
296 arm,psci-suspend-param = <0x40000003>;
297 entry-latency-us = <724>;
298 exit-latency-us = <2027>;
299 min-residency-us = <9419>;
300 local-timer-stop;
307 compatible = "qcom,scm-msm8998", "qcom,scm";
312 compatible = "arm,psci-1.0";
316 rpm-glink {
317 compatible = "qcom,glink-rpm";
320 qcom,rpm-msg-ram = <&rpm_msg_ram>;
323 rpm_requests: rpm-requests {
324 compatible = "qcom,rpm-msm8998";
325 qcom,glink-channels = "rpm_requests";
327 rpmcc: clock-controller {
328 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
329 #clock-cells = <1>;
332 rpmpd: power-controller {
333 compatible = "qcom,msm8998-rpmpd";
334 #power-domain-cells = <1>;
335 operating-points-v2 = <&rpmpd_opp_table>;
337 rpmpd_opp_table: opp-table {
338 compatible = "operating-points-v2";
341 opp-level = <RPM_SMD_LEVEL_RETENTION>;
345 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
349 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
353 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
357 opp-level = <RPM_SMD_LEVEL_SVS>;
361 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
365 opp-level = <RPM_SMD_LEVEL_NOM>;
369 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
373 opp-level = <RPM_SMD_LEVEL_TURBO>;
377 opp-level = <RPM_SMD_LEVEL_BINNING>;
386 memory-region = <&smem_mem>;
390 smp2p-lpass {
398 qcom,local-pid = <0>;
399 qcom,remote-pid = <2>;
401 adsp_smp2p_out: master-kernel {
402 qcom,entry-name = "master-kernel";
403 #qcom,smem-state-cells = <1>;
406 adsp_smp2p_in: slave-kernel {
407 qcom,entry-name = "slave-kernel";
409 interrupt-controller;
410 #interrupt-cells = <2>;
414 smp2p-mpss {
419 qcom,local-pid = <0>;
420 qcom,remote-pid = <1>;
422 modem_smp2p_out: master-kernel {
423 qcom,entry-name = "master-kernel";
424 #qcom,smem-state-cells = <1>;
427 modem_smp2p_in: slave-kernel {
428 qcom,entry-name = "slave-kernel";
429 interrupt-controller;
430 #interrupt-cells = <2>;
434 smp2p-slpi {
439 qcom,local-pid = <0>;
440 qcom,remote-pid = <3>;
442 slpi_smp2p_out: master-kernel {
443 qcom,entry-name = "master-kernel";
444 #qcom,smem-state-cells = <1>;
447 slpi_smp2p_in: slave-kernel {
448 qcom,entry-name = "slave-kernel";
449 interrupt-controller;
450 #interrupt-cells = <2>;
454 thermal-zones {
455 cpu0-thermal {
456 polling-delay-passive = <250>;
457 polling-delay = <1000>;
459 thermal-sensors = <&tsens0 1>;
462 cpu0_alert0: trip-point0 {
476 cpu1-thermal {
477 polling-delay-passive = <250>;
478 polling-delay = <1000>;
480 thermal-sensors = <&tsens0 2>;
483 cpu1_alert0: trip-point0 {
497 cpu2-thermal {
498 polling-delay-passive = <250>;
499 polling-delay = <1000>;
501 thermal-sensors = <&tsens0 3>;
504 cpu2_alert0: trip-point0 {
518 cpu3-thermal {
519 polling-delay-passive = <250>;
520 polling-delay = <1000>;
522 thermal-sensors = <&tsens0 4>;
525 cpu3_alert0: trip-point0 {
539 cpu4-thermal {
540 polling-delay-passive = <250>;
541 polling-delay = <1000>;
543 thermal-sensors = <&tsens0 7>;
546 cpu4_alert0: trip-point0 {
560 cpu5-thermal {
561 polling-delay-passive = <250>;
562 polling-delay = <1000>;
564 thermal-sensors = <&tsens0 8>;
567 cpu5_alert0: trip-point0 {
581 cpu6-thermal {
582 polling-delay-passive = <250>;
583 polling-delay = <1000>;
585 thermal-sensors = <&tsens0 9>;
588 cpu6_alert0: trip-point0 {
602 cpu7-thermal {
603 polling-delay-passive = <250>;
604 polling-delay = <1000>;
606 thermal-sensors = <&tsens0 10>;
609 cpu7_alert0: trip-point0 {
623 gpu-bottom-thermal {
624 polling-delay-passive = <250>;
625 polling-delay = <1000>;
627 thermal-sensors = <&tsens0 12>;
630 gpu1_alert0: trip-point0 {
638 gpu-top-thermal {
639 polling-delay-passive = <250>;
640 polling-delay = <1000>;
642 thermal-sensors = <&tsens0 13>;
645 gpu2_alert0: trip-point0 {
653 clust0-mhm-thermal {
654 polling-delay-passive = <250>;
655 polling-delay = <1000>;
657 thermal-sensors = <&tsens0 5>;
660 cluster0_mhm_alert0: trip-point0 {
668 clust1-mhm-thermal {
669 polling-delay-passive = <250>;
670 polling-delay = <1000>;
672 thermal-sensors = <&tsens0 6>;
675 cluster1_mhm_alert0: trip-point0 {
683 cluster1-l2-thermal {
684 polling-delay-passive = <250>;
685 polling-delay = <1000>;
687 thermal-sensors = <&tsens0 11>;
690 cluster1_l2_alert0: trip-point0 {
698 modem-thermal {
699 polling-delay-passive = <250>;
700 polling-delay = <1000>;
702 thermal-sensors = <&tsens1 1>;
705 modem_alert0: trip-point0 {
713 mem-thermal {
714 polling-delay-passive = <250>;
715 polling-delay = <1000>;
717 thermal-sensors = <&tsens1 2>;
720 mem_alert0: trip-point0 {
728 wlan-thermal {
729 polling-delay-passive = <250>;
730 polling-delay = <1000>;
732 thermal-sensors = <&tsens1 3>;
735 wlan_alert0: trip-point0 {
743 q6-dsp-thermal {
744 polling-delay-passive = <250>;
745 polling-delay = <1000>;
747 thermal-sensors = <&tsens1 4>;
750 q6_dsp_alert0: trip-point0 {
758 camera-thermal {
759 polling-delay-passive = <250>;
760 polling-delay = <1000>;
762 thermal-sensors = <&tsens1 5>;
765 camera_alert0: trip-point0 {
773 multimedia-thermal {
774 polling-delay-passive = <250>;
775 polling-delay = <1000>;
777 thermal-sensors = <&tsens1 6>;
780 multimedia_alert0: trip-point0 {
790 compatible = "arm,armv8-timer";
798 #address-cells = <1>;
799 #size-cells = <1>;
801 compatible = "simple-bus";
803 gcc: clock-controller@100000 {
804 compatible = "qcom,gcc-msm8998";
805 #clock-cells = <1>;
806 #reset-cells = <1>;
807 #power-domain-cells = <1>;
810 clock-names = "xo", "sleep_clk";
815 * reside as read-only for the HLOS. If the HLOS tried to enable or disable
817 * enabled but unused during boot-up), the device will most likely decide
820 * as protected. The board dts (or a user-supplied dts) can override the
824 protected-clocks = <AGGRE2_SNOC_NORTH_AXI>,
830 compatible = "qcom,rpm-msg-ram";
835 compatible = "qcom,msm8998-qfprom", "qcom,qfprom";
837 #address-cells = <1>;
838 #size-cells = <1>;
840 qusb2_hstx_trim: hstx-trim@23a {
847 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
853 interrupt-names = "uplow", "critical";
854 #thermal-sensor-cells = <1>;
858 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
864 interrupt-names = "uplow", "critical";
865 #thermal-sensor-cells = <1>;
869 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
871 #iommu-cells = <1>;
873 #global-interrupts = <0>;
884 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
886 #iommu-cells = <1>;
888 #global-interrupts = <0>;
903 compatible = "qcom,pcie-msm8996";
908 reg-names = "parf", "dbi", "elbi", "config";
910 linux,pci-domain = <0>;
911 bus-range = <0x00 0xff>;
912 #address-cells = <3>;
913 #size-cells = <2>;
914 num-lanes = <1>;
916 phy-names = "pciephy";
922 #interrupt-cells = <1>;
924 interrupt-names = "msi";
925 interrupt-map-mask = <0 0 0 0x7>;
926 interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>,
936 clock-names = "pipe", "bus_master", "bus_slave", "cfg", "aux";
938 power-domains = <&gcc PCIE_0_GDSC>;
939 iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
940 perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
944 compatible = "qcom,msm8998-qmp-pcie-phy";
946 #address-cells = <1>;
947 #size-cells = <1>;
954 clock-names = "aux", "cfg_ahb", "ref";
957 reset-names = "phy", "common";
959 vdda-phy-supply = <&vreg_l1a_0p875>;
960 vdda-pll-supply = <&vreg_l2a_1p2>;
964 #phy-cells = <0>;
967 clock-names = "pipe0";
968 clock-output-names = "pcie_0_pipe_clk_src";
969 #clock-cells = <0>;
974 compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
978 phy-names = "ufsphy";
979 lanes-per-direction = <2>;
980 power-domains = <&gcc UFS_GDSC>;
982 #reset-cells = <1>;
984 clock-names =
1002 freq-table-hz =
1013 reset-names = "rst";
1017 compatible = "qcom,msm8998-qmp-ufs-phy";
1019 #address-cells = <1>;
1020 #size-cells = <1>;
1024 clock-names =
1031 reset-names = "ufsphy";
1040 #phy-cells = <0>;
1045 compatible = "qcom,tcsr-mutex";
1047 #hwlock-cells = <1>;
1051 compatible = "qcom,msm8998-tcsr", "syscon";
1056 compatible = "qcom,msm8998-pinctrl";
1059 gpio-controller;
1060 #gpio-cells = <2>;
1061 interrupt-controller;
1062 #interrupt-cells = <2>;
1064 sdc2_on: sdc2-on {
1067 drive-strength = <16>;
1068 bias-disable;
1073 drive-strength = <10>;
1074 bias-pull-up;
1079 drive-strength = <10>;
1080 bias-pull-up;
1084 sdc2_off: sdc2-off {
1087 drive-strength = <2>;
1088 bias-disable;
1093 drive-strength = <2>;
1094 bias-pull-up;
1099 drive-strength = <2>;
1100 bias-pull-up;
1104 sdc2_cd: sdc2-cd {
1107 bias-pull-up;
1108 drive-strength = <2>;
1111 blsp1_uart3_on: blsp1-uart3-on {
1115 drive-strength = <2>;
1116 bias-disable;
1122 drive-strength = <2>;
1123 bias-disable;
1129 drive-strength = <2>;
1130 bias-disable;
1136 drive-strength = <2>;
1137 bias-disable;
1141 blsp1_i2c1_default: blsp1-i2c1-default {
1144 drive-strength = <2>;
1145 bias-disable;
1148 blsp1_i2c1_sleep: blsp1-i2c1-sleep {
1151 drive-strength = <2>;
1152 bias-pull-up;
1155 blsp1_i2c2_default: blsp1-i2c2-default {
1158 drive-strength = <2>;
1159 bias-disable;
1162 blsp1_i2c2_sleep: blsp1-i2c2-sleep {
1165 drive-strength = <2>;
1166 bias-pull-up;
1169 blsp1_i2c3_default: blsp1-i2c3-default {
1172 drive-strength = <2>;
1173 bias-disable;
1176 blsp1_i2c3_sleep: blsp1-i2c3-sleep {
1179 drive-strength = <2>;
1180 bias-pull-up;
1183 blsp1_i2c4_default: blsp1-i2c4-default {
1186 drive-strength = <2>;
1187 bias-disable;
1190 blsp1_i2c4_sleep: blsp1-i2c4-sleep {
1193 drive-strength = <2>;
1194 bias-pull-up;
1197 blsp1_i2c5_default: blsp1-i2c5-default {
1200 drive-strength = <2>;
1201 bias-disable;
1204 blsp1_i2c5_sleep: blsp1-i2c5-sleep {
1207 drive-strength = <2>;
1208 bias-pull-up;
1211 blsp1_i2c6_default: blsp1-i2c6-default {
1214 drive-strength = <2>;
1215 bias-disable;
1218 blsp1_i2c6_sleep: blsp1-i2c6-sleep {
1221 drive-strength = <2>;
1222 bias-pull-up;
1225 blsp2_i2c1_default: blsp2-i2c1-default {
1228 drive-strength = <2>;
1229 bias-disable;
1232 blsp2_i2c1_sleep: blsp2-i2c1-sleep {
1235 drive-strength = <2>;
1236 bias-pull-up;
1239 blsp2_i2c2_default: blsp2-i2c2-default {
1242 drive-strength = <2>;
1243 bias-disable;
1246 blsp2_i2c2_sleep: blsp2-i2c2-sleep {
1249 drive-strength = <2>;
1250 bias-pull-up;
1253 blsp2_i2c3_default: blsp2-i2c3-default {
1256 drive-strength = <2>;
1257 bias-disable;
1260 blsp2_i2c3_sleep: blsp2-i2c3-sleep {
1263 drive-strength = <2>;
1264 bias-pull-up;
1267 blsp2_i2c4_default: blsp2-i2c4-default {
1270 drive-strength = <2>;
1271 bias-disable;
1274 blsp2_i2c4_sleep: blsp2-i2c4-sleep {
1277 drive-strength = <2>;
1278 bias-pull-up;
1281 blsp2_i2c5_default: blsp2-i2c5-default {
1284 drive-strength = <2>;
1285 bias-disable;
1288 blsp2_i2c5_sleep: blsp2-i2c5-sleep {
1291 drive-strength = <2>;
1292 bias-pull-up;
1295 blsp2_i2c6_default: blsp2-i2c6-default {
1298 drive-strength = <2>;
1299 bias-disable;
1302 blsp2_i2c6_sleep: blsp2-i2c6-sleep {
1305 drive-strength = <2>;
1306 bias-pull-up;
1311 compatible = "qcom,msm8998-mss-pil";
1313 reg-names = "qdsp6", "rmb";
1315 interrupts-extended =
1322 interrupt-names = "wdog", "fatal", "ready",
1323 "handover", "stop-ack",
1324 "shutdown-ack";
1334 clock-names = "iface", "bus", "mem", "gpll0_mss",
1337 qcom,smem-states = <&modem_smp2p_out 0>;
1338 qcom,smem-state-names = "stop";
1341 reset-names = "mss_restart";
1343 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
1345 power-domains = <&rpmpd MSM8998_VDDCX>,
1347 power-domain-names = "cx", "mx";
1352 memory-region = <&mba_mem>;
1356 memory-region = <&mpss_mem>;
1359 glink-edge {
1362 qcom,remote-pid = <1>;
1368 compatible = "qcom,adreno-540.1", "qcom,adreno";
1370 reg-names = "kgsl_3d0_reg_memory";
1378 clock-names = "iface",
1387 operating-points-v2 = <&gpu_opp_table>;
1388 power-domains = <&rpmpd MSM8998_VDDMX>;
1391 gpu_opp_table: opp-table {
1392 compatible = "operating-points-v2";
1393 opp-710000097 {
1394 opp-hz = /bits/ 64 <710000097>;
1395 opp-level = <RPM_SMD_LEVEL_TURBO>;
1396 opp-supported-hw = <0xFF>;
1399 opp-670000048 {
1400 opp-hz = /bits/ 64 <670000048>;
1401 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
1402 opp-supported-hw = <0xFF>;
1405 opp-596000097 {
1406 opp-hz = /bits/ 64 <596000097>;
1407 opp-level = <RPM_SMD_LEVEL_NOM>;
1408 opp-supported-hw = <0xFF>;
1411 opp-515000097 {
1412 opp-hz = /bits/ 64 <515000097>;
1413 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
1414 opp-supported-hw = <0xFF>;
1417 opp-414000000 {
1418 opp-hz = /bits/ 64 <414000000>;
1419 opp-level = <RPM_SMD_LEVEL_SVS>;
1420 opp-supported-hw = <0xFF>;
1423 opp-342000000 {
1424 opp-hz = /bits/ 64 <342000000>;
1425 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
1426 opp-supported-hw = <0xFF>;
1429 opp-257000000 {
1430 opp-hz = /bits/ 64 <257000000>;
1431 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
1432 opp-supported-hw = <0xFF>;
1438 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
1443 clock-names = "iface", "mem", "mem_iface";
1445 #global-interrupts = <0>;
1446 #iommu-cells = <1>;
1452 * GPU-GX GDSC's parent is GPU-CX. We need to bring up the
1453 * GPU-CX for SMMU but we need both of them up for Adreno.
1459 power-domains = <&gpucc GPU_GX_GDSC>;
1463 gpucc: clock-controller@5065000 {
1464 compatible = "qcom,msm8998-gpucc";
1465 #clock-cells = <1>;
1466 #reset-cells = <1>;
1467 #power-domain-cells = <1>;
1472 clock-names = "xo",
1477 compatible = "qcom,msm8998-slpi-pas";
1480 interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>,
1485 interrupt-names = "wdog", "fatal", "ready",
1486 "handover", "stop-ack";
1488 px-supply = <&vreg_lvs2a_1p8>;
1492 clock-names = "xo", "aggre2";
1494 memory-region = <&slpi_mem>;
1496 qcom,smem-states = <&slpi_smp2p_out 0>;
1497 qcom,smem-state-names = "stop";
1499 power-domains = <&rpmpd MSM8998_SSCCX>;
1500 power-domain-names = "ssc_cx";
1504 glink-edge {
1507 qcom,remote-pid = <3>;
1513 compatible = "arm,coresight-stm", "arm,primecell";
1516 reg-names = "stm-base", "stm-data-base";
1520 clock-names = "apb_pclk", "atclk";
1522 out-ports {
1525 remote-endpoint = <&funnel0_in7>;
1532 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1537 clock-names = "apb_pclk", "atclk";
1539 out-ports {
1542 remote-endpoint =
1548 in-ports {
1549 #address-cells = <1>;
1550 #size-cells = <0>;
1555 remote-endpoint = <&stm_out>;
1562 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1567 clock-names = "apb_pclk", "atclk";
1569 out-ports {
1572 remote-endpoint =
1578 in-ports {
1579 #address-cells = <1>;
1580 #size-cells = <0>;
1585 remote-endpoint =
1593 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1598 clock-names = "apb_pclk", "atclk";
1600 out-ports {
1603 remote-endpoint =
1609 in-ports {
1610 #address-cells = <1>;
1611 #size-cells = <0>;
1616 remote-endpoint =
1624 remote-endpoint =
1632 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1637 clock-names = "apb_pclk", "atclk";
1639 out-ports {
1642 remote-endpoint = <&etr_in>;
1647 in-ports {
1650 remote-endpoint = <&etf_out>;
1657 compatible = "arm,coresight-tmc", "arm,primecell";
1662 clock-names = "apb_pclk", "atclk";
1664 out-ports {
1667 remote-endpoint =
1673 in-ports {
1676 remote-endpoint =
1684 compatible = "arm,coresight-tmc", "arm,primecell";
1689 clock-names = "apb_pclk", "atclk";
1690 arm,scatter-gather;
1692 in-ports {
1695 remote-endpoint =
1703 compatible = "arm,coresight-etm4x", "arm,primecell";
1708 clock-names = "apb_pclk", "atclk";
1712 out-ports {
1715 remote-endpoint =
1723 compatible = "arm,coresight-etm4x", "arm,primecell";
1728 clock-names = "apb_pclk", "atclk";
1732 out-ports {
1735 remote-endpoint =
1743 compatible = "arm,coresight-etm4x", "arm,primecell";
1748 clock-names = "apb_pclk", "atclk";
1752 out-ports {
1755 remote-endpoint =
1763 compatible = "arm,coresight-etm4x", "arm,primecell";
1768 clock-names = "apb_pclk", "atclk";
1772 out-ports {
1775 remote-endpoint =
1783 compatible = "arm,coresight-etm4x", "arm,primecell";
1788 clock-names = "apb_pclk", "atclk";
1790 out-ports {
1793 remote-endpoint =
1799 in-ports {
1800 #address-cells = <1>;
1801 #size-cells = <0>;
1806 remote-endpoint =
1814 remote-endpoint =
1822 remote-endpoint =
1830 remote-endpoint =
1838 remote-endpoint =
1846 remote-endpoint =
1854 remote-endpoint =
1862 remote-endpoint =
1870 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1875 clock-names = "apb_pclk", "atclk";
1877 out-ports {
1880 remote-endpoint =
1886 in-ports {
1889 remote-endpoint =
1897 compatible = "arm,coresight-etm4x", "arm,primecell";
1902 clock-names = "apb_pclk", "atclk";
1908 remote-endpoint = <&apss_funnel_in4>;
1914 compatible = "arm,coresight-etm4x", "arm,primecell";
1919 clock-names = "apb_pclk", "atclk";
1925 remote-endpoint = <&apss_funnel_in5>;
1931 compatible = "arm,coresight-etm4x", "arm,primecell";
1936 clock-names = "apb_pclk", "atclk";
1942 remote-endpoint = <&apss_funnel_in6>;
1948 compatible = "arm,coresight-etm4x", "arm,primecell";
1953 clock-names = "apb_pclk", "atclk";
1959 remote-endpoint = <&apss_funnel_in7>;
1965 compatible = "qcom,rpm-stats";
1970 compatible = "qcom,spmi-pmic-arb";
1976 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1977 interrupt-names = "periph_irq";
1981 #address-cells = <2>;
1982 #size-cells = <0>;
1983 interrupt-controller;
1984 #interrupt-cells = <4>;
1985 cell-index = <0>;
1989 compatible = "qcom,msm8998-dwc3", "qcom,dwc3";
1992 #address-cells = <1>;
1993 #size-cells = <1>;
2001 clock-names = "cfg_noc",
2007 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2009 assigned-clock-rates = <19200000>, <120000000>;
2013 interrupt-names = "hs_phy_irq", "ss_phy_irq";
2015 power-domains = <&gcc USB_30_GDSC>;
2026 phy-names = "usb2-phy", "usb3-phy";
2027 snps,has-lpm-erratum;
2028 snps,hird-threshold = /bits/ 8 <0x10>;
2033 compatible = "qcom,msm8998-qmp-usb3-phy";
2036 #address-cells = <1>;
2037 #size-cells = <1>;
2043 clock-names = "aux", "cfg_ahb", "ref";
2047 reset-names = "phy", "common";
2055 #phy-cells = <0>;
2056 #clock-cells = <0>;
2058 clock-names = "pipe0";
2059 clock-output-names = "usb3_phy_pipe_clk_src";
2064 compatible = "qcom,msm8998-qusb2-phy";
2067 #phy-cells = <0>;
2071 clock-names = "cfg_ahb", "ref";
2075 nvmem-cells = <&qusb2_hstx_trim>;
2079 compatible = "qcom,msm8998-sdhci", "qcom,sdhci-msm-v4";
2081 reg-names = "hc", "core";
2085 interrupt-names = "hc_irq", "pwr_irq";
2087 clock-names = "iface", "core", "xo";
2091 bus-width = <4>;
2095 blsp1_dma: dma-controller@c144000 {
2096 compatible = "qcom,bam-v1.7.0";
2100 clock-names = "bam_clk";
2101 #dma-cells = <1>;
2103 qcom,controlled-remotely;
2104 num-channels = <18>;
2105 qcom,num-ees = <4>;
2109 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2114 clock-names = "core", "iface";
2116 dma-names = "tx", "rx";
2117 pinctrl-names = "default";
2118 pinctrl-0 = <&blsp1_uart3_on>;
2123 compatible = "qcom,i2c-qup-v2.2.1";
2129 clock-names = "core", "iface";
2131 dma-names = "tx", "rx";
2132 pinctrl-names = "default", "sleep";
2133 pinctrl-0 = <&blsp1_i2c1_default>;
2134 pinctrl-1 = <&blsp1_i2c1_sleep>;
2135 clock-frequency = <400000>;
2138 #address-cells = <1>;
2139 #size-cells = <0>;
2143 compatible = "qcom,i2c-qup-v2.2.1";
2149 clock-names = "core", "iface";
2151 dma-names = "tx", "rx";
2152 pinctrl-names = "default", "sleep";
2153 pinctrl-0 = <&blsp1_i2c2_default>;
2154 pinctrl-1 = <&blsp1_i2c2_sleep>;
2155 clock-frequency = <400000>;
2158 #address-cells = <1>;
2159 #size-cells = <0>;
2163 compatible = "qcom,i2c-qup-v2.2.1";
2169 clock-names = "core", "iface";
2171 dma-names = "tx", "rx";
2172 pinctrl-names = "default", "sleep";
2173 pinctrl-0 = <&blsp1_i2c3_default>;
2174 pinctrl-1 = <&blsp1_i2c3_sleep>;
2175 clock-frequency = <400000>;
2178 #address-cells = <1>;
2179 #size-cells = <0>;
2183 compatible = "qcom,i2c-qup-v2.2.1";
2189 clock-names = "core", "iface";
2191 dma-names = "tx", "rx";
2192 pinctrl-names = "default", "sleep";
2193 pinctrl-0 = <&blsp1_i2c4_default>;
2194 pinctrl-1 = <&blsp1_i2c4_sleep>;
2195 clock-frequency = <400000>;
2198 #address-cells = <1>;
2199 #size-cells = <0>;
2203 compatible = "qcom,i2c-qup-v2.2.1";
2209 clock-names = "core", "iface";
2211 dma-names = "tx", "rx";
2212 pinctrl-names = "default", "sleep";
2213 pinctrl-0 = <&blsp1_i2c5_default>;
2214 pinctrl-1 = <&blsp1_i2c5_sleep>;
2215 clock-frequency = <400000>;
2218 #address-cells = <1>;
2219 #size-cells = <0>;
2223 compatible = "qcom,i2c-qup-v2.2.1";
2229 clock-names = "core", "iface";
2231 dma-names = "tx", "rx";
2232 pinctrl-names = "default", "sleep";
2233 pinctrl-0 = <&blsp1_i2c6_default>;
2234 pinctrl-1 = <&blsp1_i2c6_sleep>;
2235 clock-frequency = <400000>;
2238 #address-cells = <1>;
2239 #size-cells = <0>;
2242 blsp2_dma: dma-controller@c184000 {
2243 compatible = "qcom,bam-v1.7.0";
2247 clock-names = "bam_clk";
2248 #dma-cells = <1>;
2250 qcom,controlled-remotely;
2251 num-channels = <18>;
2252 qcom,num-ees = <4>;
2256 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2261 clock-names = "core", "iface";
2266 compatible = "qcom,i2c-qup-v2.2.1";
2272 clock-names = "core", "iface";
2274 dma-names = "tx", "rx";
2275 pinctrl-names = "default", "sleep";
2276 pinctrl-0 = <&blsp2_i2c1_default>;
2277 pinctrl-1 = <&blsp2_i2c1_sleep>;
2278 clock-frequency = <400000>;
2281 #address-cells = <1>;
2282 #size-cells = <0>;
2286 compatible = "qcom,i2c-qup-v2.2.1";
2292 clock-names = "core", "iface";
2294 dma-names = "tx", "rx";
2295 pinctrl-names = "default", "sleep";
2296 pinctrl-0 = <&blsp2_i2c2_default>;
2297 pinctrl-1 = <&blsp2_i2c2_sleep>;
2298 clock-frequency = <400000>;
2301 #address-cells = <1>;
2302 #size-cells = <0>;
2306 compatible = "qcom,i2c-qup-v2.2.1";
2312 clock-names = "core", "iface";
2314 dma-names = "tx", "rx";
2315 pinctrl-names = "default", "sleep";
2316 pinctrl-0 = <&blsp2_i2c3_default>;
2317 pinctrl-1 = <&blsp2_i2c3_sleep>;
2318 clock-frequency = <400000>;
2321 #address-cells = <1>;
2322 #size-cells = <0>;
2326 compatible = "qcom,i2c-qup-v2.2.1";
2332 clock-names = "core", "iface";
2334 dma-names = "tx", "rx";
2335 pinctrl-names = "default", "sleep";
2336 pinctrl-0 = <&blsp2_i2c4_default>;
2337 pinctrl-1 = <&blsp2_i2c4_sleep>;
2338 clock-frequency = <400000>;
2341 #address-cells = <1>;
2342 #size-cells = <0>;
2346 compatible = "qcom,i2c-qup-v2.2.1";
2352 clock-names = "core", "iface";
2354 dma-names = "tx", "rx";
2355 pinctrl-names = "default", "sleep";
2356 pinctrl-0 = <&blsp2_i2c5_default>;
2357 pinctrl-1 = <&blsp2_i2c5_sleep>;
2358 clock-frequency = <400000>;
2361 #address-cells = <1>;
2362 #size-cells = <0>;
2366 compatible = "qcom,i2c-qup-v2.2.1";
2372 clock-names = "core", "iface";
2374 dma-names = "tx", "rx";
2375 pinctrl-names = "default", "sleep";
2376 pinctrl-0 = <&blsp2_i2c6_default>;
2377 pinctrl-1 = <&blsp2_i2c6_sleep>;
2378 clock-frequency = <400000>;
2381 #address-cells = <1>;
2382 #size-cells = <0>;
2385 mmcc: clock-controller@c8c0000 {
2386 compatible = "qcom,mmcc-msm8998";
2387 #clock-cells = <1>;
2388 #reset-cells = <1>;
2389 #power-domain-cells = <1>;
2392 clock-names = "xo",
2415 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
2417 #iommu-cells = <1>;
2423 clock-names = "iface-mm", "iface-smmu",
2424 "bus-mm", "bus-smmu";
2426 #global-interrupts = <0>;
2451 compatible = "qcom,msm8998-adsp-pas";
2454 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
2459 interrupt-names = "wdog", "fatal", "ready",
2460 "handover", "stop-ack";
2463 clock-names = "xo";
2465 memory-region = <&adsp_mem>;
2467 qcom,smem-states = <&adsp_smp2p_out 0>;
2468 qcom,smem-state-names = "stop";
2470 power-domains = <&rpmpd MSM8998_VDDCX>;
2471 power-domain-names = "cx";
2475 glink-edge {
2478 qcom,remote-pid = <2>;
2484 compatible = "qcom,msm8998-apcs-hmss-global";
2487 #mbox-cells = <1>;
2491 #address-cells = <1>;
2492 #size-cells = <1>;
2494 compatible = "arm,armv7-timer-mem";
2498 frame-number = <0>;
2506 frame-number = <1>;
2513 frame-number = <2>;
2520 frame-number = <3>;
2527 frame-number = <4>;
2534 frame-number = <5>;
2541 frame-number = <6>;
2548 intc: interrupt-controller@17a00000 {
2549 compatible = "arm,gic-v3";
2552 #interrupt-cells = <3>;
2553 #address-cells = <1>;
2554 #size-cells = <1>;
2556 interrupt-controller;
2557 #redistributor-regions = <1>;
2558 redistributor-stride = <0x0 0x20000>;
2563 compatible = "qcom,wcn3990-wifi";
2566 reg-names = "membase";
2567 memory-region = <&wlan_msa_mem>;
2569 clock-names = "cxo_ref_clk_pin";
2585 qcom,snoc-host-cap-8bit-quirk;