Lines Matching +full:0 +full:xd00000
15 qcom,msm-id = <292 0x0>;
25 reg = <0x0 0x80000000 0x0 0x0>;
34 reg = <0x0 0x85800000 0x0 0x600000>;
39 reg = <0x0 0x85e00000 0x0 0x100000>;
44 reg = <0x0 0x86000000 0x0 0x200000>;
49 reg = <0x0 0x86200000 0x0 0x2d00000>;
55 reg = <0x0 0x88f00000 0x0 0x200000>;
63 reg = <0x0 0x8ab00000 0x0 0x700000>;
68 reg = <0x0 0x8b200000 0x0 0x1a00000>;
73 reg = <0x0 0x8cc00000 0x0 0x7000000>;
78 reg = <0x0 0x93c00000 0x0 0x500000>;
83 reg = <0x0 0x94100000 0x0 0x200000>;
88 reg = <0x0 0x94300000 0x0 0xf00000>;
93 reg = <0x0 0x95200000 0x0 0x10000>;
98 reg = <0x0 0x95210000 0x0 0x5000>;
103 reg = <0x0 0x95600000 0x0 0x100000>;
108 reg = <0x0 0x95700000 0x0 0x100000>;
116 #clock-cells = <0>;
123 #clock-cells = <0>;
130 #size-cells = <0>;
132 CPU0: cpu@0 {
135 reg = <0x0 0x0>;
149 reg = <0x0 0x1>;
159 reg = <0x0 0x2>;
169 reg = <0x0 0x3>;
179 reg = <0x0 0x100>;
193 reg = <0x0 0x101>;
203 reg = <0x0 0x102>;
213 reg = <0x0 0x103>;
261 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
265 arm,psci-suspend-param = <0x00000002>;
271 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
275 arm,psci-suspend-param = <0x40000003>;
282 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
286 arm,psci-suspend-param = <0x00000002>;
296 arm,psci-suspend-param = <0x40000003>;
321 mboxes = <&apcs_glb 0>;
398 qcom,local-pid = <0>;
419 qcom,local-pid = <0>;
439 qcom,local-pid = <0>;
794 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
800 ranges = <0 0 0 0xffffffff>;
808 reg = <0x00100000 0xb0000>;
831 reg = <0x00778000 0x7000>;
836 reg = <0x00784000 0x621c>;
841 reg = <0x23a 0x1>;
842 bits = <0 4>;
848 reg = <0x010ab000 0x1000>, /* TM */
849 <0x010aa000 0x1000>; /* SROT */
859 reg = <0x010ae000 0x1000>, /* TM */
860 <0x010ad000 0x1000>; /* SROT */
870 reg = <0x01680000 0x10000>;
873 #global-interrupts = <0>;
885 reg = <0x016c0000 0x40000>;
888 #global-interrupts = <0>;
904 reg = <0x01c00000 0x2000>,
905 <0x1b000000 0xf1d>,
906 <0x1b000f20 0xa8>,
907 <0x1b100000 0x100000>;
910 linux,pci-domain = <0>;
911 bus-range = <0x00 0xff>;
919 ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>,
920 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
925 interrupt-map-mask = <0 0 0 0x7>;
926 interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>,
927 <0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>,
928 <0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>,
929 <0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>;
939 iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
945 reg = <0x01c06000 0x18c>;
963 reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>;
964 #phy-cells = <0>;
969 #clock-cells = <0>;
975 reg = <0x01da4000 0x2500>;
1004 <0 0>,
1005 <0 0>,
1007 <0 0>,
1008 <0 0>,
1009 <0 0>,
1010 <0 0>;
1018 reg = <0x01da7000 0x18c>;
1032 resets = <&ufshc 0>;
1035 reg = <0x01da7400 0x128>,
1036 <0x01da7600 0x1fc>,
1037 <0x01da7c00 0x1dc>,
1038 <0x01da7800 0x128>,
1039 <0x01da7a00 0x1fc>;
1040 #phy-cells = <0>;
1046 reg = <0x01f40000 0x20000>;
1052 reg = <0x01f60000 0x20000>;
1057 reg = <0x03400000 0xc00000>;
1312 reg = <0x04080000 0x100>, <0x04180000 0x20>;
1317 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1337 qcom,smem-states = <&modem_smp2p_out 0>;
1343 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
1369 reg = <0x05000000 0x40000>;
1385 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
1386 iommus = <&adreno_smmu 0>;
1396 opp-supported-hw = <0xFF>;
1402 opp-supported-hw = <0xFF>;
1408 opp-supported-hw = <0xFF>;
1414 opp-supported-hw = <0xFF>;
1420 opp-supported-hw = <0xFF>;
1426 opp-supported-hw = <0xFF>;
1432 opp-supported-hw = <0xFF>;
1439 reg = <0x05040000 0x10000>;
1445 #global-interrupts = <0>;
1468 reg = <0x05065000 0x9000>;
1478 reg = <0x05800000 0x4040>;
1481 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1496 qcom,smem-states = <&slpi_smp2p_out 0>;
1514 reg = <0x06002000 0x1000>,
1515 <0x16280000 0x180000>;
1533 reg = <0x06041000 0x1000>;
1550 #size-cells = <0>;
1563 reg = <0x06042000 0x1000>;
1580 #size-cells = <0>;
1594 reg = <0x06045000 0x1000>;
1611 #size-cells = <0>;
1613 port@0 {
1614 reg = <0>;
1633 reg = <0x06046000 0x1000>;
1658 reg = <0x06047000 0x1000>;
1685 reg = <0x06048000 0x1000>;
1704 reg = <0x07840000 0x1000>;
1724 reg = <0x07940000 0x1000>;
1744 reg = <0x07a40000 0x1000>;
1764 reg = <0x07b40000 0x1000>;
1784 reg = <0x07b60000 0x1000>;
1801 #size-cells = <0>;
1803 port@0 {
1804 reg = <0>;
1871 reg = <0x07b70000 0x1000>;
1898 reg = <0x07c40000 0x1000>;
1915 reg = <0x07d40000 0x1000>;
1932 reg = <0x07e40000 0x1000>;
1949 reg = <0x07f40000 0x1000>;
1966 reg = <0x00290000 0x10000>;
1971 reg = <0x0800f000 0x1000>,
1972 <0x08400000 0x1000000>,
1973 <0x09400000 0x1000000>,
1974 <0x0a400000 0x220000>,
1975 <0x0800a000 0x3000>;
1979 qcom,ee = <0>;
1980 qcom,channel = <0>;
1982 #size-cells = <0>;
1985 cell-index = <0>;
1990 reg = <0x0a8f8800 0x400>;
2021 reg = <0x0a800000 0xcd00>;
2028 snps,hird-threshold = /bits/ 8 <0x10>;
2034 reg = <0x0c010000 0x18c>;
2050 reg = <0xc010200 0x128>,
2051 <0xc010400 0x200>,
2052 <0xc010c00 0x20c>,
2053 <0xc010600 0x128>,
2054 <0xc010800 0x200>;
2055 #phy-cells = <0>;
2056 #clock-cells = <0>;
2065 reg = <0x0c012000 0x2a8>;
2067 #phy-cells = <0>;
2080 reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>;
2097 reg = <0x0c144000 0x25000>;
2102 qcom,ee = <0>;
2110 reg = <0x0c171000 0x1000>;
2118 pinctrl-0 = <&blsp1_uart3_on>;
2124 reg = <0x0c175000 0x600>;
2133 pinctrl-0 = <&blsp1_i2c1_default>;
2139 #size-cells = <0>;
2144 reg = <0x0c176000 0x600>;
2153 pinctrl-0 = <&blsp1_i2c2_default>;
2159 #size-cells = <0>;
2164 reg = <0x0c177000 0x600>;
2173 pinctrl-0 = <&blsp1_i2c3_default>;
2179 #size-cells = <0>;
2184 reg = <0x0c178000 0x600>;
2193 pinctrl-0 = <&blsp1_i2c4_default>;
2199 #size-cells = <0>;
2204 reg = <0x0c179000 0x600>;
2213 pinctrl-0 = <&blsp1_i2c5_default>;
2219 #size-cells = <0>;
2224 reg = <0x0c17a000 0x600>;
2233 pinctrl-0 = <&blsp1_i2c6_default>;
2239 #size-cells = <0>;
2244 reg = <0x0c184000 0x25000>;
2249 qcom,ee = <0>;
2257 reg = <0x0c1b0000 0x1000>;
2267 reg = <0x0c1b5000 0x600>;
2276 pinctrl-0 = <&blsp2_i2c1_default>;
2282 #size-cells = <0>;
2287 reg = <0x0c1b6000 0x600>;
2296 pinctrl-0 = <&blsp2_i2c2_default>;
2302 #size-cells = <0>;
2307 reg = <0x0c1b7000 0x600>;
2316 pinctrl-0 = <&blsp2_i2c3_default>;
2322 #size-cells = <0>;
2327 reg = <0x0c1b8000 0x600>;
2336 pinctrl-0 = <&blsp2_i2c4_default>;
2342 #size-cells = <0>;
2347 reg = <0x0c1b9000 0x600>;
2356 pinctrl-0 = <&blsp2_i2c5_default>;
2362 #size-cells = <0>;
2367 reg = <0x0c1ba000 0x600>;
2376 pinctrl-0 = <&blsp2_i2c6_default>;
2382 #size-cells = <0>;
2390 reg = <0xc8c0000 0x40000>;
2404 <0>,
2405 <0>,
2406 <0>,
2407 <0>,
2408 <0>,
2409 <0>,
2410 <0>,
2411 <0>;
2416 reg = <0x0cd00000 0x40000>;
2426 #global-interrupts = <0>;
2452 reg = <0x17300000 0x4040>;
2455 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2467 qcom,smem-states = <&adsp_smp2p_out 0>;
2485 reg = <0x17911000 0x1000>;
2495 reg = <0x17920000 0x1000>;
2498 frame-number = <0>;
2501 reg = <0x17921000 0x1000>,
2502 <0x17922000 0x1000>;
2508 reg = <0x17923000 0x1000>;
2515 reg = <0x17924000 0x1000>;
2522 reg = <0x17925000 0x1000>;
2529 reg = <0x17926000 0x1000>;
2536 reg = <0x17927000 0x1000>;
2543 reg = <0x17928000 0x1000>;
2550 reg = <0x17a00000 0x10000>, /* GICD */
2551 <0x17b00000 0x100000>; /* GICR * 8 */
2558 redistributor-stride = <0x0 0x20000>;
2565 reg = <0x18800000 0x800000>;
2583 iommus = <&anoc2_smmu 0x1900>,
2584 <&anoc2_smmu 0x1901>;