Lines Matching refs:gcc
6 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
593 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
594 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
595 <&gcc GCC_PCIE_CLKREF_CLK>;
598 resets = <&gcc GCC_PCIE_PHY_BCR>,
599 <&gcc GCC_PCIE_PHY_COM_BCR>,
600 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
610 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
612 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
626 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
628 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
642 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
644 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
684 clocks = <&gcc GCC_PRNG_AHB_CLK>;
688 gcc: clock-controller@300000 { label
689 compatible = "qcom,gcc-msm8996";
750 clocks = <&gcc GCC_CE1_CLK>;
760 clocks = <&gcc GCC_CE1_AHB_CLK>,
761 <&gcc GCC_CE1_AXI_CLK>,
762 <&gcc GCC_CE1_CLK>;
793 clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>,
794 <&gcc GCC_AGGRE0_CNOC_AHB_CLK>,
795 <&gcc GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK>;
796 power-domains = <&gcc AGGRE0_NOC_GDSC>;
859 <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>,
860 <&gcc GPLL0>,
1165 <&gcc GCC_HDMI_CLKREF_CLK>,
1188 <&gcc GCC_BIMC_GFX_CLK>,
1189 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
1785 power-domains = <&gcc AGGRE0_NOC_GDSC>;
1794 power-domains = <&gcc PCIE0_GDSC>;
1829 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1830 <&gcc GCC_PCIE_0_AUX_CLK>,
1831 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1832 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1833 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
1845 power-domains = <&gcc PCIE1_GDSC>;
1883 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1884 <&gcc GCC_PCIE_1_AUX_CLK>,
1885 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1886 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1887 <&gcc GCC_PCIE_1_SLV_AXI_CLK>;
1898 power-domains = <&gcc PCIE2_GDSC>;
1933 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
1934 <&gcc GCC_PCIE_2_AUX_CLK>,
1935 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
1936 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
1937 <&gcc GCC_PCIE_2_SLV_AXI_CLK>;
1956 power-domains = <&gcc UFS_GDSC>;
1971 <&gcc UFS_AXI_CLK_SRC>,
1972 <&gcc GCC_UFS_AXI_CLK>,
1973 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
1974 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
1975 <&gcc GCC_UFS_AHB_CLK>,
1976 <&gcc UFS_ICE_CORE_CLK_SRC>,
1977 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
1978 <&gcc GCC_UFS_ICE_CORE_CLK>,
1980 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
1981 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
2011 clocks = <&gcc GCC_UFS_CLKREF_CLK>;
2209 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
2322 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
2339 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
2340 <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
2399 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
2400 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
2401 <&gcc GCC_BOOT_ROM_AHB_CLK>,
2403 <&gcc GCC_MSS_GPLL0_DIV_CLK>,
2404 <&gcc GCC_MSS_SNOC_AXI_CLK>,
2405 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
2411 resets = <&gcc GCC_MSS_RESTART>;
2932 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
2933 <&gcc GCC_USB30_MASTER_CLK>,
2934 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
2935 <&gcc GCC_USB30_SLEEP_CLK>,
2936 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
2943 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2944 <&gcc GCC_USB30_MASTER_CLK>;
2951 power-domains = <&gcc USB30_GDSC>;
2972 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
2973 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2974 <&gcc GCC_USB3_CLKREF_CLK>;
2977 resets = <&gcc GCC_USB3_PHY_BCR>,
2978 <&gcc GCC_USB3PHY_PHY_BCR>;
2990 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
3000 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3001 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
3004 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3014 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3015 <&gcc GCC_RX2_USB2_CLKREF_CLK>;
3018 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3033 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
3034 <&gcc GCC_SDCC1_APPS_CLK>,
3036 resets = <&gcc GCC_SDCC1_BCR>;
3057 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3058 <&gcc GCC_SDCC2_APPS_CLK>,
3060 resets = <&gcc GCC_SDCC2_BCR>;
3074 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
3085 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
3086 <&gcc GCC_BLSP1_AHB_CLK>;
3100 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
3101 <&gcc GCC_BLSP1_AHB_CLK>;
3117 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
3118 <&gcc GCC_BLSP1_AHB_CLK>;
3134 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
3145 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
3146 <&gcc GCC_BLSP2_AHB_CLK>;
3155 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
3156 <&gcc GCC_BLSP2_AHB_CLK>;
3165 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
3166 <&gcc GCC_BLSP2_AHB_CLK>;
3182 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
3183 <&gcc GCC_BLSP2_AHB_CLK>;
3199 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
3200 <&gcc GCC_BLSP2_AHB_CLK>;
3217 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
3218 <&gcc GCC_BLSP2_AHB_CLK>;
3233 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
3234 <&gcc GCC_BLSP2_AHB_CLK>;
3250 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
3251 <&gcc GCC_BLSP2_AHB_CLK>;
3270 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
3271 <&gcc GCC_USB20_MASTER_CLK>,
3272 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
3273 <&gcc GCC_USB20_SLEEP_CLK>,
3274 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
3281 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
3282 <&gcc GCC_USB20_MASTER_CLK>;
3285 power-domains = <&gcc USB30_GDSC>;
3389 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;