Lines Matching +full:q6afe +full:- +full:clocks
1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/interconnect/qcom,msm8996.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/soc/qcom,apr.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&intc>;
18 #address-cells = <2>;
19 #size-cells = <2>;
23 clocks {
24 xo_board: xo-board {
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
27 clock-frequency = <19200000>;
28 clock-output-names = "xo_board";
31 sleep_clk: sleep-clk {
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
34 clock-frequency = <32764>;
35 clock-output-names = "sleep_clk";
40 #address-cells = <2>;
41 #size-cells = <0>;
47 enable-method = "psci";
48 cpu-idle-states = <&CPU_SLEEP_0>;
49 capacity-dmips-mhz = <1024>;
50 clocks = <&kryocc 0>;
51 operating-points-v2 = <&cluster0_opp>;
52 #cooling-cells = <2>;
53 next-level-cache = <&L2_0>;
54 L2_0: l2-cache {
56 cache-level = <2>;
64 enable-method = "psci";
65 cpu-idle-states = <&CPU_SLEEP_0>;
66 capacity-dmips-mhz = <1024>;
67 clocks = <&kryocc 0>;
68 operating-points-v2 = <&cluster0_opp>;
69 #cooling-cells = <2>;
70 next-level-cache = <&L2_0>;
77 enable-method = "psci";
78 cpu-idle-states = <&CPU_SLEEP_0>;
79 capacity-dmips-mhz = <1024>;
80 clocks = <&kryocc 1>;
81 operating-points-v2 = <&cluster1_opp>;
82 #cooling-cells = <2>;
83 next-level-cache = <&L2_1>;
84 L2_1: l2-cache {
86 cache-level = <2>;
94 enable-method = "psci";
95 cpu-idle-states = <&CPU_SLEEP_0>;
96 capacity-dmips-mhz = <1024>;
97 clocks = <&kryocc 1>;
98 operating-points-v2 = <&cluster1_opp>;
99 #cooling-cells = <2>;
100 next-level-cache = <&L2_1>;
103 cpu-map {
125 idle-states {
126 entry-method = "psci";
128 CPU_SLEEP_0: cpu-sleep-0 {
129 compatible = "arm,idle-state";
130 idle-state-name = "standalone-power-collapse";
131 arm,psci-suspend-param = <0x00000004>;
132 entry-latency-us = <130>;
133 exit-latency-us = <80>;
134 min-residency-us = <300>;
139 cluster0_opp: opp-table-cluster0 {
140 compatible = "operating-points-v2-kryo-cpu";
141 nvmem-cells = <&speedbin_efuse>;
142 opp-shared;
145 opp-307200000 {
146 opp-hz = /bits/ 64 <307200000>;
147 opp-supported-hw = <0x77>;
148 clock-latency-ns = <200000>;
150 opp-422400000 {
151 opp-hz = /bits/ 64 <422400000>;
152 opp-supported-hw = <0x77>;
153 clock-latency-ns = <200000>;
155 opp-480000000 {
156 opp-hz = /bits/ 64 <480000000>;
157 opp-supported-hw = <0x77>;
158 clock-latency-ns = <200000>;
160 opp-556800000 {
161 opp-hz = /bits/ 64 <556800000>;
162 opp-supported-hw = <0x77>;
163 clock-latency-ns = <200000>;
165 opp-652800000 {
166 opp-hz = /bits/ 64 <652800000>;
167 opp-supported-hw = <0x77>;
168 clock-latency-ns = <200000>;
170 opp-729600000 {
171 opp-hz = /bits/ 64 <729600000>;
172 opp-supported-hw = <0x77>;
173 clock-latency-ns = <200000>;
175 opp-844800000 {
176 opp-hz = /bits/ 64 <844800000>;
177 opp-supported-hw = <0x77>;
178 clock-latency-ns = <200000>;
180 opp-960000000 {
181 opp-hz = /bits/ 64 <960000000>;
182 opp-supported-hw = <0x77>;
183 clock-latency-ns = <200000>;
185 opp-1036800000 {
186 opp-hz = /bits/ 64 <1036800000>;
187 opp-supported-hw = <0x77>;
188 clock-latency-ns = <200000>;
190 opp-1113600000 {
191 opp-hz = /bits/ 64 <1113600000>;
192 opp-supported-hw = <0x77>;
193 clock-latency-ns = <200000>;
195 opp-1190400000 {
196 opp-hz = /bits/ 64 <1190400000>;
197 opp-supported-hw = <0x77>;
198 clock-latency-ns = <200000>;
200 opp-1228800000 {
201 opp-hz = /bits/ 64 <1228800000>;
202 opp-supported-hw = <0x77>;
203 clock-latency-ns = <200000>;
205 opp-1324800000 {
206 opp-hz = /bits/ 64 <1324800000>;
207 opp-supported-hw = <0x77>;
208 clock-latency-ns = <200000>;
210 opp-1401600000 {
211 opp-hz = /bits/ 64 <1401600000>;
212 opp-supported-hw = <0x77>;
213 clock-latency-ns = <200000>;
215 opp-1478400000 {
216 opp-hz = /bits/ 64 <1478400000>;
217 opp-supported-hw = <0x77>;
218 clock-latency-ns = <200000>;
220 opp-1593600000 {
221 opp-hz = /bits/ 64 <1593600000>;
222 opp-supported-hw = <0x77>;
223 clock-latency-ns = <200000>;
227 cluster1_opp: opp-table-cluster1 {
228 compatible = "operating-points-v2-kryo-cpu";
229 nvmem-cells = <&speedbin_efuse>;
230 opp-shared;
233 opp-307200000 {
234 opp-hz = /bits/ 64 <307200000>;
235 opp-supported-hw = <0x77>;
236 clock-latency-ns = <200000>;
238 opp-403200000 {
239 opp-hz = /bits/ 64 <403200000>;
240 opp-supported-hw = <0x77>;
241 clock-latency-ns = <200000>;
243 opp-480000000 {
244 opp-hz = /bits/ 64 <480000000>;
245 opp-supported-hw = <0x77>;
246 clock-latency-ns = <200000>;
248 opp-556800000 {
249 opp-hz = /bits/ 64 <556800000>;
250 opp-supported-hw = <0x77>;
251 clock-latency-ns = <200000>;
253 opp-652800000 {
254 opp-hz = /bits/ 64 <652800000>;
255 opp-supported-hw = <0x77>;
256 clock-latency-ns = <200000>;
258 opp-729600000 {
259 opp-hz = /bits/ 64 <729600000>;
260 opp-supported-hw = <0x77>;
261 clock-latency-ns = <200000>;
263 opp-806400000 {
264 opp-hz = /bits/ 64 <806400000>;
265 opp-supported-hw = <0x77>;
266 clock-latency-ns = <200000>;
268 opp-883200000 {
269 opp-hz = /bits/ 64 <883200000>;
270 opp-supported-hw = <0x77>;
271 clock-latency-ns = <200000>;
273 opp-940800000 {
274 opp-hz = /bits/ 64 <940800000>;
275 opp-supported-hw = <0x77>;
276 clock-latency-ns = <200000>;
278 opp-1036800000 {
279 opp-hz = /bits/ 64 <1036800000>;
280 opp-supported-hw = <0x77>;
281 clock-latency-ns = <200000>;
283 opp-1113600000 {
284 opp-hz = /bits/ 64 <1113600000>;
285 opp-supported-hw = <0x77>;
286 clock-latency-ns = <200000>;
288 opp-1190400000 {
289 opp-hz = /bits/ 64 <1190400000>;
290 opp-supported-hw = <0x77>;
291 clock-latency-ns = <200000>;
293 opp-1248000000 {
294 opp-hz = /bits/ 64 <1248000000>;
295 opp-supported-hw = <0x77>;
296 clock-latency-ns = <200000>;
298 opp-1324800000 {
299 opp-hz = /bits/ 64 <1324800000>;
300 opp-supported-hw = <0x77>;
301 clock-latency-ns = <200000>;
303 opp-1401600000 {
304 opp-hz = /bits/ 64 <1401600000>;
305 opp-supported-hw = <0x77>;
306 clock-latency-ns = <200000>;
308 opp-1478400000 {
309 opp-hz = /bits/ 64 <1478400000>;
310 opp-supported-hw = <0x77>;
311 clock-latency-ns = <200000>;
313 opp-1555200000 {
314 opp-hz = /bits/ 64 <1555200000>;
315 opp-supported-hw = <0x77>;
316 clock-latency-ns = <200000>;
318 opp-1632000000 {
319 opp-hz = /bits/ 64 <1632000000>;
320 opp-supported-hw = <0x77>;
321 clock-latency-ns = <200000>;
323 opp-1708800000 {
324 opp-hz = /bits/ 64 <1708800000>;
325 opp-supported-hw = <0x77>;
326 clock-latency-ns = <200000>;
328 opp-1785600000 {
329 opp-hz = /bits/ 64 <1785600000>;
330 opp-supported-hw = <0x77>;
331 clock-latency-ns = <200000>;
333 opp-1824000000 {
334 opp-hz = /bits/ 64 <1824000000>;
335 opp-supported-hw = <0x77>;
336 clock-latency-ns = <200000>;
338 opp-1920000000 {
339 opp-hz = /bits/ 64 <1920000000>;
340 opp-supported-hw = <0x77>;
341 clock-latency-ns = <200000>;
343 opp-1996800000 {
344 opp-hz = /bits/ 64 <1996800000>;
345 opp-supported-hw = <0x77>;
346 clock-latency-ns = <200000>;
348 opp-2073600000 {
349 opp-hz = /bits/ 64 <2073600000>;
350 opp-supported-hw = <0x77>;
351 clock-latency-ns = <200000>;
353 opp-2150400000 {
354 opp-hz = /bits/ 64 <2150400000>;
355 opp-supported-hw = <0x77>;
356 clock-latency-ns = <200000>;
362 compatible = "qcom,scm-msm8996", "qcom,scm";
363 qcom,dload-mode = <&tcsr_2 0x13000>;
374 compatible = "arm,psci-1.0";
378 reserved-memory {
379 #address-cells = <2>;
380 #size-cells = <2>;
385 no-map;
390 no-map;
393 smem_mem: smem-mem@86000000 {
395 no-map;
400 no-map;
404 compatible = "qcom,rmtfs-mem";
407 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
408 no-map;
410 qcom,client-id = <1>;
416 no-map;
421 no-map;
426 no-map;
430 compatible = "shared-dma-pool";
432 no-map;
437 no-map;
442 no-map;
446 rpm-glink {
447 compatible = "qcom,glink-rpm";
451 qcom,rpm-msg-ram = <&rpm_msg_ram>;
455 rpm_requests: rpm-requests {
456 compatible = "qcom,rpm-msm8996";
457 qcom,glink-channels = "rpm_requests";
460 compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc";
461 #clock-cells = <1>;
462 clocks = <&xo_board>;
463 clock-names = "xo";
466 rpmpd: power-controller {
467 compatible = "qcom,msm8996-rpmpd";
468 #power-domain-cells = <1>;
469 operating-points-v2 = <&rpmpd_opp_table>;
471 rpmpd_opp_table: opp-table {
472 compatible = "operating-points-v2";
475 opp-level = <1>;
479 opp-level = <2>;
483 opp-level = <3>;
487 opp-level = <4>;
491 opp-level = <5>;
495 opp-level = <6>;
504 memory-region = <&smem_mem>;
508 smp2p-adsp {
516 qcom,local-pid = <0>;
517 qcom,remote-pid = <2>;
519 adsp_smp2p_out: master-kernel {
520 qcom,entry-name = "master-kernel";
521 #qcom,smem-state-cells = <1>;
524 adsp_smp2p_in: slave-kernel {
525 qcom,entry-name = "slave-kernel";
527 interrupt-controller;
528 #interrupt-cells = <2>;
532 smp2p-mpss {
540 qcom,local-pid = <0>;
541 qcom,remote-pid = <1>;
543 mpss_smp2p_out: master-kernel {
544 qcom,entry-name = "master-kernel";
545 #qcom,smem-state-cells = <1>;
548 mpss_smp2p_in: slave-kernel {
549 qcom,entry-name = "slave-kernel";
551 interrupt-controller;
552 #interrupt-cells = <2>;
556 smp2p-slpi {
564 qcom,local-pid = <0>;
565 qcom,remote-pid = <3>;
567 slpi_smp2p_out: master-kernel {
568 qcom,entry-name = "master-kernel";
569 #qcom,smem-state-cells = <1>;
572 slpi_smp2p_in: slave-kernel {
573 qcom,entry-name = "slave-kernel";
575 interrupt-controller;
576 #interrupt-cells = <2>;
581 #address-cells = <1>;
582 #size-cells = <1>;
584 compatible = "simple-bus";
586 pcie_phy: phy-wrapper@34000 {
587 compatible = "qcom,msm8996-qmp-pcie-phy";
589 #address-cells = <1>;
590 #size-cells = <1>;
593 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
596 clock-names = "aux", "cfg_ahb", "ref";
601 reset-names = "phy", "common", "cfg";
610 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
611 clock-names = "pipe0";
613 reset-names = "lane0";
615 #clock-cells = <0>;
616 clock-output-names = "pcie_0_pipe_clk_src";
618 #phy-cells = <0>;
626 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
627 clock-names = "pipe1";
629 reset-names = "lane1";
631 #clock-cells = <0>;
632 clock-output-names = "pcie_1_pipe_clk_src";
634 #phy-cells = <0>;
642 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
643 clock-names = "pipe2";
645 reset-names = "lane2";
647 #clock-cells = <0>;
648 clock-output-names = "pcie_2_pipe_clk_src";
650 #phy-cells = <0>;
655 compatible = "qcom,rpm-msg-ram";
660 compatible = "qcom,msm8996-qfprom", "qcom,qfprom";
662 #address-cells = <1>;
663 #size-cells = <1>;
682 compatible = "qcom,prng-ee";
684 clocks = <&gcc GCC_PRNG_AHB_CLK>;
685 clock-names = "core";
688 gcc: clock-controller@300000 {
689 compatible = "qcom,gcc-msm8996";
690 #clock-cells = <1>;
691 #reset-cells = <1>;
692 #power-domain-cells = <1>;
695 clocks = <&rpmcc RPM_SMD_BB_CLK1>,
703 clock-names = "cxo",
716 compatible = "qcom,msm8996-bimc";
718 #interconnect-cells = <1>;
719 clock-names = "bus", "bus_a";
720 clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
724 tsens0: thermal-sensor@4a9000 {
725 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
731 interrupt-names = "uplow", "critical";
732 #thermal-sensor-cells = <1>;
735 tsens1: thermal-sensor@4ad000 {
736 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
742 interrupt-names = "uplow", "critical";
743 #thermal-sensor-cells = <1>;
746 cryptobam: dma-controller@644000 {
747 compatible = "qcom,bam-v1.7.0";
750 clocks = <&gcc GCC_CE1_CLK>;
751 clock-names = "bam_clk";
752 #dma-cells = <1>;
754 qcom,controlled-remotely;
758 compatible = "qcom,crypto-v5.4";
760 clocks = <&gcc GCC_CE1_AHB_CLK>,
763 clock-names = "iface", "bus", "core";
765 dma-names = "rx", "tx";
769 compatible = "qcom,msm8996-cnoc";
771 #interconnect-cells = <1>;
772 clock-names = "bus", "bus_a";
773 clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
778 compatible = "qcom,msm8996-snoc";
780 #interconnect-cells = <1>;
781 clock-names = "bus", "bus_a";
782 clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
787 compatible = "qcom,msm8996-a0noc";
789 #interconnect-cells = <1>;
790 clock-names = "aggre0_snoc_axi",
793 clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>,
796 power-domains = <&gcc AGGRE0_NOC_GDSC>;
800 compatible = "qcom,msm8996-a1noc";
802 #interconnect-cells = <1>;
803 clock-names = "bus", "bus_a";
804 clocks = <&rpmcc RPM_SMD_AGGR1_NOC_CLK>,
809 compatible = "qcom,msm8996-a2noc";
811 #interconnect-cells = <1>;
812 clock-names = "bus", "bus_a";
813 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
818 compatible = "qcom,msm8996-mnoc";
820 #interconnect-cells = <1>;
821 clock-names = "bus", "bus_a", "iface";
822 clocks = <&rpmcc RPM_SMD_MMAXI_CLK>,
828 compatible = "qcom,msm8996-pnoc";
830 #interconnect-cells = <1>;
831 clock-names = "bus", "bus_a";
832 clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
837 compatible = "qcom,tcsr-mutex";
839 #hwlock-cells = <1>;
843 compatible = "qcom,tcsr-msm8996", "syscon";
848 compatible = "qcom,tcsr-msm8996", "syscon";
852 mmcc: clock-controller@8c0000 {
853 compatible = "qcom,mmcc-msm8996";
854 #clock-cells = <1>;
855 #reset-cells = <1>;
856 #power-domain-cells = <1>;
858 clocks = <&xo_board>,
866 clock-names = "xo",
874 assigned-clocks = <&mmcc MMPLL9_PLL>,
879 assigned-clock-rates = <624000000>,
892 reg-names = "mdss_phys",
896 power-domains = <&mmcc MDSS_GDSC>;
899 interrupt-controller;
900 #interrupt-cells = <1>;
902 clocks = <&mmcc MDSS_AHB_CLK>,
904 clock-names = "iface", "core";
906 #address-cells = <1>;
907 #size-cells = <1>;
915 reg-names = "mdp_phys";
917 interrupt-parent = <&mdss>;
920 clocks = <&mmcc MDSS_AHB_CLK>,
925 clock-names = "iface",
933 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
935 assigned-clock-rates = <300000000>,
941 interconnect-names = "mdp0-mem", "mdp1-mem", "rotator-mem";
944 #address-cells = <1>;
945 #size-cells = <0>;
950 remote-endpoint = <&hdmi_in>;
957 remote-endpoint = <&dsi0_in>;
964 remote-endpoint = <&dsi1_in>;
971 compatible = "qcom,mdss-dsi-ctrl";
973 reg-names = "dsi_ctrl";
975 interrupt-parent = <&mdss>;
978 clocks = <&mmcc MDSS_MDP_CLK>,
985 clock-names = "mdp_core",
992 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
993 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
996 phy-names = "dsi";
999 #address-cells = <1>;
1000 #size-cells = <0>;
1003 #address-cells = <1>;
1004 #size-cells = <0>;
1009 remote-endpoint = <&mdp5_intf1_out>;
1021 dsi0_phy: dsi-phy@994400 {
1022 compatible = "qcom,dsi-phy-14nm";
1026 reg-names = "dsi_phy",
1030 #clock-cells = <1>;
1031 #phy-cells = <0>;
1033 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_BB_CLK1>;
1034 clock-names = "iface", "ref";
1039 compatible = "qcom,mdss-dsi-ctrl";
1041 reg-names = "dsi_ctrl";
1043 interrupt-parent = <&mdss>;
1046 clocks = <&mmcc MDSS_MDP_CLK>,
1053 clock-names = "mdp_core",
1060 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
1061 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
1064 phy-names = "dsi";
1067 #address-cells = <1>;
1068 #size-cells = <0>;
1071 #address-cells = <1>;
1072 #size-cells = <0>;
1077 remote-endpoint = <&mdp5_intf2_out>;
1089 dsi1_phy: dsi-phy@996400 {
1090 compatible = "qcom,dsi-phy-14nm";
1094 reg-names = "dsi_phy",
1098 #clock-cells = <1>;
1099 #phy-cells = <0>;
1101 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_BB_CLK1>;
1102 clock-names = "iface", "ref";
1106 hdmi: hdmi-tx@9a0000 {
1107 compatible = "qcom,hdmi-tx-8996";
1111 reg-names = "core_physical",
1115 interrupt-parent = <&mdss>;
1118 clocks = <&mmcc MDSS_MDP_CLK>,
1123 clock-names =
1131 #sound-dai-cells = <1>;
1136 #address-cells = <1>;
1137 #size-cells = <0>;
1142 remote-endpoint = <&mdp5_intf3_out>;
1148 hdmi_phy: hdmi-phy@9a0600 {
1149 #phy-cells = <0>;
1150 compatible = "qcom,hdmi-phy-8996";
1157 reg-names = "hdmi_pll",
1164 clocks = <&mmcc MDSS_AHB_CLK>,
1167 clock-names = "iface",
1171 #clock-cells = <0>;
1178 compatible = "qcom,adreno-530.2", "qcom,adreno";
1181 reg-names = "kgsl_3d0_reg_memory";
1185 clocks = <&mmcc GPU_GX_GFX3D_CLK>,
1191 clock-names = "core",
1198 interconnect-names = "gfx-mem";
1200 power-domains = <&mmcc GPU_GX_GDSC>;
1203 nvmem-cells = <&speedbin_efuse>;
1204 nvmem-cell-names = "speed_bin";
1206 operating-points-v2 = <&gpu_opp_table>;
1210 #cooling-cells = <2>;
1212 gpu_opp_table: opp-table {
1213 compatible = "operating-points-v2";
1220 opp-624000000 {
1221 opp-hz = /bits/ 64 <624000000>;
1222 opp-supported-hw = <0x01>;
1224 opp-560000000 {
1225 opp-hz = /bits/ 64 <560000000>;
1226 opp-supported-hw = <0x01>;
1228 opp-510000000 {
1229 opp-hz = /bits/ 64 <510000000>;
1230 opp-supported-hw = <0xFF>;
1232 opp-401800000 {
1233 opp-hz = /bits/ 64 <401800000>;
1234 opp-supported-hw = <0xFF>;
1236 opp-315000000 {
1237 opp-hz = /bits/ 64 <315000000>;
1238 opp-supported-hw = <0xFF>;
1240 opp-214000000 {
1241 opp-hz = /bits/ 64 <214000000>;
1242 opp-supported-hw = <0xFF>;
1244 opp-133000000 {
1245 opp-hz = /bits/ 64 <133000000>;
1246 opp-supported-hw = <0xFF>;
1250 zap-shader {
1251 memory-region = <&gpu_mem>;
1256 compatible = "qcom,msm8996-pinctrl";
1259 gpio-controller;
1260 gpio-ranges = <&tlmm 0 0 150>;
1261 #gpio-cells = <2>;
1262 interrupt-controller;
1263 #interrupt-cells = <2>;
1265 blsp1_spi1_default: blsp1-spi1-default {
1269 drive-strength = <12>;
1270 bias-disable;
1276 drive-strength = <16>;
1277 bias-disable;
1278 output-high;
1282 blsp1_spi1_sleep: blsp1-spi1-sleep {
1285 drive-strength = <2>;
1286 bias-pull-down;
1289 blsp2_uart2_2pins_default: blsp2-uart1-2pins {
1292 drive-strength = <16>;
1293 bias-disable;
1296 blsp2_uart2_2pins_sleep: blsp2-uart1-2pins-sleep {
1299 drive-strength = <2>;
1300 bias-disable;
1303 blsp2_i2c2_default: blsp2-i2c2 {
1306 drive-strength = <16>;
1307 bias-disable;
1310 blsp2_i2c2_sleep: blsp2-i2c2-sleep {
1313 drive-strength = <2>;
1314 bias-disable;
1317 cci0_default: cci0-default {
1320 drive-strength = <16>;
1321 bias-disable;
1325 camera_rear_default: camera-rear-default {
1329 drive-strength = <16>;
1330 bias-disable;
1336 drive-strength = <16>;
1337 bias-disable;
1343 drive-strength = <16>;
1344 bias-disable;
1348 cci1_default: cci1-default {
1351 drive-strength = <16>;
1352 bias-disable;
1356 camera_board_default: camera-board-default {
1360 drive-strength = <16>;
1361 bias-disable;
1367 drive-strength = <16>;
1368 bias-disable;
1374 drive-strength = <16>;
1375 bias-disable;
1380 camera_front_default: camera-front-default {
1384 drive-strength = <16>;
1385 bias-disable;
1391 drive-strength = <16>;
1392 bias-disable;
1398 drive-strength = <16>;
1399 bias-disable;
1403 pcie0_state_on: pcie0-state-on {
1407 drive-strength = <2>;
1408 bias-pull-down;
1414 drive-strength = <2>;
1415 bias-pull-up;
1421 drive-strength = <2>;
1422 bias-pull-up;
1426 pcie0_state_off: pcie0-state-off {
1430 drive-strength = <2>;
1431 bias-pull-down;
1437 drive-strength = <2>;
1438 bias-disable;
1444 drive-strength = <2>;
1445 bias-disable;
1449 blsp1_uart2_default: blsp1-uart2-default {
1452 drive-strength = <16>;
1453 bias-disable;
1456 blsp1_uart2_sleep: blsp1-uart2-sleep {
1459 drive-strength = <2>;
1460 bias-disable;
1463 blsp1_i2c3_default: blsp1-i2c2-default {
1466 drive-strength = <16>;
1467 bias-disable;
1470 blsp1_i2c3_sleep: blsp1-i2c2-sleep {
1473 drive-strength = <2>;
1474 bias-disable;
1477 blsp2_uart3_4pins_default: blsp2-uart2-4pins {
1480 drive-strength = <16>;
1481 bias-disable;
1484 blsp2_uart3_4pins_sleep: blsp2-uart2-4pins-sleep {
1487 drive-strength = <2>;
1488 bias-disable;
1491 blsp2_i2c3_default: blsp2-i2c3 {
1494 drive-strength = <16>;
1495 bias-disable;
1498 blsp2_i2c3_sleep: blsp2-i2c3-sleep {
1501 drive-strength = <2>;
1502 bias-disable;
1505 wcd_intr_default: wcd-intr-default{
1508 drive-strength = <2>;
1509 bias-pull-down;
1510 input-enable;
1513 blsp2_i2c1_default: blsp2-i2c1 {
1516 drive-strength = <16>;
1517 bias-disable;
1520 blsp2_i2c1_sleep: blsp2-i2c0-sleep {
1523 drive-strength = <2>;
1524 bias-disable;
1527 blsp2_i2c5_default: blsp2-i2c5 {
1530 drive-strength = <2>;
1531 bias-disable;
1536 cdc_reset_active: cdc-reset-active {
1539 drive-strength = <16>;
1540 bias-pull-down;
1541 output-high;
1544 cdc_reset_sleep: cdc-reset-sleep {
1547 drive-strength = <16>;
1548 bias-disable;
1549 output-low;
1552 blsp2_spi6_default: blsp2-spi5-default {
1556 drive-strength = <12>;
1557 bias-disable;
1563 drive-strength = <16>;
1564 bias-disable;
1565 output-high;
1569 blsp2_spi6_sleep: blsp2-spi5-sleep {
1572 drive-strength = <2>;
1573 bias-pull-down;
1576 blsp2_i2c6_default: blsp2-i2c6 {
1579 drive-strength = <16>;
1580 bias-disable;
1583 blsp2_i2c6_sleep: blsp2-i2c6-sleep {
1586 drive-strength = <2>;
1587 bias-disable;
1590 pcie1_state_on: pcie1-state-on {
1594 drive-strength = <2>;
1595 bias-pull-down;
1601 drive-strength = <2>;
1602 bias-pull-up;
1608 drive-strength = <2>;
1609 bias-pull-down;
1613 pcie1_state_off: pcie1-state-off {
1618 drive-strength = <2>;
1619 bias-disable;
1625 drive-strength = <2>;
1626 bias-disable;
1630 pcie2_state_on: pcie2-state-on {
1634 drive-strength = <2>;
1635 bias-pull-down;
1641 drive-strength = <2>;
1642 bias-pull-up;
1648 drive-strength = <2>;
1649 bias-pull-down;
1653 pcie2_state_off: pcie2-state-off {
1658 drive-strength = <2>;
1659 bias-disable;
1665 drive-strength = <2>;
1666 bias-disable;
1670 sdc1_state_on: sdc1-state-on {
1673 bias-disable;
1674 drive-strength = <16>;
1679 bias-pull-up;
1680 drive-strength = <10>;
1685 bias-pull-up;
1686 drive-strength = <10>;
1691 bias-pull-down;
1695 sdc1_state_off: sdc1-state-off {
1698 bias-disable;
1699 drive-strength = <2>;
1704 bias-pull-up;
1705 drive-strength = <2>;
1710 bias-pull-up;
1711 drive-strength = <2>;
1716 bias-pull-down;
1720 sdc2_state_on: sdc2-clk-on {
1723 bias-disable;
1724 drive-strength = <16>;
1729 bias-pull-up;
1730 drive-strength = <10>;
1735 bias-pull-up;
1736 drive-strength = <10>;
1740 sdc2_state_off: sdc2-clk-off {
1743 bias-disable;
1744 drive-strength = <2>;
1749 bias-pull-up;
1750 drive-strength = <2>;
1755 bias-pull-up;
1756 drive-strength = <2>;
1762 compatible = "qcom,rpm-stats";
1767 compatible = "qcom,spmi-pmic-arb";
1773 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1774 interrupt-names = "periph_irq";
1778 #address-cells = <2>;
1779 #size-cells = <0>;
1780 interrupt-controller;
1781 #interrupt-cells = <4>;
1785 power-domains = <&gcc AGGRE0_NOC_GDSC>;
1786 compatible = "simple-pm-bus";
1787 #address-cells = <1>;
1788 #size-cells = <1>;
1792 compatible = "qcom,pcie-msm8996";
1794 power-domains = <&gcc PCIE0_GDSC>;
1795 bus-range = <0x00 0xff>;
1796 num-lanes = <1>;
1802 reg-names = "parf", "dbi", "elbi","config";
1805 phy-names = "pciephy";
1807 #address-cells = <3>;
1808 #size-cells = <2>;
1815 interrupt-names = "msi";
1816 #interrupt-cells = <1>;
1817 interrupt-map-mask = <0 0 0 0x7>;
1818 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1823 pinctrl-names = "default", "sleep";
1824 pinctrl-0 = <&pcie0_state_on>;
1825 pinctrl-1 = <&pcie0_state_off>;
1827 linux,pci-domain = <0>;
1829 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1835 clock-names = "pipe",
1844 compatible = "qcom,pcie-msm8996";
1845 power-domains = <&gcc PCIE1_GDSC>;
1846 bus-range = <0x00 0xff>;
1847 num-lanes = <1>;
1856 reg-names = "parf", "dbi", "elbi","config";
1859 phy-names = "pciephy";
1861 #address-cells = <3>;
1862 #size-cells = <2>;
1869 interrupt-names = "msi";
1870 #interrupt-cells = <1>;
1871 interrupt-map-mask = <0 0 0 0x7>;
1872 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1877 pinctrl-names = "default", "sleep";
1878 pinctrl-0 = <&pcie1_state_on>;
1879 pinctrl-1 = <&pcie1_state_off>;
1881 linux,pci-domain = <1>;
1883 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1889 clock-names = "pipe",
1897 compatible = "qcom,pcie-msm8996";
1898 power-domains = <&gcc PCIE2_GDSC>;
1899 bus-range = <0x00 0xff>;
1900 num-lanes = <1>;
1907 reg-names = "parf", "dbi", "elbi","config";
1910 phy-names = "pciephy";
1912 #address-cells = <3>;
1913 #size-cells = <2>;
1920 interrupt-names = "msi";
1921 #interrupt-cells = <1>;
1922 interrupt-map-mask = <0 0 0 0x7>;
1923 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1928 pinctrl-names = "default", "sleep";
1929 pinctrl-0 = <&pcie2_state_on>;
1930 pinctrl-1 = <&pcie2_state_off>;
1932 linux,pci-domain = <2>;
1933 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
1939 clock-names = "pipe",
1948 compatible = "qcom,msm8996-ufshc", "qcom,ufshc",
1949 "jedec,ufs-2.0";
1954 phy-names = "ufsphy";
1956 power-domains = <&gcc UFS_GDSC>;
1958 clock-names =
1970 clocks =
1982 freq-table-hz =
1995 lanes-per-direction = <1>;
1996 #reset-cells = <1>;
2005 compatible = "qcom,msm8996-qmp-ufs-phy";
2007 #address-cells = <1>;
2008 #size-cells = <1>;
2011 clocks = <&gcc GCC_UFS_CLKREF_CLK>;
2012 clock-names = "ref";
2015 reset-names = "ufsphy";
2022 #phy-cells = <0>;
2027 compatible = "qcom,msm8996-camss";
2042 reg-names = "csiphy0",
2066 interrupt-names = "csiphy0",
2076 power-domains = <&mmcc VFE0_GDSC>,
2078 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2114 clock-names = "top_ahb",
2156 #address-cells = <1>;
2157 #size-cells = <0>;
2162 compatible = "qcom,msm8996-cci";
2163 #address-cells = <1>;
2164 #size-cells = <0>;
2167 power-domains = <&mmcc CAMSS_GDSC>;
2168 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2172 clock-names = "camss_top_ahb",
2176 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
2178 assigned-clock-rates = <80000000>, <37500000>;
2179 pinctrl-names = "default";
2180 pinctrl-0 = <&cci0_default &cci1_default>;
2183 cci_i2c0: i2c-bus@0 {
2185 clock-frequency = <400000>;
2186 #address-cells = <1>;
2187 #size-cells = <0>;
2190 cci_i2c1: i2c-bus@1 {
2192 clock-frequency = <400000>;
2193 #address-cells = <1>;
2194 #size-cells = <0>;
2199 compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2202 #global-interrupts = <1>;
2206 #iommu-cells = <1>;
2208 clocks = <&mmcc GPU_AHB_CLK>,
2210 clock-names = "iface", "bus";
2212 power-domains = <&mmcc GPU_GDSC>;
2215 venus: video-codec@c00000 {
2216 compatible = "qcom,msm8996-venus";
2219 power-domains = <&mmcc VENUS_GDSC>;
2220 clocks = <&mmcc VIDEO_CORE_CLK>,
2224 clock-names = "core", "iface", "bus", "mbus";
2227 interconnect-names = "video-mem", "cpu-cfg";
2248 memory-region = <&venus_mem>;
2251 video-decoder {
2252 compatible = "venus-decoder";
2253 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2254 clock-names = "core";
2255 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2258 video-encoder {
2259 compatible = "venus-encoder";
2260 clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
2261 clock-names = "core";
2262 power-domains = <&mmcc VENUS_CORE1_GDSC>;
2267 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2270 #global-interrupts = <1>;
2274 #iommu-cells = <1>;
2275 clocks = <&mmcc SMMU_MDP_AHB_CLK>,
2277 clock-names = "iface", "bus";
2279 power-domains = <&mmcc MDSS_GDSC>;
2283 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2285 #global-interrupts = <1>;
2294 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
2295 clocks = <&mmcc SMMU_VIDEO_AHB_CLK>,
2297 clock-names = "iface", "bus";
2298 #iommu-cells = <1>;
2303 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2306 #global-interrupts = <1>;
2310 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
2311 clocks = <&mmcc SMMU_VFE_AHB_CLK>,
2313 clock-names = "iface",
2315 #iommu-cells = <1>;
2319 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2321 #iommu-cells = <1>;
2322 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
2324 #global-interrupts = <1>;
2339 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
2341 clock-names = "iface", "bus";
2345 compatible = "qcom,msm8996-slpi-pil";
2348 interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>,
2353 interrupt-names = "wdog",
2357 "stop-ack";
2359 clocks = <&xo_board>,
2361 clock-names = "xo", "aggre2";
2363 memory-region = <&slpi_mem>;
2365 qcom,smem-states = <&slpi_smp2p_out 0>;
2366 qcom,smem-state-names = "stop";
2368 power-domains = <&rpmpd MSM8996_VDDSSCX>;
2369 power-domain-names = "ssc_cx";
2373 smd-edge {
2378 qcom,smd-edge = <3>;
2379 qcom,remote-pid = <3>;
2384 compatible = "qcom,msm8996-mss-pil";
2387 reg-names = "qdsp6", "rmb";
2389 interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>,
2395 interrupt-names = "wdog", "fatal", "ready",
2396 "handover", "stop-ack",
2397 "shutdown-ack";
2399 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
2408 clock-names = "iface", "bus", "mem", "xo", "gpll0_mss",
2412 reset-names = "mss_restart";
2414 power-domains = <&rpmpd MSM8996_VDDCX>,
2416 power-domain-names = "cx", "mx";
2418 qcom,smem-states = <&mpss_smp2p_out 0>;
2419 qcom,smem-state-names = "stop";
2421 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x4000>;
2426 memory-region = <&mba_mem>;
2430 memory-region = <&mpss_mem>;
2433 smd-edge {
2438 qcom,smd-edge = <0>;
2439 qcom,remote-pid = <1>;
2444 compatible = "arm,coresight-stm", "arm,primecell";
2447 reg-names = "stm-base", "stm-stimulus-base";
2449 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2450 clock-names = "apb_pclk", "atclk";
2452 out-ports {
2455 remote-endpoint =
2463 compatible = "arm,coresight-tpiu", "arm,primecell";
2466 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2467 clock-names = "apb_pclk", "atclk";
2469 in-ports {
2472 remote-endpoint =
2480 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2483 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2484 clock-names = "apb_pclk", "atclk";
2486 in-ports {
2487 #address-cells = <1>;
2488 #size-cells = <0>;
2493 remote-endpoint =
2499 out-ports {
2502 remote-endpoint =
2510 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2513 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2514 clock-names = "apb_pclk", "atclk";
2516 in-ports {
2517 #address-cells = <1>;
2518 #size-cells = <0>;
2523 remote-endpoint =
2529 out-ports {
2532 remote-endpoint =
2540 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2543 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2544 clock-names = "apb_pclk", "atclk";
2547 out-ports {
2550 remote-endpoint =
2558 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2561 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2562 clock-names = "apb_pclk", "atclk";
2564 in-ports {
2565 #address-cells = <1>;
2566 #size-cells = <0>;
2571 remote-endpoint =
2579 remote-endpoint =
2587 remote-endpoint =
2593 out-ports {
2596 remote-endpoint =
2604 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2607 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2608 clock-names = "apb_pclk", "atclk";
2610 in-ports {
2613 remote-endpoint =
2619 out-ports {
2620 #address-cells = <1>;
2621 #size-cells = <0>;
2626 remote-endpoint =
2634 remote-endpoint =
2642 compatible = "arm,coresight-tmc", "arm,primecell";
2645 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2646 clock-names = "apb_pclk", "atclk";
2648 in-ports {
2651 remote-endpoint =
2657 out-ports {
2660 remote-endpoint =
2668 compatible = "arm,coresight-tmc", "arm,primecell";
2671 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2672 clock-names = "apb_pclk", "atclk";
2673 arm,scatter-gather;
2675 in-ports {
2678 remote-endpoint =
2686 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2689 clocks = <&rpmcc RPM_QDSS_CLK>;
2690 clock-names = "apb_pclk";
2696 compatible = "arm,coresight-etm4x", "arm,primecell";
2699 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2700 clock-names = "apb_pclk", "atclk";
2704 out-ports {
2707 remote-endpoint =
2715 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2718 clocks = <&rpmcc RPM_QDSS_CLK>;
2719 clock-names = "apb_pclk";
2725 compatible = "arm,coresight-etm4x", "arm,primecell";
2728 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2729 clock-names = "apb_pclk", "atclk";
2733 out-ports {
2736 remote-endpoint =
2744 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2747 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2748 clock-names = "apb_pclk", "atclk";
2750 in-ports {
2751 #address-cells = <1>;
2752 #size-cells = <0>;
2757 remote-endpoint = <&etm0_out>;
2764 remote-endpoint = <&etm1_out>;
2769 out-ports {
2772 remote-endpoint =
2780 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2783 clocks = <&rpmcc RPM_QDSS_CLK>;
2784 clock-names = "apb_pclk";
2790 compatible = "arm,coresight-etm4x", "arm,primecell";
2793 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2794 clock-names = "apb_pclk", "atclk";
2798 out-ports {
2801 remote-endpoint =
2809 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2812 clocks = <&rpmcc RPM_QDSS_CLK>;
2813 clock-names = "apb_pclk";
2819 compatible = "arm,coresight-etm4x", "arm,primecell";
2822 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2823 clock-names = "apb_pclk", "atclk";
2827 out-ports {
2830 remote-endpoint =
2838 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2841 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2842 clock-names = "apb_pclk", "atclk";
2844 in-ports {
2845 #address-cells = <1>;
2846 #size-cells = <0>;
2851 remote-endpoint = <&etm2_out>;
2858 remote-endpoint = <&etm3_out>;
2863 out-ports {
2866 remote-endpoint =
2874 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2877 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2878 clock-names = "apb_pclk", "atclk";
2880 in-ports {
2881 #address-cells = <1>;
2882 #size-cells = <0>;
2887 remote-endpoint =
2895 remote-endpoint =
2901 out-ports {
2904 remote-endpoint =
2911 kryocc: clock-controller@6400000 {
2912 compatible = "qcom,msm8996-apcc";
2915 clock-names = "xo";
2916 clocks = <&rpmcc RPM_SMD_BB_CLK1>;
2918 #clock-cells = <1>;
2922 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
2924 #address-cells = <1>;
2925 #size-cells = <1>;
2930 interrupt-names = "hs_phy_irq", "ss_phy_irq";
2932 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
2937 clock-names = "cfg_noc",
2943 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2945 assigned-clock-rates = <19200000>, <120000000>;
2949 interconnect-names = "usb-ddr", "apps-usb";
2951 power-domains = <&gcc USB30_GDSC>;
2959 phy-names = "usb2-phy", "usb3-phy";
2966 compatible = "qcom,msm8996-qmp-usb3-phy";
2968 #address-cells = <1>;
2969 #size-cells = <1>;
2972 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
2975 clock-names = "aux", "cfg_ahb", "ref";
2979 reset-names = "phy", "common";
2986 #phy-cells = <0>;
2988 #clock-cells = <0>;
2989 clock-output-names = "usb3_phy_pipe_clk_src";
2990 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
2991 clock-names = "pipe0";
2996 compatible = "qcom,msm8996-qusb2-phy";
2998 #phy-cells = <0>;
3000 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3002 clock-names = "cfg_ahb", "ref";
3005 nvmem-cells = <&qusb2p_hstx_trim>;
3010 compatible = "qcom,msm8996-qusb2-phy";
3012 #phy-cells = <0>;
3014 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3016 clock-names = "cfg_ahb", "ref";
3019 nvmem-cells = <&qusb2s_hstx_trim>;
3024 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
3026 reg-names = "hc", "core";
3030 interrupt-names = "hc_irq", "pwr_irq";
3032 clock-names = "iface", "core", "xo";
3033 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
3038 pinctrl-names = "default", "sleep";
3039 pinctrl-0 = <&sdc1_state_on>;
3040 pinctrl-1 = <&sdc1_state_off>;
3042 bus-width = <8>;
3043 non-removable;
3048 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
3050 reg-names = "hc", "core";
3054 interrupt-names = "hc_irq", "pwr_irq";
3056 clock-names = "iface", "core", "xo";
3057 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3062 pinctrl-names = "default", "sleep";
3063 pinctrl-0 = <&sdc2_state_on>;
3064 pinctrl-1 = <&sdc2_state_off>;
3066 bus-width = <4>;
3070 blsp1_dma: dma-controller@7544000 {
3071 compatible = "qcom,bam-v1.7.0";
3074 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
3075 clock-names = "bam_clk";
3076 qcom,controlled-remotely;
3077 #dma-cells = <1>;
3082 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3085 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
3087 clock-names = "core", "iface";
3088 pinctrl-names = "default", "sleep";
3089 pinctrl-0 = <&blsp1_uart2_default>;
3090 pinctrl-1 = <&blsp1_uart2_sleep>;
3092 dma-names = "tx", "rx";
3097 compatible = "qcom,spi-qup-v2.2.1";
3100 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
3102 clock-names = "core", "iface";
3103 pinctrl-names = "default", "sleep";
3104 pinctrl-0 = <&blsp1_spi1_default>;
3105 pinctrl-1 = <&blsp1_spi1_sleep>;
3107 dma-names = "tx", "rx";
3108 #address-cells = <1>;
3109 #size-cells = <0>;
3114 compatible = "qcom,i2c-qup-v2.2.1";
3117 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
3119 clock-names = "core", "iface";
3120 pinctrl-names = "default", "sleep";
3121 pinctrl-0 = <&blsp1_i2c3_default>;
3122 pinctrl-1 = <&blsp1_i2c3_sleep>;
3124 dma-names = "tx", "rx";
3125 #address-cells = <1>;
3126 #size-cells = <0>;
3130 blsp2_dma: dma-controller@7584000 {
3131 compatible = "qcom,bam-v1.7.0";
3134 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
3135 clock-names = "bam_clk";
3136 qcom,controlled-remotely;
3137 #dma-cells = <1>;
3142 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3145 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
3147 clock-names = "core", "iface";
3152 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3155 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
3157 clock-names = "core", "iface";
3162 compatible = "qcom,i2c-qup-v2.2.1";
3165 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
3167 clock-names = "core", "iface";
3168 pinctrl-names = "default", "sleep";
3169 pinctrl-0 = <&blsp2_i2c1_default>;
3170 pinctrl-1 = <&blsp2_i2c1_sleep>;
3172 dma-names = "tx", "rx";
3173 #address-cells = <1>;
3174 #size-cells = <0>;
3179 compatible = "qcom,i2c-qup-v2.2.1";
3182 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
3184 clock-names = "core", "iface";
3185 pinctrl-names = "default", "sleep";
3186 pinctrl-0 = <&blsp2_i2c2_default>;
3187 pinctrl-1 = <&blsp2_i2c2_sleep>;
3189 dma-names = "tx", "rx";
3190 #address-cells = <1>;
3191 #size-cells = <0>;
3196 compatible = "qcom,i2c-qup-v2.2.1";
3199 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
3201 clock-names = "core", "iface";
3202 clock-frequency = <400000>;
3203 pinctrl-names = "default", "sleep";
3204 pinctrl-0 = <&blsp2_i2c3_default>;
3205 pinctrl-1 = <&blsp2_i2c3_sleep>;
3207 dma-names = "tx", "rx";
3208 #address-cells = <1>;
3209 #size-cells = <0>;
3214 compatible = "qcom,i2c-qup-v2.2.1";
3217 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
3219 clock-names = "core", "iface";
3220 pinctrl-names = "default";
3221 pinctrl-0 = <&blsp2_i2c5_default>;
3223 dma-names = "tx", "rx";
3224 #address-cells = <1>;
3225 #size-cells = <0>;
3230 compatible = "qcom,i2c-qup-v2.2.1";
3233 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
3235 clock-names = "core", "iface";
3236 pinctrl-names = "default", "sleep";
3237 pinctrl-0 = <&blsp2_i2c6_default>;
3238 pinctrl-1 = <&blsp2_i2c6_sleep>;
3240 dma-names = "tx", "rx";
3241 #address-cells = <1>;
3242 #size-cells = <0>;
3247 compatible = "qcom,spi-qup-v2.2.1";
3250 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
3252 clock-names = "core", "iface";
3253 pinctrl-names = "default", "sleep";
3254 pinctrl-0 = <&blsp2_spi6_default>;
3255 pinctrl-1 = <&blsp2_spi6_sleep>;
3257 dma-names = "tx", "rx";
3258 #address-cells = <1>;
3259 #size-cells = <0>;
3264 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
3266 #address-cells = <1>;
3267 #size-cells = <1>;
3270 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
3275 clock-names = "cfg_noc",
3281 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
3283 assigned-clock-rates = <19200000>, <60000000>;
3285 power-domains = <&gcc USB30_GDSC>;
3286 qcom,select-utmi-as-pipe-clk;
3294 phy-names = "usb2-phy";
3295 maximum-speed = "high-speed";
3301 slimbam: dma-controller@9184000 {
3302 compatible = "qcom,bam-v1.7.0";
3303 qcom,controlled-remotely;
3305 num-channels = <31>;
3307 #dma-cells = <1>;
3309 qcom,num-ees = <2>;
3313 compatible = "qcom,slim-ngd-v1.5.0";
3315 reg-names = "ctrl";
3319 dma-names = "rx", "tx", "tx2", "rx2";
3320 #address-cells = <1>;
3321 #size-cells = <0>;
3324 #address-cells = <1>;
3325 #size-cells = <1>;
3327 tasha_ifd: tas-ifd {
3333 pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
3334 pinctrl-names = "default";
3339 interrupt-parent = <&tlmm>;
3342 interrupt-names = "intr1", "intr2";
3343 interrupt-controller;
3344 #interrupt-cells = <1>;
3345 reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>;
3347 slim-ifc-dev = <&tasha_ifd>;
3349 #sound-dai-cells = <1>;
3355 compatible = "qcom,msm8996-adsp-pil";
3358 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
3363 interrupt-names = "wdog", "fatal", "ready",
3364 "handover", "stop-ack";
3366 clocks = <&rpmcc RPM_SMD_BB_CLK1>;
3367 clock-names = "xo";
3369 memory-region = <&adsp_mem>;
3371 qcom,smem-states = <&adsp_smp2p_out 0>;
3372 qcom,smem-state-names = "stop";
3374 power-domains = <&rpmpd MSM8996_VDDCX>;
3375 power-domain-names = "cx";
3379 smd-edge {
3384 qcom,smd-edge = <1>;
3385 qcom,remote-pid = <2>;
3386 #address-cells = <1>;
3387 #size-cells = <0>;
3389 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
3390 compatible = "qcom,apr-v2";
3391 qcom,smd-channels = "apr_audio_svc";
3393 #address-cells = <1>;
3394 #size-cells = <0>;
3401 q6afe: q6afe { label
3402 compatible = "qcom,q6afe";
3405 compatible = "qcom,q6afe-dais";
3406 #address-cells = <1>;
3407 #size-cells = <0>;
3408 #sound-dai-cells = <1>;
3419 compatible = "qcom,q6asm-dais";
3420 #address-cells = <1>;
3421 #size-cells = <0>;
3422 #sound-dai-cells = <1>;
3431 compatible = "qcom,q6adm-routing";
3432 #sound-dai-cells = <0>;
3441 compatible = "qcom,msm8996-apcs-hmss-global";
3444 #mbox-cells = <1>;
3448 #address-cells = <1>;
3449 #size-cells = <1>;
3451 compatible = "arm,armv7-timer-mem";
3453 clock-frequency = <19200000>;
3456 frame-number = <0>;
3464 frame-number = <1>;
3471 frame-number = <2>;
3478 frame-number = <3>;
3485 frame-number = <4>;
3492 frame-number = <5>;
3499 frame-number = <6>;
3511 intc: interrupt-controller@9bc0000 {
3512 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
3513 #interrupt-cells = <3>;
3514 interrupt-controller;
3515 #redistributor-regions = <1>;
3516 redistributor-stride = <0x0 0x40000>;
3526 thermal-zones {
3527 cpu0-thermal {
3528 polling-delay-passive = <250>;
3529 polling-delay = <1000>;
3531 thermal-sensors = <&tsens0 3>;
3534 cpu0_alert0: trip-point0 {
3548 cpu1-thermal {
3549 polling-delay-passive = <250>;
3550 polling-delay = <1000>;
3552 thermal-sensors = <&tsens0 5>;
3555 cpu1_alert0: trip-point0 {
3569 cpu2-thermal {
3570 polling-delay-passive = <250>;
3571 polling-delay = <1000>;
3573 thermal-sensors = <&tsens0 8>;
3576 cpu2_alert0: trip-point0 {
3590 cpu3-thermal {
3591 polling-delay-passive = <250>;
3592 polling-delay = <1000>;
3594 thermal-sensors = <&tsens0 10>;
3597 cpu3_alert0: trip-point0 {
3611 gpu-top-thermal {
3612 polling-delay-passive = <250>;
3613 polling-delay = <1000>;
3615 thermal-sensors = <&tsens1 6>;
3618 gpu1_alert0: trip-point0 {
3625 cooling-maps {
3628 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3633 gpu-bottom-thermal {
3634 polling-delay-passive = <250>;
3635 polling-delay = <1000>;
3637 thermal-sensors = <&tsens1 7>;
3640 gpu2_alert0: trip-point0 {
3647 cooling-maps {
3650 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3655 m4m-thermal {
3656 polling-delay-passive = <250>;
3657 polling-delay = <1000>;
3659 thermal-sensors = <&tsens0 1>;
3662 m4m_alert0: trip-point0 {
3670 l3-or-venus-thermal {
3671 polling-delay-passive = <250>;
3672 polling-delay = <1000>;
3674 thermal-sensors = <&tsens0 2>;
3677 l3_or_venus_alert0: trip-point0 {
3685 cluster0-l2-thermal {
3686 polling-delay-passive = <250>;
3687 polling-delay = <1000>;
3689 thermal-sensors = <&tsens0 7>;
3692 cluster0_l2_alert0: trip-point0 {
3700 cluster1-l2-thermal {
3701 polling-delay-passive = <250>;
3702 polling-delay = <1000>;
3704 thermal-sensors = <&tsens0 12>;
3707 cluster1_l2_alert0: trip-point0 {
3715 camera-thermal {
3716 polling-delay-passive = <250>;
3717 polling-delay = <1000>;
3719 thermal-sensors = <&tsens1 1>;
3722 camera_alert0: trip-point0 {
3730 q6-dsp-thermal {
3731 polling-delay-passive = <250>;
3732 polling-delay = <1000>;
3734 thermal-sensors = <&tsens1 2>;
3737 q6_dsp_alert0: trip-point0 {
3745 mem-thermal {
3746 polling-delay-passive = <250>;
3747 polling-delay = <1000>;
3749 thermal-sensors = <&tsens1 3>;
3752 mem_alert0: trip-point0 {
3760 modemtx-thermal {
3761 polling-delay-passive = <250>;
3762 polling-delay = <1000>;
3764 thermal-sensors = <&tsens1 4>;
3767 modemtx_alert0: trip-point0 {
3777 compatible = "arm,armv8-timer";