Lines Matching full:mmcc
7 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
824 <&mmcc AHB_CLK_SRC>;
852 mmcc: clock-controller@8c0000 { label
853 compatible = "qcom,mmcc-msm8996";
874 assigned-clocks = <&mmcc MMPLL9_PLL>,
875 <&mmcc MMPLL1_PLL>,
876 <&mmcc MMPLL3_PLL>,
877 <&mmcc MMPLL4_PLL>,
878 <&mmcc MMPLL5_PLL>;
896 power-domains = <&mmcc MDSS_GDSC>;
902 clocks = <&mmcc MDSS_AHB_CLK>,
903 <&mmcc MDSS_MDP_CLK>;
920 clocks = <&mmcc MDSS_AHB_CLK>,
921 <&mmcc MDSS_AXI_CLK>,
922 <&mmcc MDSS_MDP_CLK>,
923 <&mmcc SMMU_MDP_AXI_CLK>,
924 <&mmcc MDSS_VSYNC_CLK>;
933 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
934 <&mmcc MDSS_VSYNC_CLK>;
978 clocks = <&mmcc MDSS_MDP_CLK>,
979 <&mmcc MDSS_BYTE0_CLK>,
980 <&mmcc MDSS_AHB_CLK>,
981 <&mmcc MDSS_AXI_CLK>,
982 <&mmcc MMSS_MISC_AHB_CLK>,
983 <&mmcc MDSS_PCLK0_CLK>,
984 <&mmcc MDSS_ESC0_CLK>;
992 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
1033 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_BB_CLK1>;
1046 clocks = <&mmcc MDSS_MDP_CLK>,
1047 <&mmcc MDSS_BYTE1_CLK>,
1048 <&mmcc MDSS_AHB_CLK>,
1049 <&mmcc MDSS_AXI_CLK>,
1050 <&mmcc MMSS_MISC_AHB_CLK>,
1051 <&mmcc MDSS_PCLK1_CLK>,
1052 <&mmcc MDSS_ESC1_CLK>;
1060 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
1101 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_BB_CLK1>;
1118 clocks = <&mmcc MDSS_MDP_CLK>,
1119 <&mmcc MDSS_AHB_CLK>,
1120 <&mmcc MDSS_HDMI_CLK>,
1121 <&mmcc MDSS_HDMI_AHB_CLK>,
1122 <&mmcc MDSS_EXTPCLK_CLK>;
1164 clocks = <&mmcc MDSS_AHB_CLK>,
1185 clocks = <&mmcc GPU_GX_GFX3D_CLK>,
1186 <&mmcc GPU_AHB_CLK>,
1187 <&mmcc GPU_GX_RBBMTIMER_CLK>,
1200 power-domains = <&mmcc GPU_GX_GDSC>;
2076 power-domains = <&mmcc VFE0_GDSC>,
2077 <&mmcc VFE1_GDSC>;
2078 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2079 <&mmcc CAMSS_ISPIF_AHB_CLK>,
2080 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
2081 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
2082 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
2083 <&mmcc CAMSS_CSI0_AHB_CLK>,
2084 <&mmcc CAMSS_CSI0_CLK>,
2085 <&mmcc CAMSS_CSI0PHY_CLK>,
2086 <&mmcc CAMSS_CSI0PIX_CLK>,
2087 <&mmcc CAMSS_CSI0RDI_CLK>,
2088 <&mmcc CAMSS_CSI1_AHB_CLK>,
2089 <&mmcc CAMSS_CSI1_CLK>,
2090 <&mmcc CAMSS_CSI1PHY_CLK>,
2091 <&mmcc CAMSS_CSI1PIX_CLK>,
2092 <&mmcc CAMSS_CSI1RDI_CLK>,
2093 <&mmcc CAMSS_CSI2_AHB_CLK>,
2094 <&mmcc CAMSS_CSI2_CLK>,
2095 <&mmcc CAMSS_CSI2PHY_CLK>,
2096 <&mmcc CAMSS_CSI2PIX_CLK>,
2097 <&mmcc CAMSS_CSI2RDI_CLK>,
2098 <&mmcc CAMSS_CSI3_AHB_CLK>,
2099 <&mmcc CAMSS_CSI3_CLK>,
2100 <&mmcc CAMSS_CSI3PHY_CLK>,
2101 <&mmcc CAMSS_CSI3PIX_CLK>,
2102 <&mmcc CAMSS_CSI3RDI_CLK>,
2103 <&mmcc CAMSS_AHB_CLK>,
2104 <&mmcc CAMSS_VFE0_CLK>,
2105 <&mmcc CAMSS_CSI_VFE0_CLK>,
2106 <&mmcc CAMSS_VFE0_AHB_CLK>,
2107 <&mmcc CAMSS_VFE0_STREAM_CLK>,
2108 <&mmcc CAMSS_VFE1_CLK>,
2109 <&mmcc CAMSS_CSI_VFE1_CLK>,
2110 <&mmcc CAMSS_VFE1_AHB_CLK>,
2111 <&mmcc CAMSS_VFE1_STREAM_CLK>,
2112 <&mmcc CAMSS_VFE_AHB_CLK>,
2113 <&mmcc CAMSS_VFE_AXI_CLK>;
2167 power-domains = <&mmcc CAMSS_GDSC>;
2168 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2169 <&mmcc CAMSS_CCI_AHB_CLK>,
2170 <&mmcc CAMSS_CCI_CLK>,
2171 <&mmcc CAMSS_AHB_CLK>;
2176 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
2177 <&mmcc CAMSS_CCI_CLK>;
2208 clocks = <&mmcc GPU_AHB_CLK>,
2212 power-domains = <&mmcc GPU_GDSC>;
2219 power-domains = <&mmcc VENUS_GDSC>;
2220 clocks = <&mmcc VIDEO_CORE_CLK>,
2221 <&mmcc VIDEO_AHB_CLK>,
2222 <&mmcc VIDEO_AXI_CLK>,
2223 <&mmcc VIDEO_MAXI_CLK>;
2253 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2255 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2260 clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
2262 power-domains = <&mmcc VENUS_CORE1_GDSC>;
2275 clocks = <&mmcc SMMU_MDP_AHB_CLK>,
2276 <&mmcc SMMU_MDP_AXI_CLK>;
2279 power-domains = <&mmcc MDSS_GDSC>;
2294 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
2295 clocks = <&mmcc SMMU_VIDEO_AHB_CLK>,
2296 <&mmcc SMMU_VIDEO_AXI_CLK>;
2310 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
2311 clocks = <&mmcc SMMU_VFE_AHB_CLK>,
2312 <&mmcc SMMU_VFE_AXI_CLK>;