Lines Matching +full:0 +full:x00a00030
26 #clock-cells = <0>;
33 #clock-cells = <0>;
41 #size-cells = <0>;
43 CPU0: cpu@0 {
46 reg = <0x0 0x0>;
50 clocks = <&kryocc 0>;
63 reg = <0x0 0x1>;
67 clocks = <&kryocc 0>;
76 reg = <0x0 0x100>;
93 reg = <0x0 0x101>;
128 CPU_SLEEP_0: cpu-sleep-0 {
131 arm,psci-suspend-param = <0x00000004>;
147 opp-supported-hw = <0x77>;
152 opp-supported-hw = <0x77>;
157 opp-supported-hw = <0x77>;
162 opp-supported-hw = <0x77>;
167 opp-supported-hw = <0x77>;
172 opp-supported-hw = <0x77>;
177 opp-supported-hw = <0x77>;
182 opp-supported-hw = <0x77>;
187 opp-supported-hw = <0x77>;
192 opp-supported-hw = <0x77>;
197 opp-supported-hw = <0x77>;
202 opp-supported-hw = <0x77>;
207 opp-supported-hw = <0x77>;
212 opp-supported-hw = <0x77>;
217 opp-supported-hw = <0x77>;
222 opp-supported-hw = <0x77>;
235 opp-supported-hw = <0x77>;
240 opp-supported-hw = <0x77>;
245 opp-supported-hw = <0x77>;
250 opp-supported-hw = <0x77>;
255 opp-supported-hw = <0x77>;
260 opp-supported-hw = <0x77>;
265 opp-supported-hw = <0x77>;
270 opp-supported-hw = <0x77>;
275 opp-supported-hw = <0x77>;
280 opp-supported-hw = <0x77>;
285 opp-supported-hw = <0x77>;
290 opp-supported-hw = <0x77>;
295 opp-supported-hw = <0x77>;
300 opp-supported-hw = <0x77>;
305 opp-supported-hw = <0x77>;
310 opp-supported-hw = <0x77>;
315 opp-supported-hw = <0x77>;
320 opp-supported-hw = <0x77>;
325 opp-supported-hw = <0x77>;
330 opp-supported-hw = <0x77>;
335 opp-supported-hw = <0x77>;
340 opp-supported-hw = <0x77>;
345 opp-supported-hw = <0x77>;
350 opp-supported-hw = <0x77>;
355 opp-supported-hw = <0x77>;
363 qcom,dload-mode = <&tcsr_2 0x13000>;
370 reg = <0x0 0x80000000 0x0 0x0>;
384 reg = <0x0 0x85800000 0x0 0x600000>;
389 reg = <0x0 0x85e00000 0x0 0x200000>;
394 reg = <0x0 0x86000000 0x0 0x200000>;
399 reg = <0x0 0x86200000 0x0 0x2600000>;
406 size = <0x0 0x200000>;
407 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
415 reg = <0x0 0x88800000 0x0 0x6200000>;
420 reg = <0x0 0x8ea00000 0x0 0x1b00000>;
425 reg = <0x0 0x90500000 0x0 0xa00000>;
431 reg = <0x0 0x90f00000 0x0 0x100000>;
436 reg = <0x0 0x91000000 0x0 0x500000>;
441 reg = <0x0 0x91500000 0x0 0x200000>;
453 mboxes = <&apcs_glb 0>;
512 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
516 qcom,local-pid = <0>;
540 qcom,local-pid = <0>;
564 qcom,local-pid = <0>;
583 ranges = <0 0 0 0xffffffff>;
588 reg = <0x00034000 0x488>;
591 ranges = <0x0 0x00034000 0x4000>;
606 reg = <0x1000 0x130>,
607 <0x1200 0x200>,
608 <0x1400 0x1dc>;
615 #clock-cells = <0>;
618 #phy-cells = <0>;
622 reg = <0x2000 0x130>,
623 <0x2200 0x200>,
624 <0x2400 0x1dc>;
631 #clock-cells = <0>;
634 #phy-cells = <0>;
638 reg = <0x3000 0x130>,
639 <0x3200 0x200>,
640 <0x3400 0x1dc>;
647 #clock-cells = <0>;
650 #phy-cells = <0>;
656 reg = <0x00068000 0x6000>;
661 reg = <0x00074000 0x8ff>;
666 reg = <0x24e 0x2>;
671 reg = <0x24f 0x1>;
676 reg = <0x133 0x1>;
683 reg = <0x00083000 0x1000>;
693 reg = <0x00300000 0x90000>;
702 <0>, <0>, <0>;
717 reg = <0x00408000 0x5a000>;
726 reg = <0x004a9000 0x1000>, /* TM */
727 <0x004a8000 0x1000>; /* SROT */
737 reg = <0x004ad000 0x1000>, /* TM */
738 <0x004ac000 0x1000>; /* SROT */
748 reg = <0x00644000 0x24000>;
753 qcom,ee = <0>;
759 reg = <0x0067a000 0x6000>;
770 reg = <0x00500000 0x1000>;
779 reg = <0x00524000 0x1c000>;
788 reg = <0x00543000 0x6000>;
801 reg = <0x00562000 0x5000>;
810 reg = <0x00583000 0x7000>;
819 reg = <0x005a4000 0x1c000>;
829 reg = <0x005c0000 0x3000>;
838 reg = <0x00740000 0x20000>;
844 reg = <0x00760000 0x20000>;
849 reg = <0x007a0000 0x18000>;
857 reg = <0x008c0000 0x40000>;
862 <&dsi0_phy 0>,
863 <0>,
864 <0>,
865 <0>;
889 reg = <0x00900000 0x1000>,
890 <0x009b0000 0x1040>,
891 <0x009b8000 0x1040>;
914 reg = <0x00901000 0x90000>;
918 interrupts = <0>;
931 iommus = <&mdp_smmu 0>;
945 #size-cells = <0>;
947 port@0 {
948 reg = <0>;
972 reg = <0x00994000 0x400>;
993 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
1000 #size-cells = <0>;
1004 #size-cells = <0>;
1006 port@0 {
1007 reg = <0>;
1023 reg = <0x00994400 0x100>,
1024 <0x00994500 0x300>,
1025 <0x00994800 0x188>;
1031 #phy-cells = <0>;
1040 reg = <0x00996000 0x400>;
1061 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
1068 #size-cells = <0>;
1072 #size-cells = <0>;
1074 port@0 {
1075 reg = <0>;
1091 reg = <0x00996400 0x100>,
1092 <0x00996500 0x300>,
1093 <0x00996800 0x188>;
1099 #phy-cells = <0>;
1108 reg = <0x009a0000 0x50c>,
1109 <0x00070000 0x6158>,
1110 <0x009e0000 0xfff>;
1137 #size-cells = <0>;
1139 port@0 {
1140 reg = <0>;
1149 #phy-cells = <0>;
1151 reg = <0x009a0600 0x1c4>,
1152 <0x009a0a00 0x124>,
1153 <0x009a0c00 0x124>,
1154 <0x009a0e00 0x124>,
1155 <0x009a1000 0x124>,
1156 <0x009a1200 0x0c8>;
1171 #clock-cells = <0>;
1180 reg = <0x00b00000 0x3f000>;
1183 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
1201 iommus = <&adreno_smmu 0>;
1217 * bin (1 << 0). All the rest are available on
1222 opp-supported-hw = <0x01>;
1226 opp-supported-hw = <0x01>;
1230 opp-supported-hw = <0xFF>;
1234 opp-supported-hw = <0xFF>;
1238 opp-supported-hw = <0xFF>;
1242 opp-supported-hw = <0xFF>;
1246 opp-supported-hw = <0xFF>;
1257 reg = <0x01010000 0x300000>;
1260 gpio-ranges = <&tlmm 0 0 150>;
1763 reg = <0x00290000 0x10000>;
1768 reg = <0x0400f000 0x1000>,
1769 <0x04400000 0x800000>,
1770 <0x04c00000 0x800000>,
1771 <0x05800000 0x200000>,
1772 <0x0400a000 0x002100>;
1776 qcom,ee = <0>;
1777 qcom,channel = <0>;
1779 #size-cells = <0>;
1784 agnoc@0 {
1795 bus-range = <0x00 0xff>;
1798 reg = <0x00600000 0x2000>,
1799 <0x0c000000 0xf1d>,
1800 <0x0c000f20 0xa8>,
1801 <0x0c100000 0x100000>;
1809 ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
1810 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
1817 interrupt-map-mask = <0 0 0 0x7>;
1818 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1819 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1820 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1821 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1824 pinctrl-0 = <&pcie0_state_on>;
1827 linux,pci-domain = <0>;
1846 bus-range = <0x00 0xff>;
1851 reg = <0x00608000 0x2000>,
1852 <0x0d000000 0xf1d>,
1853 <0x0d000f20 0xa8>,
1854 <0x0d100000 0x100000>;
1863 ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
1864 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
1871 interrupt-map-mask = <0 0 0 0x7>;
1872 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1873 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1874 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1875 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1878 pinctrl-0 = <&pcie1_state_on>;
1899 bus-range = <0x00 0xff>;
1902 reg = <0x00610000 0x2000>,
1903 <0x0e000000 0xf1d>,
1904 <0x0e000f20 0xa8>,
1905 <0x0e100000 0x100000>;
1914 ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
1915 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
1922 interrupt-map-mask = <0 0 0 0x7>;
1923 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1924 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1925 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1926 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1929 pinctrl-0 = <&pcie2_state_on>;
1950 reg = <0x00624000 0x2500>;
1984 <0 0>,
1985 <0 0>,
1986 <0 0>,
1987 <0 0>,
1989 <0 0>,
1990 <0 0>,
1991 <0 0>,
1992 <0 0>,
1993 <0 0>;
2006 reg = <0x00627000 0x1c4>;
2014 resets = <&ufshc 0>;
2019 reg = <0x627400 0x12c>,
2020 <0x627600 0x200>,
2021 <0x627c00 0x1b4>;
2022 #phy-cells = <0>;
2028 reg = <0x00a34000 0x1000>,
2029 <0x00a00030 0x4>,
2030 <0x00a35000 0x1000>,
2031 <0x00a00038 0x4>,
2032 <0x00a36000 0x1000>,
2033 <0x00a00040 0x4>,
2034 <0x00a30000 0x100>,
2035 <0x00a30400 0x100>,
2036 <0x00a30800 0x100>,
2037 <0x00a30c00 0x100>,
2038 <0x00a31000 0x500>,
2039 <0x00a00020 0x10>,
2040 <0x00a10000 0x1000>,
2041 <0x00a14000 0x1000>;
2150 iommus = <&vfe_smmu 0>,
2157 #size-cells = <0>;
2164 #size-cells = <0>;
2165 reg = <0xa0c000 0x1000>;
2180 pinctrl-0 = <&cci0_default &cci1_default>;
2183 cci_i2c0: i2c-bus@0 {
2184 reg = <0>;
2187 #size-cells = <0>;
2194 #size-cells = <0>;
2200 reg = <0x00b40000 0x10000>;
2217 reg = <0x00c00000 0xff000>;
2228 iommus = <&venus_smmu 0x00>,
2229 <&venus_smmu 0x01>,
2230 <&venus_smmu 0x0a>,
2231 <&venus_smmu 0x07>,
2232 <&venus_smmu 0x0e>,
2233 <&venus_smmu 0x0f>,
2234 <&venus_smmu 0x08>,
2235 <&venus_smmu 0x09>,
2236 <&venus_smmu 0x0b>,
2237 <&venus_smmu 0x0c>,
2238 <&venus_smmu 0x0d>,
2239 <&venus_smmu 0x10>,
2240 <&venus_smmu 0x11>,
2241 <&venus_smmu 0x21>,
2242 <&venus_smmu 0x28>,
2243 <&venus_smmu 0x29>,
2244 <&venus_smmu 0x2b>,
2245 <&venus_smmu 0x2c>,
2246 <&venus_smmu 0x2d>,
2247 <&venus_smmu 0x31>;
2268 reg = <0x00d00000 0x10000>;
2284 reg = <0x00d40000 0x20000>;
2304 reg = <0x00da0000 0x10000>;
2320 reg = <0x01600000 0x20000>;
2346 reg = <0x01c00000 0x4000>;
2348 interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>,
2349 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2365 qcom,smem-states = <&slpi_smp2p_out 0>;
2385 reg = <0x2080000 0x100>,
2386 <0x2180000 0x020>;
2389 interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>,
2390 <&mpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2418 qcom,smem-states = <&mpss_smp2p_out 0>;
2421 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x4000>;
2438 qcom,smd-edge = <0>;
2445 reg = <0x3002000 0x1000>,
2446 <0x8280000 0x180000>;
2464 reg = <0x3020000 0x1000>;
2481 reg = <0x3021000 0x1000>;
2488 #size-cells = <0>;
2511 reg = <0x3022000 0x1000>;
2518 #size-cells = <0>;
2541 reg = <0x3023000 0x1000>;
2559 reg = <0x3025000 0x1000>;
2566 #size-cells = <0>;
2568 port@0 {
2569 reg = <0>;
2605 reg = <0x3026000 0x1000>;
2621 #size-cells = <0>;
2623 port@0 {
2624 reg = <0>;
2643 reg = <0x3027000 0x1000>;
2669 reg = <0x3028000 0x1000>;
2687 reg = <0x3810000 0x1000>;
2697 reg = <0x3840000 0x1000>;
2716 reg = <0x3910000 0x1000>;
2726 reg = <0x3940000 0x1000>;
2743 funnel@39b0000 { /* APSS Funnel 0 */
2745 reg = <0x39b0000 0x1000>;
2752 #size-cells = <0>;
2754 port@0 {
2755 reg = <0>;
2781 reg = <0x3a10000 0x1000>;
2791 reg = <0x3a40000 0x1000>;
2810 reg = <0x3b10000 0x1000>;
2820 reg = <0x3b40000 0x1000>;
2839 reg = <0x3bb0000 0x1000>;
2846 #size-cells = <0>;
2848 port@0 {
2849 reg = <0>;
2875 reg = <0x3bc0000 0x1000>;
2882 #size-cells = <0>;
2884 port@0 {
2885 reg = <0>;
2913 reg = <0x06400000 0x90000>;
2923 reg = <0x06af8800 0x400>;
2956 reg = <0x06a00000 0xcc00>;
2957 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
2967 reg = <0x07410000 0x1c4>;
2983 reg = <0x07410200 0x200>,
2984 <0x07410400 0x130>,
2985 <0x07410600 0x1a8>;
2986 #phy-cells = <0>;
2988 #clock-cells = <0>;
2997 reg = <0x07411000 0x180>;
2998 #phy-cells = <0>;
3011 reg = <0x07412000 0x180>;
3012 #phy-cells = <0>;
3025 reg = <0x07464900 0x11c>, <0x07464000 0x800>;
3039 pinctrl-0 = <&sdc1_state_on>;
3049 reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
3063 pinctrl-0 = <&sdc2_state_on>;
3072 reg = <0x07544000 0x2b000>;
3078 qcom,ee = <0>;
3083 reg = <0x07570000 0x1000>;
3089 pinctrl-0 = <&blsp1_uart2_default>;
3098 reg = <0x07575000 0x600>;
3104 pinctrl-0 = <&blsp1_spi1_default>;
3109 #size-cells = <0>;
3115 reg = <0x07577000 0x1000>;
3121 pinctrl-0 = <&blsp1_i2c3_default>;
3126 #size-cells = <0>;
3132 reg = <0x07584000 0x2b000>;
3138 qcom,ee = <0>;
3143 reg = <0x075b0000 0x1000>;
3153 reg = <0x075b1000 0x1000>;
3163 reg = <0x075b5000 0x1000>;
3169 pinctrl-0 = <&blsp2_i2c1_default>;
3174 #size-cells = <0>;
3180 reg = <0x075b6000 0x1000>;
3186 pinctrl-0 = <&blsp2_i2c2_default>;
3191 #size-cells = <0>;
3197 reg = <0x075b7000 0x1000>;
3204 pinctrl-0 = <&blsp2_i2c3_default>;
3209 #size-cells = <0>;
3215 reg = <0x75b9000 0x1000>;
3221 pinctrl-0 = <&blsp2_i2c5_default>;
3225 #size-cells = <0>;
3231 reg = <0x75ba000 0x1000>;
3237 pinctrl-0 = <&blsp2_i2c6_default>;
3242 #size-cells = <0>;
3248 reg = <0x075ba000 0x600>;
3254 pinctrl-0 = <&blsp2_spi6_default>;
3259 #size-cells = <0>;
3265 reg = <0x076f8800 0x400>;
3291 reg = <0x07600000 0xcc00>;
3292 interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
3304 reg = <0x09184000 0x32000>;
3306 interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
3314 reg = <0x091c0000 0x2C000>;
3316 interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
3321 #size-cells = <0>;
3329 reg = <0 0>;
3333 pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
3337 reg = <1 0>;
3356 reg = <0x09300000 0x80000>;
3358 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
3359 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3371 qcom,smem-states = <&adsp_smp2p_out 0>;
3387 #size-cells = <0>;
3394 #size-cells = <0>;
3407 #size-cells = <0>;
3421 #size-cells = <0>;
3432 #sound-dai-cells = <0>;
3442 reg = <0x09820000 0x1000>;
3452 reg = <0x09840000 0x1000>;
3456 frame-number = <0>;
3459 reg = <0x09850000 0x1000>,
3460 <0x09860000 0x1000>;
3466 reg = <0x09870000 0x1000>;
3473 reg = <0x09880000 0x1000>;
3480 reg = <0x09890000 0x1000>;
3487 reg = <0x098a0000 0x1000>;
3494 reg = <0x098b0000 0x1000>;
3501 reg = <0x098c0000 0x1000>;
3508 reg = <0x09a10000 0x1000>;
3516 redistributor-stride = <0x0 0x40000>;
3517 reg = <0x09bc0000 0x10000>,
3518 <0x09c00000 0x100000>;