Lines Matching +full:msm +full:- +full:uartdm +full:- +full:v1
1 // SPDX-License-Identifier: BSD-3-Clause
4 #include <dt-bindings/clock/qcom,gcc-msm8953.h>
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/power/qcom-rpmpd.h>
8 #include <dt-bindings/thermal/thermal.h>
11 interrupt-parent = <&intc>;
13 #address-cells = <2>;
14 #size-cells = <2>;
19 sleep_clk: sleep-clk {
20 compatible = "fixed-clock";
21 #clock-cells = <0>;
22 clock-frequency = <32768>;
25 xo_board: xo-board {
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <19200000>;
29 clock-output-names = "xo";
34 #address-cells = <1>;
35 #size-cells = <0>;
39 compatible = "arm,cortex-a53";
41 enable-method = "psci";
42 capacity-dmips-mhz = <1024>;
43 next-level-cache = <&L2_0>;
44 #cooling-cells = <2>;
46 l1-icache {
49 l1-dcache {
56 compatible = "arm,cortex-a53";
58 enable-method = "psci";
59 capacity-dmips-mhz = <1024>;
60 next-level-cache = <&L2_0>;
61 #cooling-cells = <2>;
63 l1-icache {
66 l1-dcache {
73 compatible = "arm,cortex-a53";
75 enable-method = "psci";
76 capacity-dmips-mhz = <1024>;
77 next-level-cache = <&L2_0>;
78 #cooling-cells = <2>;
80 l1-icache {
83 l1-dcache {
90 compatible = "arm,cortex-a53";
92 enable-method = "psci";
93 capacity-dmips-mhz = <1024>;
94 next-level-cache = <&L2_0>;
95 #cooling-cells = <2>;
97 l1-icache {
100 l1-dcache {
107 compatible = "arm,cortex-a53";
109 enable-method = "psci";
110 capacity-dmips-mhz = <1024>;
111 next-level-cache = <&L2_1>;
112 #cooling-cells = <2>;
114 l1-icache {
117 l1-dcache {
124 compatible = "arm,cortex-a53";
126 enable-method = "psci";
127 capacity-dmips-mhz = <1024>;
128 next-level-cache = <&L2_1>;
129 #cooling-cells = <2>;
131 l1-icache {
134 l1-dcache {
141 compatible = "arm,cortex-a53";
143 enable-method = "psci";
144 capacity-dmips-mhz = <1024>;
145 next-level-cache = <&L2_1>;
146 #cooling-cells = <2>;
148 l1-icache {
151 l1-dcache {
158 compatible = "arm,cortex-a53";
160 enable-method = "psci";
161 capacity-dmips-mhz = <1024>;
162 next-level-cache = <&L2_1>;
163 #cooling-cells = <2>;
165 l1-icache {
168 l1-dcache {
173 cpu-map {
205 L2_0: l2-cache_0 {
207 cache-level = <2>;
210 L2_1: l2-cache_1 {
212 cache-level = <2>;
218 compatible = "qcom,scm-msm8953", "qcom,scm";
222 clock-names = "core", "bus", "iface";
223 #reset-cells = <1>;
234 compatible = "arm,cortex-a53-pmu";
239 compatible = "arm,psci-1.0";
243 reserved-memory {
244 #address-cells = <2>;
245 #size-cells = <2>;
249 compatible = "shared-dma-pool";
251 no-map;
256 no-map;
262 qcom,rpm-msg-ram = <&rpm_msg_ram>;
264 no-map;
269 no-map;
274 no-map;
279 no-map;
284 no-map;
289 no-map;
294 no-map;
299 no-map;
304 no-map;
308 compatible = "qcom,rmtfs-mem";
310 no-map;
312 qcom,client-id = <1>;
322 qcom,smd-edge = <15>;
324 rpm_requests: rpm-requests {
325 compatible = "qcom,rpm-msm8953";
326 qcom,smd-channels = "rpm_requests";
329 compatible = "qcom,rpmcc-msm8953", "qcom,rpmcc";
331 clock-names = "xo";
332 #clock-cells = <1>;
335 rpmpd: power-controller {
336 compatible = "qcom,msm8953-rpmpd";
337 #power-domain-cells = <1>;
338 operating-points-v2 = <&rpmpd_opp_table>;
341 clock-names = "ref";
343 rpmpd_opp_table: opp-table {
344 compatible = "operating-points-v2";
347 opp-level = <RPM_SMD_LEVEL_RETENTION>;
351 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
355 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
359 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
363 opp-level = <RPM_SMD_LEVEL_SVS>;
367 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
371 opp-level = <RPM_SMD_LEVEL_NOM>;
375 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
379 opp-level = <RPM_SMD_LEVEL_TURBO>;
390 #address-cells = <1>;
391 #size-cells = <0>;
393 qcom,ipc-1 = <&apcs 8 13>;
394 qcom,ipc-3 = <&apcs 8 19>;
399 #qcom,smem-state-cells = <1>;
404 #address-cells = <1>;
405 #size-cells = <1>;
407 compatible = "simple-bus";
410 compatible = "qcom,rpm-msg-ram";
415 compatible = "qcom,msm8953-qusb2-phy";
417 #phy-cells = <0>;
421 clock-names = "cfg_ahb", "ref";
423 qcom,tcsr-syscon = <&tcsr_phy_clk_scheme_sel>;
434 clock-names = "core";
437 tsens0: thermal-sensor@4a9000 {
438 compatible = "qcom,msm8953-tsens", "qcom,tsens-v2";
444 interrupt-names = "uplow", "critical";
445 #thermal-sensor-cells = <1>;
454 compatible = "qcom,msm8953-pinctrl";
457 gpio-controller;
458 gpio-ranges = <&tlmm 0 0 155>;
459 #gpio-cells = <2>;
460 interrupt-controller;
461 #interrupt-cells = <2>;
463 uart_console_active: uart-console-active-pins {
466 drive-strength = <2>;
467 bias-disable;
470 uart_console_sleep: uart-console-sleep-pins {
473 drive-strength = <2>;
474 bias-pull-down;
477 sdc1_clk_on: sdc1-clk-on-pins {
479 bias-disable;
480 drive-strength = <16>;
483 sdc1_clk_off: sdc1-clk-off-pins {
485 bias-disable;
486 drive-strength = <2>;
489 sdc1_cmd_on: sdc1-cmd-on-pins {
491 bias-disable;
492 drive-strength = <10>;
495 sdc1_cmd_off: sdc1-cmd-off-pins {
497 bias-disable;
498 drive-strength = <2>;
501 sdc1_data_on: sdc1-data-on-pins {
503 bias-pull-up;
504 drive-strength = <10>;
507 sdc1_data_off: sdc1-data-off-pins {
509 bias-pull-up;
510 drive-strength = <2>;
513 sdc1_rclk_on: sdc1-rclk-on-pins {
515 bias-pull-down;
518 sdc1_rclk_off: sdc1-rclk-off-pins {
520 bias-pull-down;
523 sdc2_clk_on: sdc2-clk-on-pins {
525 drive-strength = <16>;
526 bias-disable;
529 sdc2_clk_off: sdc2-clk-off-pins {
531 bias-disable;
532 drive-strength = <2>;
535 sdc2_cmd_on: sdc2-cmd-on-pins {
537 bias-pull-up;
538 drive-strength = <10>;
541 sdc2_cmd_off: sdc2-cmd-off-pins {
543 bias-pull-up;
544 drive-strength = <2>;
547 sdc2_data_on: sdc2-data-on-pins {
549 bias-pull-up;
550 drive-strength = <10>;
553 sdc2_data_off: sdc2-data-off-pins {
555 bias-pull-up;
556 drive-strength = <2>;
559 sdc2_cd_on: cd-on-pins {
562 drive-strength = <2>;
563 bias-pull-up;
566 sdc2_cd_off: cd-off-pins {
569 drive-strength = <2>;
570 bias-disable;
573 gpio_key_default: gpio-key-default-pins {
576 drive-strength = <2>;
577 bias-pull-up;
580 i2c_1_default: i2c-1-default-pins {
583 drive-strength = <2>;
584 bias-disable;
587 i2c_1_sleep: i2c-1-sleep-pins {
590 drive-strength = <2>;
591 bias-disable;
594 i2c_2_default: i2c-2-default-pins {
597 drive-strength = <2>;
598 bias-disable;
601 i2c_2_sleep: i2c-2-sleep-pins {
604 drive-strength = <2>;
605 bias-disable;
608 i2c_3_default: i2c-3-default-pins {
611 drive-strength = <2>;
612 bias-disable;
615 i2c_3_sleep: i2c-3-sleep-pins {
618 drive-strength = <2>;
619 bias-disable;
622 i2c_4_default: i2c-4-default-pins {
625 drive-strength = <2>;
626 bias-disable;
629 i2c_4_sleep: i2c-4-sleep-pins {
632 drive-strength = <2>;
633 bias-disable;
636 i2c_5_default: i2c-5-default-pins {
639 drive-strength = <2>;
640 bias-disable;
643 i2c_5_sleep: i2c-5-sleep-pins {
646 drive-strength = <2>;
647 bias-disable;
650 i2c_6_default: i2c-6-default-pins {
653 drive-strength = <2>;
654 bias-disable;
657 i2c_6_sleep: i2c-6-sleep-pins {
660 drive-strength = <2>;
661 bias-disable;
664 i2c_7_default: i2c-7-default-pins {
667 drive-strength = <2>;
668 bias-disable;
671 i2c_7_sleep: i2c-7-sleep-pins {
674 drive-strength = <2>;
675 bias-disable;
678 i2c_8_default: i2c-8-default-pins {
681 drive-strength = <2>;
682 bias-disable;
685 i2c_8_sleep: i2c-8-sleep-pins {
688 drive-strength = <2>;
689 bias-disable;
693 gcc: clock-controller@1800000 {
694 compatible = "qcom,gcc-msm8953";
696 #clock-cells = <1>;
697 #reset-cells = <1>;
698 #power-domain-cells = <1>;
705 clock-names = "xo",
714 compatible = "qcom,tcsr-mutex";
716 #hwlock-cells = <1>;
720 compatible = "qcom,tcsr-msm8953", "syscon";
725 compatible = "qcom,tcsr-msm8953", "syscon";
730 compatible = "qcom,spmi-pmic-arb";
736 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
737 interrupt-names = "periph_irq";
741 interrupt-controller;
743 #interrupt-cells = <4>;
744 #address-cells = <2>;
745 #size-cells = <0>;
749 compatible = "qcom,msm8953-dwc3", "qcom,dwc3";
751 #address-cells = <1>;
752 #size-cells = <1>;
757 interrupt-names = "hs_phy_irq", "ss_phy_irq";
764 clock-names = "cfg_noc",
770 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
772 assigned-clock-rates = <19200000>, <133330000>;
774 power-domains = <&gcc USB30_GDSC>;
776 qcom,select-utmi-as-pipe-clk;
785 phy-names = "usb2-phy";
787 snps,usb2-gadget-lpm-disable;
788 snps,dis-u1-entry-quirk;
789 snps,dis-u2-entry-quirk;
790 snps,is-utmi-l1-suspend;
791 snps,hird-threshold = /bits/ 8 <0x00>;
793 maximum-speed = "high-speed";
799 compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4";
802 reg-names = "hc", "core";
806 interrupt-names = "hc_irq", "pwr_irq";
811 clock-names = "iface", "core", "xo";
813 power-domains = <&rpmpd MSM8953_VDDCX>;
814 operating-points-v2 = <&sdhc1_opp_table>;
816 pinctrl-names = "default", "sleep";
817 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
818 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
820 mmc-hs400-1_8v;
821 mmc-hs200-1_8v;
822 mmc-ddr-1_8v;
823 bus-width = <8>;
824 non-removable;
828 sdhc1_opp_table: opp-table-sdhc1 {
829 compatible = "operating-points-v2";
831 opp-25000000 {
832 opp-hz = /bits/ 64 <25000000>;
833 required-opps = <&rpmpd_opp_low_svs>;
836 opp-50000000 {
837 opp-hz = /bits/ 64 <50000000>;
838 required-opps = <&rpmpd_opp_svs>;
841 opp-100000000 {
842 opp-hz = /bits/ 64 <100000000>;
843 required-opps = <&rpmpd_opp_svs>;
846 opp-192000000 {
847 opp-hz = /bits/ 64 <192000000>;
848 required-opps = <&rpmpd_opp_nom>;
851 opp-384000000 {
852 opp-hz = /bits/ 64 <384000000>;
853 required-opps = <&rpmpd_opp_nom>;
859 compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4";
862 reg-names = "hc", "core";
866 interrupt-names = "hc_irq", "pwr_irq";
871 clock-names = "iface", "core", "xo";
873 power-domains = <&rpmpd MSM8953_VDDCX>;
874 operating-points-v2 = <&sdhc2_opp_table>;
876 pinctrl-names = "default", "sleep";
877 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
878 pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
880 bus-width = <4>;
884 sdhc2_opp_table: opp-table-sdhc2 {
885 compatible = "operating-points-v2";
887 opp-25000000 {
888 opp-hz = /bits/ 64 <25000000>;
889 required-opps = <&rpmpd_opp_low_svs>;
892 opp-50000000 {
893 opp-hz = /bits/ 64 <50000000>;
894 required-opps = <&rpmpd_opp_svs>;
897 opp-100000000 {
898 opp-hz = /bits/ 64 <100000000>;
899 required-opps = <&rpmpd_opp_svs>;
902 opp-177770000 {
903 opp-hz = /bits/ 64 <177770000>;
904 required-opps = <&rpmpd_opp_nom>;
907 opp-200000000 {
908 opp-hz = /bits/ 64 <200000000>;
909 required-opps = <&rpmpd_opp_nom>;
915 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
920 clock-names = "core", "iface";
926 compatible = "qcom,i2c-qup-v2.2.1";
929 clock-names = "core", "iface";
933 pinctrl-names = "default", "sleep";
934 pinctrl-0 = <&i2c_1_default>;
935 pinctrl-1 = <&i2c_1_sleep>;
937 #address-cells = <1>;
938 #size-cells = <0>;
944 compatible = "qcom,i2c-qup-v2.2.1";
947 clock-names = "core", "iface";
951 pinctrl-names = "default", "sleep";
952 pinctrl-0 = <&i2c_2_default>;
953 pinctrl-1 = <&i2c_2_sleep>;
955 #address-cells = <1>;
956 #size-cells = <0>;
962 compatible = "qcom,i2c-qup-v2.2.1";
965 clock-names = "core", "iface";
968 pinctrl-names = "default", "sleep";
969 pinctrl-0 = <&i2c_3_default>;
970 pinctrl-1 = <&i2c_3_sleep>;
972 #address-cells = <1>;
973 #size-cells = <0>;
979 compatible = "qcom,i2c-qup-v2.2.1";
982 clock-names = "core", "iface";
985 pinctrl-names = "default", "sleep";
986 pinctrl-0 = <&i2c_4_default>;
987 pinctrl-1 = <&i2c_4_sleep>;
989 #address-cells = <1>;
990 #size-cells = <0>;
996 compatible = "qcom,i2c-qup-v2.2.1";
999 clock-names = "core", "iface";
1002 pinctrl-names = "default", "sleep";
1003 pinctrl-0 = <&i2c_5_default>;
1004 pinctrl-1 = <&i2c_5_sleep>;
1006 #address-cells = <1>;
1007 #size-cells = <0>;
1013 compatible = "qcom,i2c-qup-v2.2.1";
1016 clock-names = "core", "iface";
1019 pinctrl-names = "default", "sleep";
1020 pinctrl-0 = <&i2c_6_default>;
1021 pinctrl-1 = <&i2c_6_sleep>;
1023 #address-cells = <1>;
1024 #size-cells = <0>;
1030 compatible = "qcom,i2c-qup-v2.2.1";
1033 clock-names = "core", "iface";
1036 pinctrl-names = "default", "sleep";
1037 pinctrl-0 = <&i2c_7_default>;
1038 pinctrl-1 = <&i2c_7_sleep>;
1040 #address-cells = <1>;
1041 #size-cells = <0>;
1047 compatible = "qcom,i2c-qup-v2.2.1";
1050 clock-names = "core", "iface";
1053 pinctrl-names = "default", "sleep";
1054 pinctrl-0 = <&i2c_8_default>;
1055 pinctrl-1 = <&i2c_8_sleep>;
1057 #address-cells = <1>;
1058 #size-cells = <0>;
1063 intc: interrupt-controller@b000000 {
1064 compatible = "qcom,msm-qgic2";
1065 interrupt-controller;
1066 #interrupt-cells = <3>;
1071 compatible = "qcom,msm8953-apcs-kpss-global", "syscon";
1073 #mbox-cells = <1>;
1077 compatible = "arm,armv7-timer-mem";
1079 #address-cells = <0x01>;
1080 #size-cells = <0x01>;
1084 frame-number = <0>;
1092 frame-number = <1>;
1099 frame-number = <2>;
1106 frame-number = <3>;
1113 frame-number = <4>;
1120 frame-number = <5>;
1127 frame-number = <6>;
1135 thermal-zones {
1136 cpu0-thermal {
1137 polling-delay-passive = <250>;
1138 polling-delay = <1000>;
1139 thermal-sensors = <&tsens0 9>;
1141 cpu0_alert: trip-point0 {
1152 cooling-maps {
1155 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1159 cpu1-thermal {
1160 polling-delay-passive = <250>;
1161 polling-delay = <1000>;
1162 thermal-sensors = <&tsens0 10>;
1164 cpu1_alert: trip-point0 {
1175 cooling-maps {
1178 cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1182 cpu2-thermal {
1183 polling-delay-passive = <250>;
1184 polling-delay = <1000>;
1185 thermal-sensors = <&tsens0 11>;
1187 cpu2_alert: trip-point0 {
1198 cooling-maps {
1201 cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1205 cpu3-thermal {
1206 polling-delay-passive = <250>;
1207 polling-delay = <1000>;
1208 thermal-sensors = <&tsens0 12>;
1210 cpu3_alert: trip-point0 {
1221 cooling-maps {
1224 cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1228 cpu4-thermal {
1229 polling-delay-passive = <250>;
1230 polling-delay = <1000>;
1231 thermal-sensors = <&tsens0 4>;
1233 cpu4_alert: trip-point0 {
1244 cooling-maps {
1247 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1251 cpu5-thermal {
1252 polling-delay-passive = <250>;
1253 polling-delay = <1000>;
1254 thermal-sensors = <&tsens0 5>;
1256 cpu5_alert: trip-point0 {
1267 cooling-maps {
1270 cooling-device = <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1274 cpu6-thermal {
1275 polling-delay-passive = <250>;
1276 polling-delay = <1000>;
1277 thermal-sensors = <&tsens0 6>;
1279 cpu6_alert: trip-point0 {
1290 cooling-maps {
1293 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1297 cpu7-thermal {
1298 polling-delay-passive = <250>;
1299 polling-delay = <1000>;
1300 thermal-sensors = <&tsens0 7>;
1302 cpu7_alert: trip-point0 {
1313 cooling-maps {
1316 cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1323 compatible = "arm,armv8-timer";