Lines Matching +full:0 +full:x500
31 reg = <0 0x80000000 0 0>;
40 reg = <0x0 0x86000000 0x0 0x300000>;
46 reg = <0x0 0x86300000 0x0 0x100000>;
54 reg = <0x0 0x86400000 0x0 0x100000>;
59 reg = <0x0 0x86500000 0x0 0x180000>;
64 reg = <0x0 0x86680000 0x0 0x80000>;
70 reg = <0x0 0x86700000 0x0 0xe0000>;
77 reg = <0x0 0x867e0000 0x0 0x20000>;
82 reg = <0x0 0x86800000 0x0 0x2b00000>;
87 reg = <0x0 0x89300000 0x0 0x600000>;
92 reg = <0x0 0x89900000 0x0 0x600000>;
98 reg = <0 0x8ea00000 0 0x100000>;
105 #clock-cells = <0>;
111 #clock-cells = <0>;
118 #size-cells = <0>;
120 CPU0: cpu@0 {
123 reg = <0x0>;
138 reg = <0x1>;
153 reg = <0x2>;
168 reg = <0x3>;
188 CPU_SLEEP_0: cpu-sleep-0 {
191 arm,psci-suspend-param = <0x40000002>;
203 arm,psci-suspend-param = <0x41000012>;
211 arm,psci-suspend-param = <0x41000032>;
246 qcom,dload-mode = <&tcsr 0x6100>;
260 #power-domain-cells = <0>;
266 #power-domain-cells = <0>;
272 #power-domain-cells = <0>;
278 #power-domain-cells = <0>;
284 #power-domain-cells = <0>;
294 qcom,ipc = <&apcs 8 0>;
348 qcom,local-pid = <0>;
373 qcom,local-pid = <0>;
394 #size-cells = <0>;
399 apps_smsm: apps@0 {
400 reg = <0>;
422 soc: soc@0 {
425 ranges = <0 0 0 0xffffffff>;
430 reg = <0x00022000 0x200>;
437 reg = <0x004ab000 0x4>;
442 reg = <0x0005c000 0x1000>;
446 reg = <0xd0 0x8>;
449 reg = <0xec 0x4>;
455 reg = <0x00060000 0x8000>;
460 reg = <0x00290000 0x10000>;
465 reg = <0x00400000 0x62000>;
474 reg = <0x004a9000 0x1000>, /* TM */
475 <0x004a8000 0x1000>; /* SROT */
486 reg = <0x00500000 0x11000>;
495 reg = <0x00580000 0x14000>;
504 reg = <0x00802000 0x1000>,
505 <0x09280000 0x180000>;
523 /* CTI 0 - TMC connections */
526 reg = <0x00810000 0x1000>;
537 reg = <0x00811000 0x1000>;
549 reg = <0x00820000 0x1000>;
567 reg = <0x00821000 0x1000>;
576 #size-cells = <0>;
580 * 0 - connected to Resource and Power Manger CPU ETM
615 reg = <0x00824000 0x1000>;
624 #size-cells = <0>;
626 port@0 {
627 reg = <0>;
651 reg = <0x00825000 0x1000>;
677 reg = <0x00826000 0x1000>;
695 reg = <0x00841000 0x1000>;
704 #size-cells = <0>;
706 port@0 {
707 reg = <0>;
743 reg = <0x00850000 0x1000>;
752 reg = <0x00852000 0x1000>;
761 reg = <0x00854000 0x1000>;
770 reg = <0x00856000 0x1000>;
778 /* CTI - CPU-0 */
782 reg = <0x00858000 0x1000>;
797 reg = <0x00859000 0x1000>;
812 reg = <0x0085a000 0x1000>;
827 reg = <0x0085b000 0x1000>;
840 reg = <0x0085c000 0x1000>;
861 reg = <0x0085d000 0x1000>;
882 reg = <0x0085e000 0x1000>;
903 reg = <0x0085f000 0x1000>;
924 reg = <0x01000000 0x300000>;
927 gpio-ranges = <&msmgpio 0 0 122>;
938 reg = <0x01800000 0x80000>;
942 <&dsi_phy0 0>,
943 <0>,
944 <0>,
945 <0>;
957 reg = <0x01905000 0x20000>;
963 reg = <0x01937000 0x30000>;
969 reg = <0x01a00000 0x1000>,
970 <0x01ac8000 0x3000>;
993 reg = <0x01a01000 0x89000>;
997 interrupts = <0>;
1012 #size-cells = <0>;
1014 port@0 {
1015 reg = <0>;
1025 reg = <0x01a98000 0x25c>;
1033 assigned-clock-parents = <&dsi_phy0 0>,
1052 #size-cells = <0>;
1056 #size-cells = <0>;
1058 port@0 {
1059 reg = <0>;
1075 reg = <0x01a98300 0xd4>,
1076 <0x01a98500 0x280>,
1077 <0x01a98780 0x30>;
1083 #phy-cells = <0>;
1093 reg = <0x01b0ac00 0x200>,
1094 <0x01b00030 0x4>,
1095 <0x01b0b000 0x200>,
1096 <0x01b00038 0x4>,
1097 <0x01b08000 0x100>,
1098 <0x01b08400 0x100>,
1099 <0x01b0a000 0x500>,
1100 <0x01b00020 0x10>,
1101 <0x01b10000 0x1000>;
1166 #size-cells = <0>;
1173 #size-cells = <0>;
1174 reg = <0x01b0c000 0x1000>;
1186 pinctrl-0 = <&cci0_default>;
1189 cci_i2c0: i2c-bus@0 {
1190 reg = <0>;
1193 #size-cells = <0>;
1199 reg = <0x01c00000 0x20000>;
1235 reg = <0x01d00000 0xff000>;
1260 ranges = <0 0x01e20000 0x40000>;
1261 reg = <0x01ef0000 0x3000>;
1270 reg = <0x3000 0x1000>;
1277 reg = <0x4000 0x1000>;
1284 reg = <0x5000 0x1000>;
1294 ranges = <0 0x01f08000 0x10000>;
1303 reg = <0x1000 0x1000>;
1310 reg = <0x2000 0x1000>;
1317 reg = <0x0200f000 0x001000>,
1318 <0x02400000 0x400000>,
1319 <0x02c00000 0x400000>,
1320 <0x03800000 0x200000>,
1321 <0x0200a000 0x002100>;
1325 qcom,ee = <0>;
1326 qcom,channel = <0>;
1328 #size-cells = <0>;
1335 reg = <0x04044000 0x19000>;
1338 qcom,ee = <0>;
1349 reg = <0x04080000 0x100>,
1350 <0x04020000 0x040>;
1355 <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1372 qcom,smem-states = <&hexagon_smp2p_out 0>;
1375 resets = <&scm 0>;
1378 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1409 qcom,smd-edge = <0>;
1422 #size-cells = <0>;
1435 reg = <0x07702000 0x4>, <0x07702004 0x4>;
1467 reg = <0x07708000 0x10000>;
1471 #size-cells = <0>;
1476 reg = <0x0771c000 0x400>;
1485 reg = <0x07824900 0x11c>, <0x07824000 0x800>;
1503 reg = <0x07864900 0x11c>, <0x07864000 0x800>;
1519 reg = <0x07884000 0x23000>;
1524 qcom,ee = <0>;
1530 reg = <0x078af000 0x200>;
1534 dmas = <&blsp_dma 0>, <&blsp_dma 1>;
1537 pinctrl-0 = <&blsp1_uart1_default>;
1544 reg = <0x078b0000 0x200>;
1551 pinctrl-0 = <&blsp1_uart2_default>;
1558 reg = <0x078b5000 0x500>;
1564 pinctrl-0 = <&i2c1_default>;
1567 #size-cells = <0>;
1573 reg = <0x078b5000 0x500>;
1581 pinctrl-0 = <&spi1_default>;
1584 #size-cells = <0>;
1590 reg = <0x078b6000 0x500>;
1596 pinctrl-0 = <&i2c2_default>;
1599 #size-cells = <0>;
1605 reg = <0x078b6000 0x500>;
1613 pinctrl-0 = <&spi2_default>;
1616 #size-cells = <0>;
1622 reg = <0x078b7000 0x500>;
1628 pinctrl-0 = <&i2c3_default>;
1631 #size-cells = <0>;
1637 reg = <0x078b7000 0x500>;
1645 pinctrl-0 = <&spi3_default>;
1648 #size-cells = <0>;
1654 reg = <0x078b8000 0x500>;
1660 pinctrl-0 = <&i2c4_default>;
1663 #size-cells = <0>;
1669 reg = <0x078b8000 0x500>;
1677 pinctrl-0 = <&spi4_default>;
1680 #size-cells = <0>;
1686 reg = <0x078b9000 0x500>;
1692 pinctrl-0 = <&i2c5_default>;
1695 #size-cells = <0>;
1701 reg = <0x078b9000 0x500>;
1709 pinctrl-0 = <&spi5_default>;
1712 #size-cells = <0>;
1718 reg = <0x078ba000 0x500>;
1724 pinctrl-0 = <&i2c6_default>;
1727 #size-cells = <0>;
1733 reg = <0x078ba000 0x500>;
1741 pinctrl-0 = <&spi6_default>;
1744 #size-cells = <0>;
1750 reg = <0x078d9000 0x200>,
1751 <0x078d9200 0x200>;
1766 ahb-burst-config = <0>;
1776 #phy-cells = <0>;
1779 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
1781 qcom,init-seq = /bits/ 8 <0x0 0x44>,
1782 <0x1 0x6b>,
1783 <0x2 0x24>,
1784 <0x3 0x13>;
1791 reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
1797 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1807 qcom,smem-states = <&wcnss_smp2p_out 0>;
1811 pinctrl-0 = <&wcnss_pin_a>;
1859 reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>,
1860 <0x0b001000 0x1000>, <0x0b004000 0x2000>;
1861 interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1866 reg = <0x0b011000 0x1000>;
1870 #clock-cells = <0>;
1875 reg = <0x0b016000 0x40>;
1876 #clock-cells = <0>;
1886 reg = <0x0b020000 0x1000>;
1890 frame-number = <0>;
1893 reg = <0x0b021000 0x1000>,
1894 <0x0b022000 0x1000>;
1900 reg = <0x0b023000 0x1000>;
1907 reg = <0x0b024000 0x1000>;
1914 reg = <0x0b025000 0x1000>;
1921 reg = <0x0b026000 0x1000>;
1928 reg = <0x0b027000 0x1000>;
1935 reg = <0x0b028000 0x1000>;
1942 reg = <0x0b088000 0x1000>;
1947 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
1948 reg = <0x0b089000 0x1000>;
1954 reg = <0x0b098000 0x1000>;
1959 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
1960 reg = <0x0b099000 0x1000>;
1966 reg = <0x0b0a8000 0x1000>;
1971 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
1972 reg = <0x0b0a9000 0x1000>;
1978 reg = <0x0b0b8000 0x1000>;
1983 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
1984 reg = <0x0b0b9000 0x1000>;
2089 thermal-sensors = <&tsens 0>;