Lines Matching full:gcc
7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
121 clocks = <&gcc GCC_USB1_AUX_CLK>,
122 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
126 resets = <&gcc GCC_USB1_PHY_BCR>,
127 <&gcc GCC_USB3PHY_1_PHY_BCR>;
138 clocks = <&gcc GCC_USB1_PIPE_CLK>;
149 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
153 resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
164 clocks = <&gcc GCC_USB0_AUX_CLK>,
165 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
169 resets = <&gcc GCC_USB0_PHY_BCR>,
170 <&gcc GCC_USB3PHY_0_PHY_BCR>;
181 clocks = <&gcc GCC_USB0_PIPE_CLK>;
192 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
196 resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
207 clocks = <&gcc GCC_PCIE0_AUX_CLK>,
208 <&gcc GCC_PCIE0_AHB_CLK>;
210 resets = <&gcc GCC_PCIE0_PHY_BCR>,
211 <&gcc GCC_PCIE0PHY_PHY_BCR>;
222 clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
235 clocks = <&gcc GCC_PCIE1_AUX_CLK>,
236 <&gcc GCC_PCIE1_AHB_CLK>;
238 resets = <&gcc GCC_PCIE1_PHY_BCR>,
239 <&gcc GCC_PCIE1PHY_PHY_BCR>;
250 clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
262 clocks = <&gcc GCC_MDIO_AHB_CLK>;
271 clocks = <&gcc GCC_PRNG_AHB_CLK>;
280 clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
291 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
292 <&gcc GCC_CRYPTO_AXI_CLK>,
293 <&gcc GCC_CRYPTO_CLK>;
350 gcc: gcc@1800000 { label
351 compatible = "qcom,gcc-ipq8074";
392 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
393 <&gcc GCC_SDCC1_APPS_CLK>,
396 resets = <&gcc GCC_SDCC1_BCR>;
410 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
420 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
421 <&gcc GCC_BLSP1_AHB_CLK>;
430 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
431 <&gcc GCC_BLSP1_AHB_CLK>;
445 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
446 <&gcc GCC_BLSP1_AHB_CLK>;
460 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
461 <&gcc GCC_BLSP1_AHB_CLK>;
476 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
477 <&gcc GCC_BLSP1_AHB_CLK>;
493 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
494 <&gcc GCC_BLSP1_AHB_CLK>;
508 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
509 <&gcc GCC_BLSP1_AHB_CLK>;
523 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
524 <&gcc GCC_BLSP1_AHB_CLK>;
536 clocks = <&gcc GCC_QPIC_AHB_CLK>;
548 clocks = <&gcc GCC_QPIC_CLK>,
549 <&gcc GCC_QPIC_AHB_CLK>;
568 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
569 <&gcc GCC_USB0_MASTER_CLK>,
570 <&gcc GCC_USB0_SLEEP_CLK>,
571 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
577 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
578 <&gcc GCC_USB0_MASTER_CLK>,
579 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
584 power-domains = <&gcc USB0_GDSC>;
586 resets = <&gcc GCC_USB0_BCR>;
610 clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
611 <&gcc GCC_USB1_MASTER_CLK>,
612 <&gcc GCC_USB1_SLEEP_CLK>,
613 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
619 assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
620 <&gcc GCC_USB1_MASTER_CLK>,
621 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
626 power-domains = <&gcc USB1_GDSC>;
628 resets = <&gcc GCC_USB1_BCR>;
770 clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
771 <&gcc GCC_PCIE1_AXI_M_CLK>,
772 <&gcc GCC_PCIE1_AXI_S_CLK>,
773 <&gcc GCC_PCIE1_AHB_CLK>,
774 <&gcc GCC_PCIE1_AUX_CLK>;
780 resets = <&gcc GCC_PCIE1_PIPE_ARES>,
781 <&gcc GCC_PCIE1_SLEEP_ARES>,
782 <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
783 <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
784 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
785 <&gcc GCC_PCIE1_AHB_ARES>,
786 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
832 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
833 <&gcc GCC_PCIE0_AXI_M_CLK>,
834 <&gcc GCC_PCIE0_AXI_S_CLK>,
835 <&gcc GCC_PCIE0_AHB_CLK>,
836 <&gcc GCC_PCIE0_AUX_CLK>;
843 resets = <&gcc GCC_PCIE0_PIPE_ARES>,
844 <&gcc GCC_PCIE0_SLEEP_ARES>,
845 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
846 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
847 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
848 <&gcc GCC_PCIE0_AHB_ARES>,
849 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;