Lines Matching +full:glink +full:- +full:channels
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
10 #include <dt-bindings/reset/qcom,gcc-ipq6018.h>
11 #include <dt-bindings/clock/qcom,apss-ipq.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&intc>;
19 sleep_clk: sleep-clk {
20 compatible = "fixed-clock";
21 clock-frequency = <32000>;
22 #clock-cells = <0>;
26 compatible = "fixed-clock";
27 clock-frequency = <24000000>;
28 #clock-cells = <0>;
33 #address-cells = <1>;
34 #size-cells = <0>;
38 compatible = "arm,cortex-a53";
40 enable-method = "psci";
41 next-level-cache = <&L2_0>;
43 clock-names = "cpu";
44 operating-points-v2 = <&cpu_opp_table>;
45 cpu-supply = <&ipq6018_s2>;
50 compatible = "arm,cortex-a53";
51 enable-method = "psci";
53 next-level-cache = <&L2_0>;
55 clock-names = "cpu";
56 operating-points-v2 = <&cpu_opp_table>;
57 cpu-supply = <&ipq6018_s2>;
62 compatible = "arm,cortex-a53";
63 enable-method = "psci";
65 next-level-cache = <&L2_0>;
67 clock-names = "cpu";
68 operating-points-v2 = <&cpu_opp_table>;
69 cpu-supply = <&ipq6018_s2>;
74 compatible = "arm,cortex-a53";
75 enable-method = "psci";
77 next-level-cache = <&L2_0>;
79 clock-names = "cpu";
80 operating-points-v2 = <&cpu_opp_table>;
81 cpu-supply = <&ipq6018_s2>;
84 L2_0: l2-cache {
86 cache-level = <0x2>;
90 cpu_opp_table: opp-table-cpu {
91 compatible = "operating-points-v2";
92 opp-shared;
94 opp-864000000 {
95 opp-hz = /bits/ 64 <864000000>;
96 opp-microvolt = <725000>;
97 clock-latency-ns = <200000>;
99 opp-1056000000 {
100 opp-hz = /bits/ 64 <1056000000>;
101 opp-microvolt = <787500>;
102 clock-latency-ns = <200000>;
104 opp-1320000000 {
105 opp-hz = /bits/ 64 <1320000000>;
106 opp-microvolt = <862500>;
107 clock-latency-ns = <200000>;
109 opp-1440000000 {
110 opp-hz = /bits/ 64 <1440000000>;
111 opp-microvolt = <925000>;
112 clock-latency-ns = <200000>;
114 opp-1608000000 {
115 opp-hz = /bits/ 64 <1608000000>;
116 opp-microvolt = <987500>;
117 clock-latency-ns = <200000>;
119 opp-1800000000 {
120 opp-hz = /bits/ 64 <1800000000>;
121 opp-microvolt = <1062500>;
122 clock-latency-ns = <200000>;
128 compatible = "qcom,scm-ipq6018", "qcom,scm";
133 compatible = "arm,cortex-a53-pmu";
139 compatible = "arm,psci-1.0";
143 reserved-memory {
144 #address-cells = <2>;
145 #size-cells = <2>;
150 no-map;
155 no-map;
160 no-map;
165 no-map;
171 memory-region = <&smem_region>;
176 #address-cells = <2>;
177 #size-cells = <2>;
179 dma-ranges;
180 compatible = "simple-bus";
183 compatible = "qcom,prng-ee";
186 clock-names = "core";
189 cryptobam: dma-controller@704000 {
190 compatible = "qcom,bam-v1.7.0";
194 clock-names = "bam_clk";
195 #dma-cells = <1>;
197 qcom,controlled-remotely;
201 compatible = "qcom,crypto-v5.1";
206 clock-names = "iface", "bus", "core";
208 dma-names = "rx", "tx";
212 compatible = "qcom,ipq6018-pinctrl";
215 gpio-controller;
216 #gpio-cells = <2>;
217 gpio-ranges = <&tlmm 0 0 80>;
218 interrupt-controller;
219 #interrupt-cells = <2>;
221 serial_3_pins: serial3-pinmux {
224 drive-strength = <8>;
225 bias-pull-down;
228 qpic_pins: qpic-pins {
235 drive-strength = <8>;
236 bias-disable;
241 compatible = "qcom,gcc-ipq6018";
244 clock-names = "xo", "sleep_clk";
245 #clock-cells = <1>;
246 #reset-cells = <1>;
250 compatible = "qcom,ipq6018-tcsr-mutex", "qcom,tcsr-mutex";
252 #hwlock-cells = <1>;
256 compatible = "qcom,tcsr-ipq6018", "syscon";
260 blsp_dma: dma-controller@7884000 {
261 compatible = "qcom,bam-v1.7.0";
265 clock-names = "bam_clk";
266 #dma-cells = <1>;
271 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
276 clock-names = "core", "iface";
281 compatible = "qcom,spi-qup-v2.2.1";
282 #address-cells = <1>;
283 #size-cells = <0>;
286 spi-max-frequency = <50000000>;
289 clock-names = "core", "iface";
291 dma-names = "tx", "rx";
296 compatible = "qcom,spi-qup-v2.2.1";
297 #address-cells = <1>;
298 #size-cells = <0>;
301 spi-max-frequency = <50000000>;
304 clock-names = "core", "iface";
306 dma-names = "tx", "rx";
311 compatible = "qcom,i2c-qup-v2.2.1";
312 #address-cells = <1>;
313 #size-cells = <0>;
318 clock-names = "core", "iface";
319 clock-frequency = <400000>;
321 dma-names = "tx", "rx";
326 compatible = "qcom,i2c-qup-v2.2.1";
327 #address-cells = <1>;
328 #size-cells = <0>;
333 clock-names = "core", "iface";
334 clock-frequency = <400000>;
336 dma-names = "tx", "rx";
340 qpic_bam: dma-controller@7984000 {
341 compatible = "qcom,bam-v1.7.0";
345 clock-names = "bam_clk";
346 #dma-cells = <1>;
352 compatible = "qcom,ipq6018-nand";
354 #address-cells = <1>;
355 #size-cells = <0>;
358 clock-names = "core", "aon";
363 dma-names = "tx", "rx", "cmd";
364 pinctrl-0 = <&qpic_pins>;
365 pinctrl-names = "default";
369 intc: interrupt-controller@b000000 {
370 compatible = "qcom,msm-qgic2";
371 #address-cells = <2>;
372 #size-cells = <2>;
373 interrupt-controller;
374 #interrupt-cells = <0x3>;
383 compatible = "arm,gic-v2m-frame";
384 msi-controller;
390 compatible = "qcom,ipq6018-qmp-pcie-phy";
393 #address-cells = <2>;
394 #size-cells = <2>;
399 clock-names = "aux", "cfg_ahb";
403 reset-names = "phy",
410 #phy-cells = <0>;
413 clock-names = "pipe0";
414 clock-output-names = "gcc_pcie0_pipe_clk_src";
415 #clock-cells = <0>;
420 compatible = "qcom,pcie-ipq6018";
426 reg-names = "dbi", "elbi", "atu", "parf", "config";
429 linux,pci-domain = <0>;
430 bus-range = <0x00 0xff>;
431 num-lanes = <1>;
432 max-link-speed = <3>;
433 #address-cells = <3>;
434 #size-cells = <2>;
437 phy-names = "pciephy";
442 0 0xfde0000>; /* non-prefetchable memory */
445 interrupt-names = "msi";
447 #interrupt-cells = <1>;
448 interrupt-map-mask = <0 0 0 0x7>;
449 interrupt-map = <0 0 0 1 &intc 0 75
463 clock-names = "iface",
477 reset-names = "pipe",
490 compatible = "qcom,kpss-wdt";
494 timeout-sec = <10>;
498 compatible = "qcom,ipq6018-apcs-apps-global";
500 #clock-cells = <1>;
502 clock-names = "pll", "xo";
503 #mbox-cells = <1>;
507 compatible = "qcom,ipq6018-a53pll";
509 #clock-cells = <0>;
511 clock-names = "xo";
515 compatible = "arm,armv8-timer";
523 #address-cells = <1>;
524 #size-cells = <1>;
526 compatible = "arm,armv7-timer-mem";
530 frame-number = <0>;
538 frame-number = <1>;
545 frame-number = <2>;
552 frame-number = <3>;
559 frame-number = <4>;
566 frame-number = <5>;
573 frame-number = <6>;
581 compatible = "qcom,ipq6018-wcss-pil";
584 reg-names = "qdsp6",
586 interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>,
591 interrupt-names = "wdog",
595 "stop-ack";
601 reset-names = "wcss_aon_reset",
606 clock-names = "prng";
608 qcom,halt-regs = <&tcsr 0x18000 0x1b000 0xe000>;
610 qcom,smem-states = <&wcss_smp2p_out 0>,
612 qcom,smem-state-names = "shutdown",
615 memory-region = <&q6_region>;
617 glink-edge {
620 qcom,remote-pid = <1>;
624 qcom,glink-channels = "IPCRTR";
630 #address-cells = <1>;
631 #size-cells = <0>;
632 compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio";
635 clock-names = "gcc_mdio_ahb_clk";
640 compatible = "qcom,ipq6018-qusb2-phy";
642 #phy-cells = <0>;
646 clock-names = "cfg_ahb", "ref";
653 compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
655 #address-cells = <2>;
656 #size-cells = <2>;
661 clock-names = "core",
665 assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
667 assigned-clock-rates = <133330000>,
677 phy-names = "usb2-phy";
678 tx-fifo-resize;
679 snps,is-utmi-l1-suspend;
680 snps,hird-threshold = /bits/ 8 <0x0>;
688 compatible = "qcom,ipq6018-qmp-usb3-phy";
690 #address-cells = <2>;
691 #size-cells = <2>;
696 clock-names = "aux", "cfg_ahb", "ref";
700 reset-names = "phy","common";
708 #phy-cells = <0>;
709 #clock-cells = <0>;
711 clock-names = "pipe0";
712 clock-output-names = "gcc_usb0_pipe_clk_src";
717 compatible = "qcom,ipq6018-qusb2-phy";
719 #phy-cells = <0>;
723 clock-names = "cfg_ahb", "ref";
730 compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
732 #address-cells = <2>;
733 #size-cells = <2>;
740 clock-names = "cfg_noc",
745 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
748 assigned-clock-rates = <133330000>,
760 phy-names = "usb2-phy", "usb3-phy";
762 clock-names = "ref";
763 tx-fifo-resize;
764 snps,is-utmi-l1-suspend;
765 snps,hird-threshold = /bits/ 8 <0x0>;
773 wcss: wcss-smp2p {
777 interrupt-parent = <&intc>;
782 qcom,local-pid = <0>;
783 qcom,remote-pid = <1>;
785 wcss_smp2p_out: master-kernel {
786 qcom,entry-name = "master-kernel";
787 #qcom,smem-state-cells = <1>;
790 wcss_smp2p_in: slave-kernel {
791 qcom,entry-name = "slave-kernel";
792 interrupt-controller;
793 #interrupt-cells = <2>;
797 rpm-glink {
798 compatible = "qcom,glink-rpm";
800 qcom,rpm-msg-ram = <&rpm_msg_ram>;
803 rpm_requests: glink-channel {
804 compatible = "qcom,rpm-ipq6018";
805 qcom,glink-channels = "rpm_requests";
808 compatible = "qcom,rpm-mp5496-regulators";
811 regulator-min-microvolt = <725000>;
812 regulator-max-microvolt = <1062500>;
813 regulator-always-on;