Lines Matching +full:0 +full:x20100000
22 #clock-cells = <0>;
28 #clock-cells = <0>;
34 #size-cells = <0>;
36 CPU0: cpu@0 {
39 reg = <0x0>;
52 reg = <0x1>;
64 reg = <0x2>;
76 reg = <0x3>;
86 cache-level = <0x2>;
149 reg = <0x0 0x60000 0x0 0x6000>;
154 reg = <0x0 0x4a600000 0x0 0x00400000>;
159 reg = <0x0 0x4aa00000 0x0 0x00100000>;
164 reg = <0x0 0x4ab00000 0x0 0x05500000>;
172 hwlocks = <&tcsr_mutex 0>;
178 ranges = <0 0 0 0 0x0 0xffffffff>;
184 reg = <0x0 0xe3000 0x0 0x1000>;
191 reg = <0x0 0x00704000 0x0 0x20000>;
202 reg = <0x0 0x0073a000 0x0 0x6000>;
213 reg = <0x0 0x01000000 0x0 0x300000>;
217 gpio-ranges = <&tlmm 0 0 80>;
242 reg = <0x0 0x01800000 0x0 0x80000>;
251 reg = <0x0 0x01905000 0x0 0x1000>;
257 reg = <0x0 0x01937000 0x0 0x21000>;
262 reg = <0x0 0x07884000 0x0 0x2b000>;
267 qcom,ee = <0>;
272 reg = <0x0 0x078b1000 0x0 0x200>;
283 #size-cells = <0>;
284 reg = <0x0 0x078b5000 0x0 0x600>;
298 #size-cells = <0>;
299 reg = <0x0 0x078b6000 0x0 0x600>;
313 #size-cells = <0>;
314 reg = <0x0 0x078b6000 0x0 0x600>;
328 #size-cells = <0>;
329 reg = <0x0 0x078b7000 0x0 0x600>;
342 reg = <0x0 0x07984000 0x0 0x1a000>;
347 qcom,ee = <0>;
353 reg = <0x0 0x079b0000 0x0 0x10000>;
355 #size-cells = <0>;
360 dmas = <&qpic_bam 0>,
364 pinctrl-0 = <&qpic_pins>;
374 #interrupt-cells = <0x3>;
375 reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/
376 <0x0 0x0b002000 0x0 0x1000>, /*GICC*/
377 <0x0 0x0b001000 0x0 0x1000>, /*GICH*/
378 <0x0 0x0b004000 0x0 0x1000>; /*GICV*/
380 ranges = <0 0 0 0xb00a000 0 0xffd>;
382 v2m@0 {
385 reg = <0x0 0x0 0x0 0xffd>;
391 reg = <0x0 0x84000 0x0 0x1bc>; /* Serdes PLL */
407 reg = <0x0 0x84200 0x0 0x16c>, /* Serdes Tx */
408 <0x0 0x84400 0x0 0x200>, /* Serdes Rx */
409 <0x0 0x84800 0x0 0x4f4>; /* PCS: Lane0, COM, PCIE */
410 #phy-cells = <0>;
415 #clock-cells = <0>;
421 reg = <0x0 0x20000000 0x0 0xf1d>,
422 <0x0 0x20000f20 0x0 0xa8>,
423 <0x0 0x20001000 0x0 0x1000>,
424 <0x0 0x80000 0x0 0x4000>,
425 <0x0 0x20100000 0x0 0x1000>;
429 linux,pci-domain = <0>;
430 bus-range = <0x00 0xff>;
439 ranges = <0x81000000 0 0x20200000 0 0x20200000
440 0 0x10000>, /* downstream I/O */
441 <0x82000000 0 0x20220000 0 0x20220000
442 0 0xfde0000>; /* non-prefetchable memory */
448 interrupt-map-mask = <0 0 0 0x7>;
449 interrupt-map = <0 0 0 1 &intc 0 75
451 <0 0 0 2 &intc 0 78
453 <0 0 0 3 &intc 0 79
455 <0 0 0 4 &intc 0 83
492 reg = <0x0 0x0b017000 0x0 0x40>;
499 reg = <0x0 0x0b111000 0x0 0x1000>;
508 reg = <0x0 0x0b116000 0x0 0x40>;
509 #clock-cells = <0>;
525 ranges = <0 0 0 0x10000000>;
527 reg = <0x0 0x0b120000 0x0 0x1000>;
530 frame-number = <0>;
533 reg = <0x0b121000 0x1000>,
534 <0x0b122000 0x1000>;
540 reg = <0x0b123000 0x1000>;
547 reg = <0x0b124000 0x1000>;
554 reg = <0x0b125000 0x1000>;
561 reg = <0x0b126000 0x1000>;
568 reg = <0x0b127000 0x1000>;
575 reg = <0x0b128000 0x1000>;
582 reg = <0x0 0x0cd00000 0x0 0x4040>,
583 <0x0 0x004ab000 0x0 0x20>;
587 <&wcss_smp2p_in 0 0>,
588 <&wcss_smp2p_in 1 0>,
589 <&wcss_smp2p_in 2 0>,
590 <&wcss_smp2p_in 3 0>;
608 qcom,halt-regs = <&tcsr 0x18000 0x1b000 0xe000>;
610 qcom,smem-states = <&wcss_smp2p_out 0>,
631 #size-cells = <0>;
633 reg = <0x0 0x90000 0x0 0x64>;
641 reg = <0x0 0x059000 0x0 0x180>;
642 #phy-cells = <0>;
654 reg = <0x0 0x070F8800 0x0 0x400>;
674 reg = <0x0 0x7000000 0x0 0xcd00>;
680 snps,hird-threshold = /bits/ 8 <0x0>;
689 reg = <0x0 0x78000 0x0 0x1C4>;
704 reg = <0x0 0x00078200 0x0 0x130>, /* Tx */
705 <0x0 0x00078400 0x0 0x200>, /* Rx */
706 <0x0 0x00078800 0x0 0x1F8>, /* PCS */
707 <0x0 0x00078600 0x0 0x044>; /* PCS misc */
708 #phy-cells = <0>;
709 #clock-cells = <0>;
718 reg = <0x0 0x079000 0x0 0x180>;
719 #phy-cells = <0>;
731 reg = <0x0 0x8AF8800 0x0 0x400>;
757 reg = <0x0 0x8A00000 0x0 0xcd00>;
765 snps,hird-threshold = /bits/ 8 <0x0>;
782 qcom,local-pid = <0>;
801 mboxes = <&apcs_glb 0>;