Lines Matching +full:bpmp +full:- +full:bus +full:- +full:id
1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/mailbox/tegra186-hsp.h>
7 #include <dt-bindings/memory/tegra234-mc.h>
8 #include <dt-bindings/power/tegra234-powergate.h>
9 #include <dt-bindings/reset/tegra234-reset.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
17 bus@0 {
18 compatible = "simple-bus";
19 #address-cells = <1>;
20 #size-cells = <1>;
24 gpcdma: dma-controller@2600000 {
25 compatible = "nvidia,tegra234-gpcdma",
26 "nvidia,tegra186-gpcdma";
28 resets = <&bpmp TEGRA234_RESET_GPCDMA>;
29 reset-names = "gpcdma";
61 #dma-cells = <1>;
63 dma-coherent;
67 compatible = "nvidia,tegra234-aconnect",
68 "nvidia,tegra210-aconnect";
69 clocks = <&bpmp TEGRA234_CLK_APE>,
70 <&bpmp TEGRA234_CLK_APB2APE>;
71 clock-names = "ape", "apb2ape";
72 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>;
73 #address-cells = <1>;
74 #size-cells = <1>;
79 compatible = "nvidia,tegra234-ahub";
81 clocks = <&bpmp TEGRA234_CLK_AHUB>;
82 clock-names = "ahub";
83 assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>;
84 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
85 #address-cells = <1>;
86 #size-cells = <1>;
91 compatible = "nvidia,tegra234-i2s",
92 "nvidia,tegra210-i2s";
94 clocks = <&bpmp TEGRA234_CLK_I2S1>,
95 <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>;
96 clock-names = "i2s", "sync_input";
97 assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>;
98 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
99 assigned-clock-rates = <1536000>;
100 sound-name-prefix = "I2S1";
105 compatible = "nvidia,tegra234-i2s",
106 "nvidia,tegra210-i2s";
108 clocks = <&bpmp TEGRA234_CLK_I2S2>,
109 <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>;
110 clock-names = "i2s", "sync_input";
111 assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>;
112 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
113 assigned-clock-rates = <1536000>;
114 sound-name-prefix = "I2S2";
119 compatible = "nvidia,tegra234-i2s",
120 "nvidia,tegra210-i2s";
122 clocks = <&bpmp TEGRA234_CLK_I2S3>,
123 <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>;
124 clock-names = "i2s", "sync_input";
125 assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>;
126 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
127 assigned-clock-rates = <1536000>;
128 sound-name-prefix = "I2S3";
133 compatible = "nvidia,tegra234-i2s",
134 "nvidia,tegra210-i2s";
136 clocks = <&bpmp TEGRA234_CLK_I2S4>,
137 <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>;
138 clock-names = "i2s", "sync_input";
139 assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>;
140 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
141 assigned-clock-rates = <1536000>;
142 sound-name-prefix = "I2S4";
147 compatible = "nvidia,tegra234-i2s",
148 "nvidia,tegra210-i2s";
150 clocks = <&bpmp TEGRA234_CLK_I2S5>,
151 <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>;
152 clock-names = "i2s", "sync_input";
153 assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>;
154 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
155 assigned-clock-rates = <1536000>;
156 sound-name-prefix = "I2S5";
161 compatible = "nvidia,tegra234-i2s",
162 "nvidia,tegra210-i2s";
164 clocks = <&bpmp TEGRA234_CLK_I2S6>,
165 <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>;
166 clock-names = "i2s", "sync_input";
167 assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>;
168 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
169 assigned-clock-rates = <1536000>;
170 sound-name-prefix = "I2S6";
175 compatible = "nvidia,tegra234-sfc",
176 "nvidia,tegra210-sfc";
178 sound-name-prefix = "SFC1";
183 compatible = "nvidia,tegra234-sfc",
184 "nvidia,tegra210-sfc";
186 sound-name-prefix = "SFC2";
191 compatible = "nvidia,tegra234-sfc",
192 "nvidia,tegra210-sfc";
194 sound-name-prefix = "SFC3";
199 compatible = "nvidia,tegra234-sfc",
200 "nvidia,tegra210-sfc";
202 sound-name-prefix = "SFC4";
207 compatible = "nvidia,tegra234-amx",
208 "nvidia,tegra194-amx";
210 sound-name-prefix = "AMX1";
215 compatible = "nvidia,tegra234-amx",
216 "nvidia,tegra194-amx";
218 sound-name-prefix = "AMX2";
223 compatible = "nvidia,tegra234-amx",
224 "nvidia,tegra194-amx";
226 sound-name-prefix = "AMX3";
231 compatible = "nvidia,tegra234-amx",
232 "nvidia,tegra194-amx";
234 sound-name-prefix = "AMX4";
239 compatible = "nvidia,tegra234-adx",
240 "nvidia,tegra210-adx";
242 sound-name-prefix = "ADX1";
247 compatible = "nvidia,tegra234-adx",
248 "nvidia,tegra210-adx";
250 sound-name-prefix = "ADX2";
255 compatible = "nvidia,tegra234-adx",
256 "nvidia,tegra210-adx";
258 sound-name-prefix = "ADX3";
263 compatible = "nvidia,tegra234-adx",
264 "nvidia,tegra210-adx";
266 sound-name-prefix = "ADX4";
272 compatible = "nvidia,tegra234-dmic",
273 "nvidia,tegra210-dmic";
275 clocks = <&bpmp TEGRA234_CLK_DMIC1>;
276 clock-names = "dmic";
277 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>;
278 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
279 assigned-clock-rates = <3072000>;
280 sound-name-prefix = "DMIC1";
285 compatible = "nvidia,tegra234-dmic",
286 "nvidia,tegra210-dmic";
288 clocks = <&bpmp TEGRA234_CLK_DMIC2>;
289 clock-names = "dmic";
290 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>;
291 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
292 assigned-clock-rates = <3072000>;
293 sound-name-prefix = "DMIC2";
298 compatible = "nvidia,tegra234-dmic",
299 "nvidia,tegra210-dmic";
301 clocks = <&bpmp TEGRA234_CLK_DMIC3>;
302 clock-names = "dmic";
303 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>;
304 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
305 assigned-clock-rates = <3072000>;
306 sound-name-prefix = "DMIC3";
311 compatible = "nvidia,tegra234-dmic",
312 "nvidia,tegra210-dmic";
314 clocks = <&bpmp TEGRA234_CLK_DMIC4>;
315 clock-names = "dmic";
316 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>;
317 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
318 assigned-clock-rates = <3072000>;
319 sound-name-prefix = "DMIC4";
324 compatible = "nvidia,tegra234-dspk",
325 "nvidia,tegra186-dspk";
327 clocks = <&bpmp TEGRA234_CLK_DSPK1>;
328 clock-names = "dspk";
329 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>;
330 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
331 assigned-clock-rates = <12288000>;
332 sound-name-prefix = "DSPK1";
337 compatible = "nvidia,tegra234-dspk",
338 "nvidia,tegra186-dspk";
340 clocks = <&bpmp TEGRA234_CLK_DSPK2>;
341 clock-names = "dspk";
342 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>;
343 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
344 assigned-clock-rates = <12288000>;
345 sound-name-prefix = "DSPK2";
349 tegra_ope1: processing-engine@2908000 {
350 compatible = "nvidia,tegra234-ope",
351 "nvidia,tegra210-ope";
353 #address-cells = <1>;
354 #size-cells = <1>;
356 sound-name-prefix = "OPE1";
360 compatible = "nvidia,tegra234-peq",
361 "nvidia,tegra210-peq";
365 dynamic-range-compressor@2908200 {
366 compatible = "nvidia,tegra234-mbdrc",
367 "nvidia,tegra210-mbdrc";
373 compatible = "nvidia,tegra234-mvc",
374 "nvidia,tegra210-mvc";
376 sound-name-prefix = "MVC1";
381 compatible = "nvidia,tegra234-mvc",
382 "nvidia,tegra210-mvc";
384 sound-name-prefix = "MVC2";
389 compatible = "nvidia,tegra234-amixer",
390 "nvidia,tegra210-amixer";
392 sound-name-prefix = "MIXER1";
397 compatible = "nvidia,tegra234-admaif",
398 "nvidia,tegra186-admaif";
420 dma-names = "rx1", "tx1",
442 interconnect-names = "dma-mem", "write";
448 compatible = "nvidia,tegra234-asrc",
449 "nvidia,tegra186-asrc";
451 sound-name-prefix = "ASRC1";
456 adma: dma-controller@2930000 {
457 compatible = "nvidia,tegra234-adma",
458 "nvidia,tegra186-adma";
460 interrupt-parent = <&agic>;
493 #dma-cells = <1>;
494 clocks = <&bpmp TEGRA234_CLK_AHUB>;
495 clock-names = "d_audio";
499 agic: interrupt-controller@2a40000 {
500 compatible = "nvidia,tegra234-agic",
501 "nvidia,tegra210-agic";
502 #interrupt-cells = <3>;
503 interrupt-controller;
509 clocks = <&bpmp TEGRA234_CLK_APE>;
510 clock-names = "clk";
516 compatible = "nvidia,tegra234-misc";
523 compatible = "nvidia,tegra234-timer";
545 compatible = "nvidia,tegra234-host1x";
549 reg-names = "common", "hypervisor", "vm";
559 interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4",
561 clocks = <&bpmp TEGRA234_CLK_HOST1X>;
562 clock-names = "host1x";
564 #address-cells = <1>;
565 #size-cells = <1>;
569 interconnect-names = "dma-mem";
573 iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>,
591 compatible = "nvidia,tegra234-vic";
594 clocks = <&bpmp TEGRA234_CLK_VIC>;
595 clock-names = "vic";
596 resets = <&bpmp TEGRA234_RESET_VIC>;
597 reset-names = "vic";
599 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>;
602 interconnect-names = "dma-mem", "write";
604 dma-coherent;
609 compatible = "nvidia,tegra234-gpio";
610 reg-names = "security", "gpio";
661 #interrupt-cells = <2>;
662 interrupt-controller;
663 #gpio-cells = <2>;
664 gpio-controller;
667 mc: memory-controller@2c00000 {
668 compatible = "nvidia,tegra234-mc";
669 reg = <0x02c00000 0x10000>, /* MC-SID */
687 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3",
691 #interconnect-cells = <1>;
694 #address-cells = <2>;
695 #size-cells = <2>;
716 dma-ranges = <0x0 0x0 0x0 0x80 0x0>;
718 emc: external-memory-controller@2c60000 {
719 compatible = "nvidia,tegra234-emc";
723 clocks = <&bpmp TEGRA234_CLK_EMC>;
724 clock-names = "emc";
727 #interconnect-cells = <0>;
729 nvidia,bpmp = <&bpmp>;
734 compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart";
737 clocks = <&bpmp TEGRA234_CLK_UARTA>;
738 clock-names = "serial";
739 resets = <&bpmp TEGRA234_RESET_UARTA>;
740 reset-names = "serial";
745 compatible = "nvidia,tegra194-i2c";
749 clock-frequency = <400000>;
750 clocks = <&bpmp TEGRA234_CLK_I2C1
751 &bpmp TEGRA234_CLK_PLLP_OUT0>;
752 assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>;
753 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
754 clock-names = "div-clk", "parent";
755 resets = <&bpmp TEGRA234_RESET_I2C1>;
756 reset-names = "i2c";
758 dma-coherent;
760 dma-names = "rx", "tx";
764 compatible = "nvidia,tegra194-i2c";
768 clock-frequency = <400000>;
769 clocks = <&bpmp TEGRA234_CLK_I2C3
770 &bpmp TEGRA234_CLK_PLLP_OUT0>;
771 assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>;
772 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
773 clock-names = "div-clk", "parent";
774 resets = <&bpmp TEGRA234_RESET_I2C3>;
775 reset-names = "i2c";
777 dma-coherent;
779 dma-names = "rx", "tx";
783 compatible = "nvidia,tegra194-i2c";
787 clock-frequency = <100000>;
788 clocks = <&bpmp TEGRA234_CLK_I2C4
789 &bpmp TEGRA234_CLK_PLLP_OUT0>;
790 assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>;
791 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
792 clock-names = "div-clk", "parent";
793 resets = <&bpmp TEGRA234_RESET_I2C4>;
794 reset-names = "i2c";
796 dma-coherent;
798 dma-names = "rx", "tx";
802 compatible = "nvidia,tegra194-i2c";
806 clock-frequency = <100000>;
807 clocks = <&bpmp TEGRA234_CLK_I2C6
808 &bpmp TEGRA234_CLK_PLLP_OUT0>;
809 assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>;
810 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
811 clock-names = "div-clk", "parent";
812 resets = <&bpmp TEGRA234_RESET_I2C6>;
813 reset-names = "i2c";
815 dma-coherent;
817 dma-names = "rx", "tx";
821 compatible = "nvidia,tegra194-i2c";
825 clock-frequency = <100000>;
826 clocks = <&bpmp TEGRA234_CLK_I2C7
827 &bpmp TEGRA234_CLK_PLLP_OUT0>;
828 assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>;
829 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
830 clock-names = "div-clk", "parent";
831 resets = <&bpmp TEGRA234_RESET_I2C7>;
832 reset-names = "i2c";
834 dma-coherent;
836 dma-names = "rx", "tx";
840 compatible = "nvidia,tegra194-i2c";
844 clock-frequency = <100000>;
845 clocks = <&bpmp TEGRA234_CLK_I2C9
846 &bpmp TEGRA234_CLK_PLLP_OUT0>;
847 assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>;
848 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
849 clock-names = "div-clk", "parent";
850 resets = <&bpmp TEGRA234_RESET_I2C9>;
851 reset-names = "i2c";
853 dma-coherent;
855 dma-names = "rx", "tx";
859 compatible = "nvidia,tegra234-qspi";
862 #address-cells = <1>;
863 #size-cells = <0>;
864 clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>,
865 <&bpmp TEGRA234_CLK_QSPI0_PM>;
866 clock-names = "qspi", "qspi_out";
867 resets = <&bpmp TEGRA234_RESET_QSPI0>;
868 reset-names = "qspi";
873 compatible = "nvidia,tegra194-pwm",
874 "nvidia,tegra186-pwm";
876 clocks = <&bpmp TEGRA234_CLK_PWM1>;
877 clock-names = "pwm";
878 resets = <&bpmp TEGRA234_RESET_PWM1>;
879 reset-names = "pwm";
881 #pwm-cells = <2>;
885 compatible = "nvidia,tegra234-qspi";
888 #address-cells = <1>;
889 #size-cells = <0>;
890 clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>,
891 <&bpmp TEGRA234_CLK_QSPI1_PM>;
892 clock-names = "qspi", "qspi_out";
893 resets = <&bpmp TEGRA234_RESET_QSPI1>;
894 reset-names = "qspi";
899 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci";
902 clocks = <&bpmp TEGRA234_CLK_SDMMC4>,
903 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>;
904 clock-names = "sdhci", "tmclk";
905 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>,
906 <&bpmp TEGRA234_CLK_PLLC4>;
907 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>;
908 resets = <&bpmp TEGRA234_RESET_SDMMC4>;
909 reset-names = "sdhci";
912 interconnect-names = "dma-mem", "write";
914 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
915 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
916 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
917 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
918 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
919 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
920 nvidia,default-tap = <0x8>;
921 nvidia,default-trim = <0x14>;
922 nvidia,dqs-trim = <40>;
923 supports-cqe;
928 compatible = "nvidia,tegra234-hda", "nvidia,tegra30-hda";
931 clocks = <&bpmp TEGRA234_CLK_AZA_BIT>,
932 <&bpmp TEGRA234_CLK_AZA_2XBIT>;
933 clock-names = "hda", "hda2codec_2x";
934 resets = <&bpmp TEGRA234_RESET_HDA>,
935 <&bpmp TEGRA234_RESET_HDACODEC>;
936 reset-names = "hda", "hda2codec_2x";
937 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>;
940 interconnect-names = "dma-mem", "write";
946 compatible = "nvidia,tegra234-efuse";
948 clocks = <&bpmp TEGRA234_CLK_FUSE>;
949 clock-names = "fuse";
953 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
964 interrupt-names = "doorbell", "shared0", "shared1", "shared2",
967 #mbox-cells = <2>;
971 compatible = "nvidia,tegra234-mgbe";
975 reg-names = "hypervisor", "mac", "xpcs";
977 interrupt-names = "common";
978 clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>,
979 <&bpmp TEGRA234_CLK_MGBE0_MAC>,
980 <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>,
981 <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>,
982 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>,
983 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>,
984 <&bpmp TEGRA234_CLK_MGBE0_TX>,
985 <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>,
986 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>,
987 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>,
988 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>,
989 <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>;
990 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
991 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
992 "rx-pcs", "tx-pcs";
993 resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>,
994 <&bpmp TEGRA234_RESET_MGBE0_PCS>;
995 reset-names = "mac", "pcs";
998 interconnect-names = "dma-mem", "write";
1000 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>;
1005 compatible = "nvidia,tegra234-mgbe";
1009 reg-names = "hypervisor", "mac", "xpcs";
1011 interrupt-names = "common";
1012 clocks = <&bpmp TEGRA234_CLK_MGBE1_APP>,
1013 <&bpmp TEGRA234_CLK_MGBE1_MAC>,
1014 <&bpmp TEGRA234_CLK_MGBE1_MAC_DIVIDER>,
1015 <&bpmp TEGRA234_CLK_MGBE1_PTP_REF>,
1016 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT_M>,
1017 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT>,
1018 <&bpmp TEGRA234_CLK_MGBE1_TX>,
1019 <&bpmp TEGRA234_CLK_MGBE1_EEE_PCS>,
1020 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_INPUT>,
1021 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>,
1022 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS>,
1023 <&bpmp TEGRA234_CLK_MGBE1_TX_PCS>;
1024 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
1025 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
1026 "rx-pcs", "tx-pcs";
1027 resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>,
1028 <&bpmp TEGRA234_RESET_MGBE1_PCS>;
1029 reset-names = "mac", "pcs";
1032 interconnect-names = "dma-mem", "write";
1034 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>;
1039 compatible = "nvidia,tegra234-mgbe";
1043 reg-names = "hypervisor", "mac", "xpcs";
1045 interrupt-names = "common";
1046 clocks = <&bpmp TEGRA234_CLK_MGBE2_APP>,
1047 <&bpmp TEGRA234_CLK_MGBE2_MAC>,
1048 <&bpmp TEGRA234_CLK_MGBE2_MAC_DIVIDER>,
1049 <&bpmp TEGRA234_CLK_MGBE2_PTP_REF>,
1050 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT_M>,
1051 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT>,
1052 <&bpmp TEGRA234_CLK_MGBE2_TX>,
1053 <&bpmp TEGRA234_CLK_MGBE2_EEE_PCS>,
1054 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_INPUT>,
1055 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>,
1056 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS>,
1057 <&bpmp TEGRA234_CLK_MGBE2_TX_PCS>;
1058 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
1059 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
1060 "rx-pcs", "tx-pcs";
1061 resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>,
1062 <&bpmp TEGRA234_RESET_MGBE2_PCS>;
1063 reset-names = "mac", "pcs";
1066 interconnect-names = "dma-mem", "write";
1068 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>;
1073 compatible = "nvidia,tegra234-mgbe";
1077 reg-names = "hypervisor", "mac", "xpcs";
1079 interrupt-names = "common";
1080 clocks = <&bpmp TEGRA234_CLK_MGBE3_APP>,
1081 <&bpmp TEGRA234_CLK_MGBE3_MAC>,
1082 <&bpmp TEGRA234_CLK_MGBE3_MAC_DIVIDER>,
1083 <&bpmp TEGRA234_CLK_MGBE3_PTP_REF>,
1084 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT_M>,
1085 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT>,
1086 <&bpmp TEGRA234_CLK_MGBE3_TX>,
1087 <&bpmp TEGRA234_CLK_MGBE3_EEE_PCS>,
1088 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_INPUT>,
1089 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>,
1090 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS>,
1091 <&bpmp TEGRA234_CLK_MGBE3_TX_PCS>;
1092 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
1093 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
1094 "rx-pcs", "tx-pcs";
1095 resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>,
1096 <&bpmp TEGRA234_RESET_MGBE3_PCS>;
1097 reset-names = "mac", "pcs";
1100 interconnect-names = "dma-mem", "write";
1102 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>;
1107 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
1240 stream-match-mask = <0x7f80>;
1241 #global-interrupts = <2>;
1242 #iommu-cells = <1>;
1244 nvidia,memory-controller = <&mc>;
1248 sce-fabric@b600000 {
1249 compatible = "nvidia,tegra234-sce-fabric";
1255 rce-fabric@be00000 {
1256 compatible = "nvidia,tegra234-rce-fabric";
1263 compatible = "nvidia,tegra234-p2u";
1265 reg-names = "ctl";
1267 #phy-cells = <0>;
1271 compatible = "nvidia,tegra234-p2u";
1273 reg-names = "ctl";
1275 #phy-cells = <0>;
1279 compatible = "nvidia,tegra234-p2u";
1281 reg-names = "ctl";
1283 #phy-cells = <0>;
1287 compatible = "nvidia,tegra234-p2u";
1289 reg-names = "ctl";
1291 #phy-cells = <0>;
1295 compatible = "nvidia,tegra234-p2u";
1297 reg-names = "ctl";
1299 #phy-cells = <0>;
1303 compatible = "nvidia,tegra234-p2u";
1305 reg-names = "ctl";
1307 #phy-cells = <0>;
1311 compatible = "nvidia,tegra234-p2u";
1313 reg-names = "ctl";
1315 #phy-cells = <0>;
1319 compatible = "nvidia,tegra234-p2u";
1321 reg-names = "ctl";
1323 #phy-cells = <0>;
1327 compatible = "nvidia,tegra234-p2u";
1329 reg-names = "ctl";
1331 #phy-cells = <0>;
1335 compatible = "nvidia,tegra234-p2u";
1337 reg-names = "ctl";
1339 #phy-cells = <0>;
1343 compatible = "nvidia,tegra234-p2u";
1345 reg-names = "ctl";
1347 #phy-cells = <0>;
1351 compatible = "nvidia,tegra234-p2u";
1353 reg-names = "ctl";
1355 #phy-cells = <0>;
1359 compatible = "nvidia,tegra234-p2u";
1361 reg-names = "ctl";
1363 #phy-cells = <0>;
1367 compatible = "nvidia,tegra234-p2u";
1369 reg-names = "ctl";
1371 #phy-cells = <0>;
1375 compatible = "nvidia,tegra234-p2u";
1377 reg-names = "ctl";
1379 #phy-cells = <0>;
1383 compatible = "nvidia,tegra234-p2u";
1385 reg-names = "ctl";
1387 #phy-cells = <0>;
1391 compatible = "nvidia,tegra234-p2u";
1393 reg-names = "ctl";
1395 #phy-cells = <0>;
1399 compatible = "nvidia,tegra234-p2u";
1401 reg-names = "ctl";
1403 #phy-cells = <0>;
1407 compatible = "nvidia,tegra234-p2u";
1409 reg-names = "ctl";
1411 #phy-cells = <0>;
1415 compatible = "nvidia,tegra234-p2u";
1417 reg-names = "ctl";
1419 #phy-cells = <0>;
1423 compatible = "nvidia,tegra234-p2u";
1425 reg-names = "ctl";
1427 #phy-cells = <0>;
1431 compatible = "nvidia,tegra234-p2u";
1433 reg-names = "ctl";
1435 #phy-cells = <0>;
1439 compatible = "nvidia,tegra234-p2u";
1441 reg-names = "ctl";
1443 #phy-cells = <0>;
1447 compatible = "nvidia,tegra234-p2u";
1449 reg-names = "ctl";
1451 #phy-cells = <0>;
1455 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
1465 interrupt-names = "shared1", "shared2", "shared3", "shared4";
1466 #mbox-cells = <2>;
1470 compatible = "nvidia,tegra194-i2c";
1474 clock-frequency = <100000>;
1475 clocks = <&bpmp TEGRA234_CLK_I2C2
1476 &bpmp TEGRA234_CLK_PLLP_OUT0>;
1477 clock-names = "div-clk", "parent";
1478 assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>;
1479 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
1480 resets = <&bpmp TEGRA234_RESET_I2C2>;
1481 reset-names = "i2c";
1483 dma-coherent;
1485 dma-names = "rx", "tx";
1489 compatible = "nvidia,tegra194-i2c";
1491 nvidia,hw-instance-id = <0x7>;
1494 clock-frequency = <400000>;
1495 clocks = <&bpmp TEGRA234_CLK_I2C8
1496 &bpmp TEGRA234_CLK_PLLP_OUT0>;
1497 clock-names = "div-clk", "parent";
1498 assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>;
1499 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
1500 resets = <&bpmp TEGRA234_RESET_I2C8>;
1501 reset-names = "i2c";
1503 dma-coherent;
1505 dma-names = "rx", "tx";
1509 compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc";
1511 interrupt-parent = <&pmc>;
1513 clocks = <&bpmp TEGRA234_CLK_CLK_32K>;
1514 clock-names = "rtc";
1519 compatible = "nvidia,tegra234-gpio-aon";
1520 reg-names = "security", "gpio";
1527 #interrupt-cells = <2>;
1528 interrupt-controller;
1529 #gpio-cells = <2>;
1530 gpio-controller;
1534 compatible = "nvidia,tegra234-pmc";
1540 reg-names = "pmc", "wake", "aotag", "scratch", "misc";
1542 #interrupt-cells = <2>;
1543 interrupt-controller;
1546 aon-fabric@c600000 {
1547 compatible = "nvidia,tegra234-aon-fabric";
1553 bpmp-fabric@d600000 {
1554 compatible = "nvidia,tegra234-bpmp-fabric";
1560 dce-fabric@de00000 {
1561 compatible = "nvidia,tegra234-sce-fabric";
1567 gic: interrupt-controller@f400000 {
1568 compatible = "arm,gic-v3";
1571 interrupt-parent = <&gic>;
1574 #redistributor-regions = <1>;
1575 #interrupt-cells = <3>;
1576 interrupt-controller;
1580 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
1711 stream-match-mask = <0x7f80>;
1712 #global-interrupts = <1>;
1713 #iommu-cells = <1>;
1715 nvidia,memory-controller = <&mc>;
1720 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
1853 stream-match-mask = <0x7f80>;
1854 #global-interrupts = <2>;
1855 #iommu-cells = <1>;
1857 nvidia,memory-controller = <&mc>;
1861 cbb-fabric@13a00000 {
1862 compatible = "nvidia,tegra234-cbb-fabric";
1870 compatible = "nvidia,tegra234-ccplex-cluster";
1872 nvidia,bpmp = <&bpmp>;
1877 compatible = "nvidia,tegra234-pcie";
1878 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>;
1883 reg-names = "appl", "config", "atu_dma", "dbi";
1885 #address-cells = <3>;
1886 #size-cells = <2>;
1888 num-lanes = <4>;
1889 num-viewport = <8>;
1890 linux,pci-domain = <8>;
1892 clocks = <&bpmp TEGRA234_CLK_PEX2_C8_CORE>;
1893 clock-names = "core";
1895 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_8_APB>,
1896 <&bpmp TEGRA234_RESET_PEX2_CORE_8>;
1897 reset-names = "apb", "core";
1901 interrupt-names = "intr", "msi";
1903 #interrupt-cells = <1>;
1904 interrupt-map-mask = <0 0 0 0>;
1905 interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1907 nvidia,bpmp = <&bpmp 8>;
1909 nvidia,aspm-cmrt-us = <60>;
1910 nvidia,aspm-pwr-on-t-us = <20>;
1911 nvidia,aspm-l0s-entrance-latency-us = <3>;
1913 bus-range = <0x0 0xff>;
1916 …<0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
1921 interconnect-names = "dma-mem", "write";
1922 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>;
1923 iommu-map-mask = <0x0>;
1924 dma-coherent;
1930 compatible = "nvidia,tegra234-pcie";
1931 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>;
1936 reg-names = "appl", "config", "atu_dma", "dbi";
1938 #address-cells = <3>;
1939 #size-cells = <2>;
1941 num-lanes = <4>;
1942 num-viewport = <8>;
1943 linux,pci-domain = <9>;
1945 clocks = <&bpmp TEGRA234_CLK_PEX2_C9_CORE>;
1946 clock-names = "core";
1948 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_9_APB>,
1949 <&bpmp TEGRA234_RESET_PEX2_CORE_9>;
1950 reset-names = "apb", "core";
1954 interrupt-names = "intr", "msi";
1956 #interrupt-cells = <1>;
1957 interrupt-map-mask = <0 0 0 0>;
1958 interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1960 nvidia,bpmp = <&bpmp 9>;
1962 nvidia,aspm-cmrt-us = <60>;
1963 nvidia,aspm-pwr-on-t-us = <20>;
1964 nvidia,aspm-l0s-entrance-latency-us = <3>;
1966 bus-range = <0x0 0xff>;
1969 …<0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
1974 interconnect-names = "dma-mem", "write";
1975 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>;
1976 iommu-map-mask = <0x0>;
1977 dma-coherent;
1983 compatible = "nvidia,tegra234-pcie";
1984 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>;
1989 reg-names = "appl", "config", "atu_dma", "dbi";
1991 #address-cells = <3>;
1992 #size-cells = <2>;
1994 num-lanes = <4>;
1995 num-viewport = <8>;
1996 linux,pci-domain = <10>;
1998 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>;
1999 clock-names = "core";
2001 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>,
2002 <&bpmp TEGRA234_RESET_PEX2_CORE_10>;
2003 reset-names = "apb", "core";
2007 interrupt-names = "intr", "msi";
2009 #interrupt-cells = <1>;
2010 interrupt-map-mask = <0 0 0 0>;
2011 interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2013 nvidia,bpmp = <&bpmp 10>;
2015 nvidia,aspm-cmrt-us = <60>;
2016 nvidia,aspm-pwr-on-t-us = <20>;
2017 nvidia,aspm-l0s-entrance-latency-us = <3>;
2019 bus-range = <0x0 0xff>;
2022 …<0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2027 interconnect-names = "dma-mem", "write";
2028 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>;
2029 iommu-map-mask = <0x0>;
2030 dma-coherent;
2036 compatible = "nvidia,tegra234-pcie";
2037 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
2042 reg-names = "appl", "config", "atu_dma", "dbi";
2044 #address-cells = <3>;
2045 #size-cells = <2>;
2047 num-lanes = <1>;
2048 num-viewport = <8>;
2049 linux,pci-domain = <1>;
2051 clocks = <&bpmp TEGRA234_CLK_PEX0_C1_CORE>;
2052 clock-names = "core";
2054 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_1_APB>,
2055 <&bpmp TEGRA234_RESET_PEX0_CORE_1>;
2056 reset-names = "apb", "core";
2060 interrupt-names = "intr", "msi";
2062 #interrupt-cells = <1>;
2063 interrupt-map-mask = <0 0 0 0>;
2064 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
2066 nvidia,bpmp = <&bpmp 1>;
2068 nvidia,aspm-cmrt-us = <60>;
2069 nvidia,aspm-pwr-on-t-us = <20>;
2070 nvidia,aspm-l0s-entrance-latency-us = <3>;
2072 bus-range = <0x0 0xff>;
2075 …<0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2080 interconnect-names = "dma-mem", "write";
2081 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>;
2082 iommu-map-mask = <0x0>;
2083 dma-coherent;
2089 compatible = "nvidia,tegra234-pcie";
2090 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
2095 reg-names = "appl", "config", "atu_dma", "dbi";
2097 #address-cells = <3>;
2098 #size-cells = <2>;
2100 num-lanes = <1>;
2101 num-viewport = <8>;
2102 linux,pci-domain = <2>;
2104 clocks = <&bpmp TEGRA234_CLK_PEX0_C2_CORE>;
2105 clock-names = "core";
2107 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_2_APB>,
2108 <&bpmp TEGRA234_RESET_PEX0_CORE_2>;
2109 reset-names = "apb", "core";
2113 interrupt-names = "intr", "msi";
2115 #interrupt-cells = <1>;
2116 interrupt-map-mask = <0 0 0 0>;
2117 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
2119 nvidia,bpmp = <&bpmp 2>;
2121 nvidia,aspm-cmrt-us = <60>;
2122 nvidia,aspm-pwr-on-t-us = <20>;
2123 nvidia,aspm-l0s-entrance-latency-us = <3>;
2125 bus-range = <0x0 0xff>;
2128 …<0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2133 interconnect-names = "dma-mem", "write";
2134 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>;
2135 iommu-map-mask = <0x0>;
2136 dma-coherent;
2142 compatible = "nvidia,tegra234-pcie";
2143 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
2148 reg-names = "appl", "config", "atu_dma", "dbi";
2150 #address-cells = <3>;
2151 #size-cells = <2>;
2153 num-lanes = <1>;
2154 num-viewport = <8>;
2155 linux,pci-domain = <3>;
2157 clocks = <&bpmp TEGRA234_CLK_PEX0_C3_CORE>;
2158 clock-names = "core";
2160 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_3_APB>,
2161 <&bpmp TEGRA234_RESET_PEX0_CORE_3>;
2162 reset-names = "apb", "core";
2166 interrupt-names = "intr", "msi";
2168 #interrupt-cells = <1>;
2169 interrupt-map-mask = <0 0 0 0>;
2170 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
2172 nvidia,bpmp = <&bpmp 3>;
2174 nvidia,aspm-cmrt-us = <60>;
2175 nvidia,aspm-pwr-on-t-us = <20>;
2176 nvidia,aspm-l0s-entrance-latency-us = <3>;
2178 bus-range = <0x0 0xff>;
2181 …<0x02000000 0x0 0x40000000 0x21 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2186 interconnect-names = "dma-mem", "write";
2187 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>;
2188 iommu-map-mask = <0x0>;
2189 dma-coherent;
2195 compatible = "nvidia,tegra234-pcie";
2196 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>;
2201 reg-names = "appl", "config", "atu_dma", "dbi";
2203 #address-cells = <3>;
2204 #size-cells = <2>;
2206 num-lanes = <4>;
2207 num-viewport = <8>;
2208 linux,pci-domain = <4>;
2210 clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>;
2211 clock-names = "core";
2213 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>,
2214 <&bpmp TEGRA234_RESET_PEX0_CORE_4>;
2215 reset-names = "apb", "core";
2219 interrupt-names = "intr", "msi";
2221 #interrupt-cells = <1>;
2222 interrupt-map-mask = <0 0 0 0>;
2223 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
2225 nvidia,bpmp = <&bpmp 4>;
2227 nvidia,aspm-cmrt-us = <60>;
2228 nvidia,aspm-pwr-on-t-us = <20>;
2229 nvidia,aspm-l0s-entrance-latency-us = <3>;
2231 bus-range = <0x0 0xff>;
2234 …<0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2239 interconnect-names = "dma-mem", "write";
2240 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>;
2241 iommu-map-mask = <0x0>;
2242 dma-coherent;
2248 compatible = "nvidia,tegra234-pcie";
2249 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>;
2254 reg-names = "appl", "config", "atu_dma", "dbi";
2256 #address-cells = <3>;
2257 #size-cells = <2>;
2259 num-lanes = <4>;
2260 num-viewport = <8>;
2261 linux,pci-domain = <0>;
2263 clocks = <&bpmp TEGRA234_CLK_PEX0_C0_CORE>;
2264 clock-names = "core";
2266 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_0_APB>,
2267 <&bpmp TEGRA234_RESET_PEX0_CORE_0>;
2268 reset-names = "apb", "core";
2272 interrupt-names = "intr", "msi";
2274 #interrupt-cells = <1>;
2275 interrupt-map-mask = <0 0 0 0>;
2276 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
2278 nvidia,bpmp = <&bpmp 0>;
2280 nvidia,aspm-cmrt-us = <60>;
2281 nvidia,aspm-pwr-on-t-us = <20>;
2282 nvidia,aspm-l0s-entrance-latency-us = <3>;
2284 bus-range = <0x0 0xff>;
2287 …<0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2292 interconnect-names = "dma-mem", "write";
2293 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>;
2294 iommu-map-mask = <0x0>;
2295 dma-coherent;
2301 compatible = "nvidia,tegra234-pcie";
2302 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
2307 reg-names = "appl", "config", "atu_dma", "dbi";
2309 #address-cells = <3>;
2310 #size-cells = <2>;
2312 num-lanes = <8>;
2313 num-viewport = <8>;
2314 linux,pci-domain = <5>;
2316 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>;
2317 clock-names = "core";
2319 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>,
2320 <&bpmp TEGRA234_RESET_PEX1_CORE_5>;
2321 reset-names = "apb", "core";
2325 interrupt-names = "intr", "msi";
2327 #interrupt-cells = <1>;
2328 interrupt-map-mask = <0 0 0 0>;
2329 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2331 nvidia,bpmp = <&bpmp 5>;
2333 nvidia,aspm-cmrt-us = <60>;
2334 nvidia,aspm-pwr-on-t-us = <20>;
2335 nvidia,aspm-l0s-entrance-latency-us = <3>;
2337 bus-range = <0x0 0xff>;
2340 …<0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2345 interconnect-names = "dma-mem", "write";
2346 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>;
2347 iommu-map-mask = <0x0>;
2348 dma-coherent;
2354 compatible = "nvidia,tegra234-pcie";
2355 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>;
2360 reg-names = "appl", "config", "atu_dma", "dbi";
2362 #address-cells = <3>;
2363 #size-cells = <2>;
2365 num-lanes = <4>;
2366 num-viewport = <8>;
2367 linux,pci-domain = <6>;
2369 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>;
2370 clock-names = "core";
2372 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>,
2373 <&bpmp TEGRA234_RESET_PEX1_CORE_6>;
2374 reset-names = "apb", "core";
2378 interrupt-names = "intr", "msi";
2380 #interrupt-cells = <1>;
2381 interrupt-map-mask = <0 0 0 0>;
2382 interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
2384 nvidia,bpmp = <&bpmp 6>;
2386 nvidia,aspm-cmrt-us = <60>;
2387 nvidia,aspm-pwr-on-t-us = <20>;
2388 nvidia,aspm-l0s-entrance-latency-us = <3>;
2390 bus-range = <0x0 0xff>;
2393 …<0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2398 interconnect-names = "dma-mem", "write";
2399 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>;
2400 iommu-map-mask = <0x0>;
2401 dma-coherent;
2407 compatible = "nvidia,tegra234-pcie";
2408 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>;
2413 reg-names = "appl", "config", "atu_dma", "dbi";
2415 #address-cells = <3>;
2416 #size-cells = <2>;
2418 num-lanes = <8>;
2419 num-viewport = <8>;
2420 linux,pci-domain = <7>;
2422 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>;
2423 clock-names = "core";
2425 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>,
2426 <&bpmp TEGRA234_RESET_PEX2_CORE_7>;
2427 reset-names = "apb", "core";
2431 interrupt-names = "intr", "msi";
2433 #interrupt-cells = <1>;
2434 interrupt-map-mask = <0 0 0 0>;
2435 interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
2437 nvidia,bpmp = <&bpmp 7>;
2439 nvidia,aspm-cmrt-us = <60>;
2440 nvidia,aspm-pwr-on-t-us = <20>;
2441 nvidia,aspm-l0s-entrance-latency-us = <3>;
2443 bus-range = <0x0 0xff>;
2446 …<0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2451 interconnect-names = "dma-mem", "write";
2452 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>;
2453 iommu-map-mask = <0x0>;
2454 dma-coherent;
2459 pcie-ep@141a0000 {
2460 compatible = "nvidia,tegra234-pcie-ep";
2461 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
2466 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2468 num-lanes = <8>;
2470 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>;
2471 clock-names = "core";
2473 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>,
2474 <&bpmp TEGRA234_RESET_PEX1_CORE_5>;
2475 reset-names = "apb", "core";
2478 interrupt-names = "intr";
2480 nvidia,bpmp = <&bpmp 5>;
2482 nvidia,enable-ext-refclk;
2483 nvidia,aspm-cmrt-us = <60>;
2484 nvidia,aspm-pwr-on-t-us = <20>;
2485 nvidia,aspm-l0s-entrance-latency-us = <3>;
2489 interconnect-names = "dma-mem", "write";
2490 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>;
2491 iommu-map-mask = <0x0>;
2492 dma-coherent;
2497 pcie-ep@141c0000{
2498 compatible = "nvidia,tegra234-pcie-ep";
2499 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>;
2504 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2506 num-lanes = <4>;
2508 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>;
2509 clock-names = "core";
2511 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>,
2512 <&bpmp TEGRA234_RESET_PEX1_CORE_6>;
2513 reset-names = "apb", "core";
2516 interrupt-names = "intr";
2518 nvidia,bpmp = <&bpmp 6>;
2520 nvidia,enable-ext-refclk;
2521 nvidia,aspm-cmrt-us = <60>;
2522 nvidia,aspm-pwr-on-t-us = <20>;
2523 nvidia,aspm-l0s-entrance-latency-us = <3>;
2527 interconnect-names = "dma-mem", "write";
2528 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>;
2529 iommu-map-mask = <0x0>;
2530 dma-coherent;
2535 pcie-ep@141e0000{
2536 compatible = "nvidia,tegra234-pcie-ep";
2537 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>;
2542 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2544 num-lanes = <8>;
2546 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>;
2547 clock-names = "core";
2549 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>,
2550 <&bpmp TEGRA234_RESET_PEX2_CORE_7>;
2551 reset-names = "apb", "core";
2554 interrupt-names = "intr";
2556 nvidia,bpmp = <&bpmp 7>;
2558 nvidia,enable-ext-refclk;
2559 nvidia,aspm-cmrt-us = <60>;
2560 nvidia,aspm-pwr-on-t-us = <20>;
2561 nvidia,aspm-l0s-entrance-latency-us = <3>;
2565 interconnect-names = "dma-mem", "write";
2566 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>;
2567 iommu-map-mask = <0x0>;
2568 dma-coherent;
2573 pcie-ep@140e0000{
2574 compatible = "nvidia,tegra234-pcie-ep";
2575 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>;
2580 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2582 num-lanes = <4>;
2584 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>;
2585 clock-names = "core";
2587 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>,
2588 <&bpmp TEGRA234_RESET_PEX2_CORE_10>;
2589 reset-names = "apb", "core";
2592 interrupt-names = "intr";
2594 nvidia,bpmp = <&bpmp 10>;
2596 nvidia,enable-ext-refclk;
2597 nvidia,aspm-cmrt-us = <60>;
2598 nvidia,aspm-pwr-on-t-us = <20>;
2599 nvidia,aspm-l0s-entrance-latency-us = <3>;
2603 interconnect-names = "dma-mem", "write";
2604 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>;
2605 iommu-map-mask = <0x0>;
2606 dma-coherent;
2612 compatible = "nvidia,tegra234-sysram", "mmio-sram";
2614 #address-cells = <1>;
2615 #size-cells = <1>;
2617 no-memory-wc;
2621 label = "cpu-bpmp-tx";
2627 label = "cpu-bpmp-rx";
2632 bpmp: bpmp { label
2633 compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp";
2637 #clock-cells = <1>;
2638 #reset-cells = <1>;
2639 #power-domain-cells = <1>;
2644 interconnect-names = "read", "write", "dma-mem", "dma-write";
2648 compatible = "nvidia,tegra186-bpmp-i2c";
2649 nvidia,bpmp-bus-id = <5>;
2650 #address-cells = <1>;
2651 #size-cells = <0>;
2656 #address-cells = <1>;
2657 #size-cells = <0>;
2660 compatible = "arm,cortex-a78";
2664 enable-method = "psci";
2666 i-cache-size = <65536>;
2667 i-cache-line-size = <64>;
2668 i-cache-sets = <256>;
2669 d-cache-size = <65536>;
2670 d-cache-line-size = <64>;
2671 d-cache-sets = <256>;
2672 next-level-cache = <&l2c0_0>;
2676 compatible = "arm,cortex-a78";
2680 enable-method = "psci";
2682 i-cache-size = <65536>;
2683 i-cache-line-size = <64>;
2684 i-cache-sets = <256>;
2685 d-cache-size = <65536>;
2686 d-cache-line-size = <64>;
2687 d-cache-sets = <256>;
2688 next-level-cache = <&l2c0_1>;
2692 compatible = "arm,cortex-a78";
2696 enable-method = "psci";
2698 i-cache-size = <65536>;
2699 i-cache-line-size = <64>;
2700 i-cache-sets = <256>;
2701 d-cache-size = <65536>;
2702 d-cache-line-size = <64>;
2703 d-cache-sets = <256>;
2704 next-level-cache = <&l2c0_2>;
2708 compatible = "arm,cortex-a78";
2712 enable-method = "psci";
2714 i-cache-size = <65536>;
2715 i-cache-line-size = <64>;
2716 i-cache-sets = <256>;
2717 d-cache-size = <65536>;
2718 d-cache-line-size = <64>;
2719 d-cache-sets = <256>;
2720 next-level-cache = <&l2c0_3>;
2724 compatible = "arm,cortex-a78";
2728 enable-method = "psci";
2730 i-cache-size = <65536>;
2731 i-cache-line-size = <64>;
2732 i-cache-sets = <256>;
2733 d-cache-size = <65536>;
2734 d-cache-line-size = <64>;
2735 d-cache-sets = <256>;
2736 next-level-cache = <&l2c1_0>;
2740 compatible = "arm,cortex-a78";
2744 enable-method = "psci";
2746 i-cache-size = <65536>;
2747 i-cache-line-size = <64>;
2748 i-cache-sets = <256>;
2749 d-cache-size = <65536>;
2750 d-cache-line-size = <64>;
2751 d-cache-sets = <256>;
2752 next-level-cache = <&l2c1_1>;
2756 compatible = "arm,cortex-a78";
2760 enable-method = "psci";
2762 i-cache-size = <65536>;
2763 i-cache-line-size = <64>;
2764 i-cache-sets = <256>;
2765 d-cache-size = <65536>;
2766 d-cache-line-size = <64>;
2767 d-cache-sets = <256>;
2768 next-level-cache = <&l2c1_2>;
2772 compatible = "arm,cortex-a78";
2776 enable-method = "psci";
2778 i-cache-size = <65536>;
2779 i-cache-line-size = <64>;
2780 i-cache-sets = <256>;
2781 d-cache-size = <65536>;
2782 d-cache-line-size = <64>;
2783 d-cache-sets = <256>;
2784 next-level-cache = <&l2c1_3>;
2788 compatible = "arm,cortex-a78";
2792 enable-method = "psci";
2794 i-cache-size = <65536>;
2795 i-cache-line-size = <64>;
2796 i-cache-sets = <256>;
2797 d-cache-size = <65536>;
2798 d-cache-line-size = <64>;
2799 d-cache-sets = <256>;
2800 next-level-cache = <&l2c2_0>;
2804 compatible = "arm,cortex-a78";
2808 enable-method = "psci";
2810 i-cache-size = <65536>;
2811 i-cache-line-size = <64>;
2812 i-cache-sets = <256>;
2813 d-cache-size = <65536>;
2814 d-cache-line-size = <64>;
2815 d-cache-sets = <256>;
2816 next-level-cache = <&l2c2_1>;
2820 compatible = "arm,cortex-a78";
2824 enable-method = "psci";
2826 i-cache-size = <65536>;
2827 i-cache-line-size = <64>;
2828 i-cache-sets = <256>;
2829 d-cache-size = <65536>;
2830 d-cache-line-size = <64>;
2831 d-cache-sets = <256>;
2832 next-level-cache = <&l2c2_2>;
2836 compatible = "arm,cortex-a78";
2840 enable-method = "psci";
2842 i-cache-size = <65536>;
2843 i-cache-line-size = <64>;
2844 i-cache-sets = <256>;
2845 d-cache-size = <65536>;
2846 d-cache-line-size = <64>;
2847 d-cache-sets = <256>;
2848 next-level-cache = <&l2c2_3>;
2851 cpu-map {
2907 l2c0_0: l2-cache00 {
2908 cache-size = <262144>;
2909 cache-line-size = <64>;
2910 cache-sets = <512>;
2911 cache-unified;
2912 next-level-cache = <&l3c0>;
2915 l2c0_1: l2-cache01 {
2916 cache-size = <262144>;
2917 cache-line-size = <64>;
2918 cache-sets = <512>;
2919 cache-unified;
2920 next-level-cache = <&l3c0>;
2923 l2c0_2: l2-cache02 {
2924 cache-size = <262144>;
2925 cache-line-size = <64>;
2926 cache-sets = <512>;
2927 cache-unified;
2928 next-level-cache = <&l3c0>;
2931 l2c0_3: l2-cache03 {
2932 cache-size = <262144>;
2933 cache-line-size = <64>;
2934 cache-sets = <512>;
2935 cache-unified;
2936 next-level-cache = <&l3c0>;
2939 l2c1_0: l2-cache10 {
2940 cache-size = <262144>;
2941 cache-line-size = <64>;
2942 cache-sets = <512>;
2943 cache-unified;
2944 next-level-cache = <&l3c1>;
2947 l2c1_1: l2-cache11 {
2948 cache-size = <262144>;
2949 cache-line-size = <64>;
2950 cache-sets = <512>;
2951 cache-unified;
2952 next-level-cache = <&l3c1>;
2955 l2c1_2: l2-cache12 {
2956 cache-size = <262144>;
2957 cache-line-size = <64>;
2958 cache-sets = <512>;
2959 cache-unified;
2960 next-level-cache = <&l3c1>;
2963 l2c1_3: l2-cache13 {
2964 cache-size = <262144>;
2965 cache-line-size = <64>;
2966 cache-sets = <512>;
2967 cache-unified;
2968 next-level-cache = <&l3c1>;
2971 l2c2_0: l2-cache20 {
2972 cache-size = <262144>;
2973 cache-line-size = <64>;
2974 cache-sets = <512>;
2975 cache-unified;
2976 next-level-cache = <&l3c2>;
2979 l2c2_1: l2-cache21 {
2980 cache-size = <262144>;
2981 cache-line-size = <64>;
2982 cache-sets = <512>;
2983 cache-unified;
2984 next-level-cache = <&l3c2>;
2987 l2c2_2: l2-cache22 {
2988 cache-size = <262144>;
2989 cache-line-size = <64>;
2990 cache-sets = <512>;
2991 cache-unified;
2992 next-level-cache = <&l3c2>;
2995 l2c2_3: l2-cache23 {
2996 cache-size = <262144>;
2997 cache-line-size = <64>;
2998 cache-sets = <512>;
2999 cache-unified;
3000 next-level-cache = <&l3c2>;
3003 l3c0: l3-cache0 {
3004 cache-size = <2097152>;
3005 cache-line-size = <64>;
3006 cache-sets = <2048>;
3009 l3c1: l3-cache1 {
3010 cache-size = <2097152>;
3011 cache-line-size = <64>;
3012 cache-sets = <2048>;
3015 l3c2: l3-cache2 {
3016 cache-size = <2097152>;
3017 cache-line-size = <64>;
3018 cache-sets = <2048>;
3023 compatible = "arm,cortex-a78-pmu";
3029 compatible = "arm,psci-1.0";
3035 compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu";
3038 mbox-names = "rx", "tx";
3045 clocks = <&bpmp TEGRA234_CLK_PLLA>,
3046 <&bpmp TEGRA234_CLK_PLLA_OUT0>;
3047 clock-names = "pll_a", "plla_out0";
3048 assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>,
3049 <&bpmp TEGRA234_CLK_PLLA_OUT0>,
3050 <&bpmp TEGRA234_CLK_AUD_MCLK>;
3051 assigned-clock-parents = <0>,
3052 <&bpmp TEGRA234_CLK_PLLA>,
3053 <&bpmp TEGRA234_CLK_PLLA_OUT0>;
3057 compatible = "arm,armv8-timer";
3062 interrupt-parent = <&gic>;
3063 always-on;