Lines Matching +full:1 +full:ee0000
19 #address-cells = <1>;
20 #size-cells = <1>;
61 #dma-cells = <1>;
73 #address-cells = <1>;
74 #size-cells = <1>;
85 #address-cells = <1>;
86 #size-cells = <1>;
353 #address-cells = <1>;
354 #size-cells = <1>;
400 dmas = <&adma 1>, <&adma 1>,
462 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
493 #dma-cells = <1>;
526 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
564 #address-cells = <1>;
565 #size-cells = <1>;
573 iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>,
574 <1 &smmu_niso0 TEGRA234_SID_HOST1X_CTX1 1>,
575 <2 &smmu_niso0 TEGRA234_SID_HOST1X_CTX2 1>,
576 <3 &smmu_niso0 TEGRA234_SID_HOST1X_CTX3 1>,
577 <4 &smmu_niso0 TEGRA234_SID_HOST1X_CTX4 1>,
578 <5 &smmu_niso0 TEGRA234_SID_HOST1X_CTX5 1>,
579 <6 &smmu_niso0 TEGRA234_SID_HOST1X_CTX6 1>,
580 <7 &smmu_niso0 TEGRA234_SID_HOST1X_CTX7 1>,
581 <8 &smmu_niso1 TEGRA234_SID_HOST1X_CTX0 1>,
582 <9 &smmu_niso1 TEGRA234_SID_HOST1X_CTX1 1>,
583 <10 &smmu_niso1 TEGRA234_SID_HOST1X_CTX2 1>,
584 <11 &smmu_niso1 TEGRA234_SID_HOST1X_CTX3 1>,
585 <12 &smmu_niso1 TEGRA234_SID_HOST1X_CTX4 1>,
586 <13 &smmu_niso1 TEGRA234_SID_HOST1X_CTX5 1>,
587 <14 &smmu_niso1 TEGRA234_SID_HOST1X_CTX6 1>,
588 <15 &smmu_niso1 TEGRA234_SID_HOST1X_CTX7 1>;
691 #interconnect-cells = <1>;
862 #address-cells = <1>;
888 #address-cells = <1>;
916 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
917 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
1242 #iommu-cells = <1>;
1366 p2u_nvhs_5: phy@3ee0000 {
1574 #redistributor-regions = <1>;
1712 #global-interrupts = <1>;
1713 #iommu-cells = <1>;
1855 #iommu-cells = <1>;
1903 #interrupt-cells = <1>;
1917 <0x01000000 0x0 0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
1956 #interrupt-cells = <1>;
1970 <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2009 #interrupt-cells = <1>;
2023 <0x01000000 0x0 0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2047 num-lanes = <1>;
2049 linux,pci-domain = <1>;
2062 #interrupt-cells = <1>;
2066 nvidia,bpmp = <&bpmp 1>;
2076 <0x01000000 0x0 0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2100 num-lanes = <1>;
2115 #interrupt-cells = <1>;
2129 <0x01000000 0x0 0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2153 num-lanes = <1>;
2168 #interrupt-cells = <1>;
2182 <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2221 #interrupt-cells = <1>;
2235 <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2274 #interrupt-cells = <1>;
2288 <0x01000000 0x0 0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2327 #interrupt-cells = <1>;
2341 <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2380 #interrupt-cells = <1>;
2394 <0x01000000 0x0 0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2433 #interrupt-cells = <1>;
2447 <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2614 #address-cells = <1>;
2615 #size-cells = <1>;
2637 #clock-cells = <1>;
2638 #reset-cells = <1>;
2639 #power-domain-cells = <1>;
2650 #address-cells = <1>;
2656 #address-cells = <1>;
3037 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>;