Lines Matching +full:0 +full:x2e000000
17 bus@0 {
22 ranges = <0x0 0x0 0x0 0x40000000>;
27 reg = <0x2600000 0x210000>;
75 ranges = <0x02900000 0x02900000 0x200000>;
80 reg = <0x02900800 0x800>;
87 ranges = <0x02900800 0x02900800 0x11800>;
93 reg = <0x2901000 0x100>;
107 reg = <0x2901100 0x100>;
121 reg = <0x2901200 0x100>;
135 reg = <0x2901300 0x100>;
149 reg = <0x2901400 0x100>;
163 reg = <0x2901500 0x100>;
177 reg = <0x2902000 0x200>;
185 reg = <0x2902200 0x200>;
193 reg = <0x2902400 0x200>;
201 reg = <0x2902600 0x200>;
209 reg = <0x2903000 0x100>;
217 reg = <0x2903100 0x100>;
225 reg = <0x2903200 0x100>;
233 reg = <0x2903300 0x100>;
241 reg = <0x2903800 0x100>;
249 reg = <0x2903900 0x100>;
257 reg = <0x2903a00 0x100>;
265 reg = <0x2903b00 0x100>;
274 reg = <0x2904000 0x100>;
287 reg = <0x2904100 0x100>;
300 reg = <0x2904200 0x100>;
313 reg = <0x2904300 0x100>;
326 reg = <0x2905000 0x100>;
339 reg = <0x2905100 0x100>;
352 reg = <0x2908000 0x100>;
362 reg = <0x2908100 0x100>;
368 reg = <0x2908200 0x200>;
375 reg = <0x290a000 0x200>;
383 reg = <0x290a200 0x200>;
391 reg = <0x290bb00 0x800>;
399 reg = <0x0290f000 0x1000>;
450 reg = <0x2910000 0x2000>;
459 reg = <0x02930000 0x20000>;
461 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
504 reg = <0x02a41000 0x1000>,
505 <0x02a42000 0x2000>;
517 reg = <0x00100000 0xf000>,
518 <0x0010f000 0x1000>;
524 reg = <0x02080000 0x00121000>;
525 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
546 reg = <0x13e00000 0x10000>,
547 <0x13e10000 0x10000>,
548 <0x13e40000 0x10000>;
567 ranges = <0x15000000 0x15000000 0x01000000>;
573 iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>,
592 reg = <0x15340000 0x00040000>;
611 reg = <0x02200000 0x10000>,
612 <0x02210000 0x10000>;
669 reg = <0x02c00000 0x10000>, /* MC-SID */
670 <0x02c10000 0x10000>, /* MC Broadcast*/
671 <0x02c20000 0x10000>, /* MC0 */
672 <0x02c30000 0x10000>, /* MC1 */
673 <0x02c40000 0x10000>, /* MC2 */
674 <0x02c50000 0x10000>, /* MC3 */
675 <0x02b80000 0x10000>, /* MC4 */
676 <0x02b90000 0x10000>, /* MC5 */
677 <0x02ba0000 0x10000>, /* MC6 */
678 <0x02bb0000 0x10000>, /* MC7 */
679 <0x01700000 0x10000>, /* MC8 */
680 <0x01710000 0x10000>, /* MC9 */
681 <0x01720000 0x10000>, /* MC10 */
682 <0x01730000 0x10000>, /* MC11 */
683 <0x01740000 0x10000>, /* MC12 */
684 <0x01750000 0x10000>, /* MC13 */
685 <0x01760000 0x10000>, /* MC14 */
686 <0x01770000 0x10000>; /* MC15 */
697 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>,
698 <0x02b80000 0x0 0x02b80000 0x0 0x040000>,
699 <0x02c00000 0x0 0x02c00000 0x0 0x100000>;
714 * Limit the DMA range for memory clients to [38:0].
716 dma-ranges = <0x0 0x0 0x0 0x80 0x0>;
720 reg = <0x0 0x02c60000 0x0 0x90000>,
721 <0x0 0x01780000 0x0 0x80000>;
727 #interconnect-cells = <0>;
735 reg = <0x03100000 0x10000>;
746 reg = <0x3160000 0x100>;
765 reg = <0x3180000 0x100>;
784 reg = <0x3190000 0x100>;
803 reg = <0x31b0000 0x100>;
822 reg = <0x31c0000 0x100>;
841 reg = <0x31e0000 0x100>;
860 reg = <0x3270000 0x1000>;
863 #size-cells = <0>;
875 reg = <0x3280000 0x10000>;
886 reg = <0x3300000 0x1000>;
889 #size-cells = <0>;
900 reg = <0x03460000 0x20000>;
914 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
915 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
916 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
917 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
918 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
919 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
920 nvidia,default-tap = <0x8>;
921 nvidia,default-trim = <0x14>;
929 reg = <0x3510000 0x10000>;
947 reg = <0x03810000 0x10000>;
954 reg = <0x03c00000 0xa0000>;
972 reg = <0x06800000 0x10000>,
973 <0x06810000 0x10000>,
974 <0x068a0000 0x10000>;
1006 reg = <0x06900000 0x10000>,
1007 <0x06910000 0x10000>,
1008 <0x069a0000 0x10000>;
1040 reg = <0x06a00000 0x10000>,
1041 <0x06a10000 0x10000>,
1042 <0x06aa0000 0x10000>;
1074 reg = <0x06b00000 0x10000>,
1075 <0x06b10000 0x10000>,
1076 <0x06ba0000 0x10000>;
1108 reg = <0x8000000 0x1000000>,
1109 <0x7000000 0x1000000>;
1240 stream-match-mask = <0x7f80>;
1250 reg = <0xb600000 0x40000>;
1257 reg = <0xbe00000 0x40000>;
1264 reg = <0x03e00000 0x10000>;
1267 #phy-cells = <0>;
1272 reg = <0x03e10000 0x10000>;
1275 #phy-cells = <0>;
1280 reg = <0x03e20000 0x10000>;
1283 #phy-cells = <0>;
1288 reg = <0x03e30000 0x10000>;
1291 #phy-cells = <0>;
1296 reg = <0x03e40000 0x10000>;
1299 #phy-cells = <0>;
1304 reg = <0x03e50000 0x10000>;
1307 #phy-cells = <0>;
1312 reg = <0x03e60000 0x10000>;
1315 #phy-cells = <0>;
1320 reg = <0x03e70000 0x10000>;
1323 #phy-cells = <0>;
1328 reg = <0x03e90000 0x10000>;
1331 #phy-cells = <0>;
1336 reg = <0x03ea0000 0x10000>;
1339 #phy-cells = <0>;
1344 reg = <0x03eb0000 0x10000>;
1347 #phy-cells = <0>;
1352 reg = <0x03ec0000 0x10000>;
1355 #phy-cells = <0>;
1360 reg = <0x03ed0000 0x10000>;
1363 #phy-cells = <0>;
1368 reg = <0x03ee0000 0x10000>;
1371 #phy-cells = <0>;
1376 reg = <0x03ef0000 0x10000>;
1379 #phy-cells = <0>;
1384 reg = <0x03f00000 0x10000>;
1387 #phy-cells = <0>;
1392 reg = <0x03f20000 0x10000>;
1395 #phy-cells = <0>;
1400 reg = <0x03f30000 0x10000>;
1403 #phy-cells = <0>;
1408 reg = <0x03f40000 0x10000>;
1411 #phy-cells = <0>;
1416 reg = <0x03f50000 0x10000>;
1419 #phy-cells = <0>;
1424 reg = <0x03f60000 0x10000>;
1427 #phy-cells = <0>;
1432 reg = <0x03f70000 0x10000>;
1435 #phy-cells = <0>;
1440 reg = <0x03f80000 0x10000>;
1443 #phy-cells = <0>;
1448 reg = <0x03f90000 0x10000>;
1451 #phy-cells = <0>;
1456 reg = <0x0c150000 0x90000>;
1462 * Shared interrupt 0 is routed only to AON/SPE, so
1471 reg = <0xc240000 0x100>;
1490 reg = <0xc250000 0x100>;
1491 nvidia,hw-instance-id = <0x7>;
1504 dmas = <&gpcdma 0>, <&gpcdma 0>;
1510 reg = <0x0c2a0000 0x10000>;
1521 reg = <0x0c2f0000 0x1000>,
1522 <0x0c2f1000 0x1000>;
1535 reg = <0x0c360000 0x10000>,
1536 <0x0c370000 0x10000>,
1537 <0x0c380000 0x10000>,
1538 <0x0c390000 0x10000>,
1539 <0x0c3a0000 0x10000>;
1548 reg = <0xc600000 0x40000>;
1555 reg = <0xd600000 0x40000>;
1562 reg = <0xde00000 0x40000>;
1569 reg = <0x0f400000 0x010000>, /* GICD */
1570 <0x0f440000 0x200000>; /* GICR */
1581 reg = <0x10000000 0x1000000>;
1711 stream-match-mask = <0x7f80>;
1721 reg = <0x12000000 0x1000000>,
1722 <0x11000000 0x1000000>;
1853 stream-match-mask = <0x7f80>;
1863 reg = <0x13a00000 0x400000>;
1871 reg = <0x0 0x0e000000 0x0 0x5ffff>;
1879 reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */
1880 <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */
1881 <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
1882 <0x00 0x2a080000 0x0 0x00040000>; /* DBI reg space (256K) */
1904 interrupt-map-mask = <0 0 0 0>;
1905 interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1913 bus-range = <0x0 0xff>;
1915 …ranges = <0x43000000 0x32 0x40000000 0x32 0x40000000 0x2 0xe8000000>, /* prefetchable memory (1190…
1916 …<0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
1917 <0x01000000 0x0 0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
1922 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>;
1923 iommu-map-mask = <0x0>;
1932 reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */
1933 <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */
1934 <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
1935 <0x00 0x2c080000 0x0 0x00040000>; /* DBI reg space (256K) */
1957 interrupt-map-mask = <0 0 0 0>;
1958 interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1966 bus-range = <0x0 0xff>;
1968 …ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xe8000000>, /* prefetchable memory (1190…
1969 …<0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
1970 <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
1975 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>;
1976 iommu-map-mask = <0x0>;
1985 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */
1986 <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */
1987 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
1988 <0x00 0x2e080000 0x0 0x00040000>; /* DBI reg space (256K) */
2010 interrupt-map-mask = <0 0 0 0>;
2011 interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2019 bus-range = <0x0 0xff>;
2021 …ranges = <0x43000000 0x38 0x40000000 0x38 0x40000000 0x2 0xe8000000>, /* prefetchable memory (1190…
2022 …<0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2023 <0x01000000 0x0 0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2028 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>;
2029 iommu-map-mask = <0x0>;
2038 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */
2039 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */
2040 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2041 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */
2063 interrupt-map-mask = <0 0 0 0>;
2064 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
2072 bus-range = <0x0 0xff>;
2074 …ranges = <0x43000000 0x20 0x80000000 0x20 0x80000000 0x0 0x28000000>, /* prefetchable memory (640 …
2075 …<0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2076 <0x01000000 0x0 0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2081 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>;
2082 iommu-map-mask = <0x0>;
2091 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */
2092 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */
2093 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2094 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */
2116 interrupt-map-mask = <0 0 0 0>;
2117 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
2125 bus-range = <0x0 0xff>;
2127 …ranges = <0x43000000 0x20 0xc0000000 0x20 0xc0000000 0x0 0x28000000>, /* prefetchable memory (640 …
2128 …<0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2129 <0x01000000 0x0 0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2134 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>;
2135 iommu-map-mask = <0x0>;
2144 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */
2145 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */
2146 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2147 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */
2169 interrupt-map-mask = <0 0 0 0>;
2170 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
2178 bus-range = <0x0 0xff>;
2180 …ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 …
2181 …<0x02000000 0x0 0x40000000 0x21 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2182 <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2187 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>;
2188 iommu-map-mask = <0x0>;
2197 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
2198 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
2199 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2200 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */
2222 interrupt-map-mask = <0 0 0 0>;
2223 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
2231 bus-range = <0x0 0xff>;
2233 …ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable memory (1190…
2234 …<0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2235 <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2240 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>;
2241 iommu-map-mask = <0x0>;
2250 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
2251 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
2252 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2253 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
2261 linux,pci-domain = <0>;
2275 interrupt-map-mask = <0 0 0 0>;
2276 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
2278 nvidia,bpmp = <&bpmp 0>;
2284 bus-range = <0x0 0xff>;
2286 …ranges = <0x43000000 0x24 0x40000000 0x24 0x40000000 0x2 0xe8000000>, /* prefetchable memory (1190…
2287 …<0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2288 <0x01000000 0x0 0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2293 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>;
2294 iommu-map-mask = <0x0>;
2303 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
2304 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */
2305 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2306 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */
2328 interrupt-map-mask = <0 0 0 0>;
2329 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2337 bus-range = <0x0 0xff>;
2339 …ranges = <0x43000000 0x27 0x40000000 0x27 0x40000000 0x3 0xe8000000>, /* prefetchable memory (1600…
2340 …<0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2341 <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2346 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>;
2347 iommu-map-mask = <0x0>;
2356 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */
2357 <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */
2358 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2359 <0x00 0x3c080000 0x0 0x00040000>; /* DBI reg space (256K) */
2381 interrupt-map-mask = <0 0 0 0>;
2382 interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
2390 bus-range = <0x0 0xff>;
2392 …ranges = <0x43000000 0x2b 0x40000000 0x2b 0x40000000 0x2 0xe8000000>, /* prefetchable memory (1190…
2393 …<0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2394 <0x01000000 0x0 0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2399 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>;
2400 iommu-map-mask = <0x0>;
2409 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */
2410 <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */
2411 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2412 <0x00 0x3e080000 0x0 0x00040000>; /* DBI reg space (256K) */
2434 interrupt-map-mask = <0 0 0 0>;
2435 interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
2443 bus-range = <0x0 0xff>;
2445 …ranges = <0x43000000 0x2e 0x40000000 0x2e 0x40000000 0x3 0xe8000000>, /* prefetchable memory (1600…
2446 …<0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2447 <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2452 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>;
2453 iommu-map-mask = <0x0>;
2462 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
2463 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2464 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
2465 <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */
2490 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>;
2491 iommu-map-mask = <0x0>;
2500 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */
2501 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2502 <0x00 0x3c080000 0x0 0x00040000>, /* DBI space (256K) */
2503 <0x2b 0x40000000 0x3 0x00000000>; /* Address Space (12G) */
2528 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>;
2529 iommu-map-mask = <0x0>;
2538 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */
2539 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2540 <0x00 0x3e080000 0x0 0x00040000>, /* DBI space (256K) */
2541 <0x2e 0x40000000 0x4 0x00000000>; /* Address Space (16G) */
2566 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>;
2567 iommu-map-mask = <0x0>;
2576 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */
2577 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2578 <0x00 0x2e080000 0x0 0x00040000>, /* DBI space (256K) */
2579 <0x38 0x40000000 0x3 0x00000000>; /* Address Space (12G) */
2604 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>;
2605 iommu-map-mask = <0x0>;
2613 reg = <0x0 0x40000000 0x0 0x80000>;
2616 ranges = <0x0 0x0 0x40000000 0x80000>;
2620 reg = <0x70000 0x1000>;
2626 reg = <0x71000 0x1000>;
2651 #size-cells = <0>;
2657 #size-cells = <0>;
2659 cpu0_0: cpu@0 {
2662 reg = <0x00000>;
2678 reg = <0x00100>;
2694 reg = <0x00200>;
2710 reg = <0x00300>;
2726 reg = <0x10000>;
2742 reg = <0x10100>;
2758 reg = <0x10200>;
2774 reg = <0x10300>;
2790 reg = <0x20000>;
2806 reg = <0x20100>;
2822 reg = <0x20200>;
2838 reg = <0x20300>;
3036 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,
3051 assigned-clock-parents = <0>,