Lines Matching +full:0 +full:x54040000
21 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
22 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
23 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
30 interrupt-map-mask = <0 0 0 0>;
31 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
33 bus-range = <0x00 0xff>;
37 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
38 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
39 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
40 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
41 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
54 pinctrl-0 = <&pex_dpd_disable>;
59 pci@1,0 {
61 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
62 reg = <0x000800 0 0 0 0>;
63 bus-range = <0x00 0xff>;
73 pci@2,0 {
75 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
76 reg = <0x001000 0 0 0 0>;
77 bus-range = <0x00 0xff>;
90 reg = <0x0 0x50000000 0x0 0x00034000>;
102 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>;
108 reg = <0x0 0x54040000 0x0 0x00040000>;
135 #size-cells = <0>;
141 reg = <0x0 0x54080000 0x0 0x700>;
153 ranges = <0x0 0x0 0x54080000 0x2000>;
157 reg = <0x838 0x1300>;
183 reg = <0x0 0x54100000 0x0 0x00040000>;
194 reg = <0x0 0x54200000 0x0 0x00040000>;
204 nvidia,head = <0>;
209 reg = <0x0 0x54240000 0x0 0x00040000>;
224 reg = <0x0 0x54300000 0x0 0x00040000>;
232 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */
237 #size-cells = <0>;
242 reg = <0x0 0x54340000 0x0 0x00040000>;
255 reg = <0x0 0x54380000 0x0 0x00040000>;
261 reg = <0x0 0x54400000 0x0 0x00040000>;
269 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */
274 #size-cells = <0>;
279 reg = <0x0 0x54480000 0x0 0x00040000>;
285 reg = <0x0 0x544c0000 0x0 0x00040000>;
291 reg = <0x0 0x54500000 0x0 0x00040000>;
302 reg = <0x0 0x54540000 0x0 0x00040000>;
312 pinctrl-0 = <&state_dpaux_aux>;
322 reg = <0x0 0x54580000 0x0 0x00040000>;
332 pinctrl-0 = <&state_dpaux1_aux>;
342 reg = <0x0 0x545c0000 0x0 0x00040000>;
369 #size-cells = <0>;
375 reg = <0x0 0x54600000 0x0 0x00040000>;
385 reg = <0x0 0x54680000 0x0 0x00040000>;
395 reg = <0x0 0x546c0000 0x0 0x00040000>;
406 #size-cells = <0>;
414 reg = <0x0 0x50041000 0x0 0x1000>,
415 <0x0 0x50042000 0x0 0x2000>,
416 <0x0 0x50044000 0x0 0x2000>,
417 <0x0 0x50046000 0x0 0x2000>;
425 reg = <0x0 0x57000000 0x0 0x01000000>,
426 <0x0 0x58000000 0x0 0x01000000>;
444 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */
445 <0x0 0x60004100 0x0 0x40>, /* secondary controller */
446 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */
447 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */
448 <0x0 0x60004400 0x0 0x40>, /* quinary controller */
449 <0x0 0x60004500 0x0 0x40>; /* senary controller */
457 reg = <0x0 0x60005000 0x0 0x400>;
459 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
478 reg = <0x0 0x60006000 0x0 0x1000>;
485 reg = <0x0 0x60007000 0x0 0x1000>;
490 reg = <0x0 0x6000d000 0x0 0x1000>;
507 reg = <0x0 0x60020000 0x0 0x1400>;
549 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
550 <0x0 0x70000008 0x0 0x04>; /* Strapping options */
555 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */
556 <0x0 0x70003000 0x0 0x294>; /* Mux registers */
560 nvidia,pull-down-strength = <0x8>;
561 nvidia,pull-up-strength = <0x8>;
567 nvidia,pull-down-strength = <0x4>;
568 nvidia,pull-up-strength = <0x3>;
574 nvidia,pull-down-strength = <0x10>;
575 nvidia,pull-up-strength = <0x10>;
581 nvidia,pull-down-strength = <0x8>;
582 nvidia,pull-up-strength = <0x8>;
588 nvidia,pull-down-strength = <0x4>;
589 nvidia,pull-up-strength = <0x3>;
595 nvidia,pull-down-strength = <0x10>;
596 nvidia,pull-up-strength = <0x10>;
611 reg = <0x0 0x70006000 0x0 0x40>;
625 reg = <0x0 0x70006040 0x0 0x40>;
639 reg = <0x0 0x70006200 0x0 0x40>;
653 reg = <0x0 0x70006300 0x0 0x40>;
667 reg = <0x0 0x7000a000 0x0 0x100>;
678 reg = <0x0 0x7000c000 0x0 0x100>;
681 #size-cells = <0>;
693 reg = <0x0 0x7000c400 0x0 0x100>;
696 #size-cells = <0>;
708 reg = <0x0 0x7000c500 0x0 0x100>;
711 #size-cells = <0>;
723 reg = <0x0 0x7000c700 0x0 0x100>;
726 #size-cells = <0>;
733 pinctrl-0 = <&state_dpaux1_i2c>;
741 reg = <0x0 0x7000d000 0x0 0x100>;
744 #size-cells = <0>;
756 reg = <0x0 0x7000d100 0x0 0x100>;
759 #size-cells = <0>;
766 pinctrl-0 = <&state_dpaux_i2c>;
774 reg = <0x0 0x7000d400 0x0 0x200>;
777 #size-cells = <0>;
789 reg = <0x0 0x7000d600 0x0 0x200>;
792 #size-cells = <0>;
804 reg = <0x0 0x7000d800 0x0 0x200>;
807 #size-cells = <0>;
819 reg = <0x0 0x7000da00 0x0 0x200>;
822 #size-cells = <0>;
834 reg = <0x0 0x7000e000 0x0 0x100>;
843 reg = <0x0 0x7000e400 0x0 0x400>;
855 #power-domain-cells = <0>;
876 #power-domain-cells = <0>;
882 #power-domain-cells = <0>;
888 #power-domain-cells = <0>;
894 #power-domain-cells = <0>;
902 #power-domain-cells = <0>;
911 #power-domain-cells = <0>;
952 reg = <0x0 0x7000f800 0x0 0x400>;
961 reg = <0x0 0x70019000 0x0 0x1000>;
973 reg = <0x0 0x7001b000 0x0 0x1000>,
974 <0x0 0x7001e000 0x0 0x1000>,
975 <0x0 0x7001f000 0x0 0x1000>;
985 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
986 <0x0 0x70020000 0x0 0x7000>, /* SATA */
987 <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */
1001 reg = <0x0 0x70030000 0x0 0x10000>;
1017 reg = <0x0 0x70090000 0x0 0x8000>,
1018 <0x0 0x70098000 0x0 0x1000>,
1019 <0x0 0x70099000 0x0 0x1000>;
1054 reg = <0x0 0x7009f000 0x0 0x1000>;
1069 usb2-0 {
1071 #phy-cells = <0>;
1076 #phy-cells = <0>;
1081 #phy-cells = <0>;
1086 #phy-cells = <0>;
1097 hsic-0 {
1099 #phy-cells = <0>;
1104 #phy-cells = <0>;
1117 pcie-0 {
1119 #phy-cells = <0>;
1124 #phy-cells = <0>;
1129 #phy-cells = <0>;
1134 #phy-cells = <0>;
1139 #phy-cells = <0>;
1144 #phy-cells = <0>;
1149 #phy-cells = <0>;
1162 sata-0 {
1164 #phy-cells = <0>;
1171 usb2-0 {
1187 hsic-0 {
1191 usb3-0 {
1211 reg = <0x0 0x700b0000 0x0 0x200>;
1220 pinctrl-0 = <&sdmmc1_3v3>;
1224 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
1225 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
1226 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
1227 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
1228 nvidia,default-tap = <0x2>;
1229 nvidia,default-trim = <0x4>;
1240 reg = <0x0 0x700b0200 0x0 0x200>;
1248 pinctrl-0 = <&sdmmc2_1v8_drv>;
1249 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
1250 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
1251 nvidia,default-tap = <0x8>;
1252 nvidia,default-trim = <0x0>;
1258 reg = <0x0 0x700b0400 0x0 0x200>;
1267 pinctrl-0 = <&sdmmc3_3v3>;
1271 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
1272 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
1273 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
1274 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
1275 nvidia,default-tap = <0x3>;
1276 nvidia,default-trim = <0x3>;
1282 reg = <0x0 0x700b0600 0x0 0x200>;
1290 pinctrl-0 = <&sdmmc4_1v8_drv>;
1292 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
1293 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
1294 nvidia,default-tap = <0x8>;
1295 nvidia,default-trim = <0x0>;
1306 reg = <0x0 0x700d0000 0x0 0x8000>,
1307 <0x0 0x700d8000 0x0 0x1000>,
1308 <0x0 0x700d9000 0x0 0x1000>;
1325 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */
1326 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
1351 reg = <0x0 0x700e3000 0x0 0x100>;
1360 reg = <0 0x70110000 0 0x100>, /* DFLL control */
1361 <0 0x70110000 0 0x100>, /* I2C output control */
1362 <0 0x70110100 0 0x100>, /* Integrated I2C controller */
1363 <0 0x70110200 0 0x100>; /* Look-up table RAM */
1372 #clock-cells = <0>;
1385 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
1390 reg = <0x702e2000 0x2000>;
1424 reg = <0x702f9000 0x1000>,
1425 <0x702fa000 0x2000>;
1434 reg = <0x702d0800 0x800>;
1441 ranges = <0x702d0000 0x702d0000 0x0000e400>;
1446 reg = <0x702d0000 0x800>;
1471 #size-cells = <0>;
1473 admaif1_port: port@0 {
1474 reg = <0>;
1557 reg = <0x702d1000 0x100>;
1570 reg = <0x702d1100 0x100>;
1583 reg = <0x702d1200 0x100>;
1596 reg = <0x702d1300 0x100>;
1609 reg = <0x702d1400 0x100>;
1622 reg = <0x702d4000 0x100>;
1634 reg = <0x702d4100 0x100>;
1646 reg = <0x702d4200 0x100>;
1658 reg = <0x702d2000 0x200>;
1665 reg = <0x702d2200 0x200>;
1672 reg = <0x702d2400 0x200>;
1679 reg = <0x702d2600 0x200>;
1686 reg = <0x702da000 0x200>;
1693 reg = <0x702da200 0x200>;
1700 reg = <0x702d3000 0x100>;
1707 reg = <0x702d3100 0x100>;
1714 reg = <0x702d3800 0x100>;
1721 reg = <0x702d3900 0x100>;
1728 reg = <0x702d8000 0x100>;
1737 reg = <0x702d8100 0x100>;
1742 reg = <0x702d8200 0x200>;
1748 reg = <0x702d8400 0x100>;
1757 reg = <0x702d8500 0x100>;
1762 reg = <0x702d8600 0x200>;
1768 reg = <0x702dbb00 0x800>;
1775 #size-cells = <0>;
1777 port@0 {
1778 reg = <0x0>;
1786 reg = <0x1>;
1794 reg = <0x2>;
1802 reg = <0x3>;
1810 reg = <0x4>;
1816 reg = <0x5>;
1824 reg = <0x6>;
1832 reg = <0x7>;
1840 reg = <0x8>;
1848 reg = <0x9>;
1860 reg = <0x0 0x70410000 0x0 0x1000>;
1863 #size-cells = <0>;
1876 reg = <0x0 0x7d000000 0x0 0x4000>;
1889 reg = <0x0 0x7d000000 0x0 0x4000>,
1890 <0x0 0x7d000000 0x0 0x4000>;
1898 nvidia,hssync-start-delay = <0>;
1903 nvidia,xcvr-lsfslew = <0>;
1914 reg = <0x0 0x7d004000 0x0 0x4000>;
1927 reg = <0x0 0x7d004000 0x0 0x4000>,
1928 <0x0 0x7d000000 0x0 0x4000>;
1936 nvidia,hssync-start-delay = <0>;
1941 nvidia,xcvr-lsfslew = <0>;
1951 #size-cells = <0>;
1953 cpu@0 {
1956 reg = <0>;
1996 arm,psci-suspend-param = <0x40000007>;
2017 interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1}
2031 assigned-clock-parents = <0>, <0>, <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
2038 polling-delay = <0>;
2046 hysteresis = <0>;
2066 polling-delay-passive = <0>;
2067 polling-delay = <0>;
2093 hysteresis = <0>;
2100 cooling-device = <&emc 0 0>;
2113 polling-delay = <0>;
2121 hysteresis = <0>;
2141 polling-delay-passive = <0>;
2142 polling-delay = <0>;
2150 hysteresis = <0>;