Lines Matching +full:tegra210 +full:- +full:xudc
1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 #include <dt-bindings/power/tegra194-powergate.h>
9 #include <dt-bindings/reset/tegra194-reset.h>
10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
11 #include <dt-bindings/memory/tegra194-mc.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
21 compatible = "simple-bus";
22 #address-cells = <1>;
23 #size-cells = <1>;
27 compatible = "nvidia,tegra194-misc";
33 compatible = "nvidia,tegra194-gpio";
34 reg-names = "security", "gpio";
85 #interrupt-cells = <2>;
86 interrupt-controller;
87 #gpio-cells = <2>;
88 gpio-controller;
91 cbb-noc@2300000 {
92 compatible = "nvidia,tegra194-cbb-noc";
102 compatible = "nvidia,tegra194-axi2apb";
113 compatible = "nvidia,tegra194-eqos",
114 "nvidia,tegra186-eqos",
115 "snps,dwc-qos-ethernet-4.10";
123 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
125 reset-names = "eqos";
128 interconnect-names = "dma-mem", "write";
132 snps,write-requests = <1>;
133 snps,read-requests = <3>;
134 snps,burst-map = <0x7>;
139 gpcdma: dma-controller@2600000 {
140 compatible = "nvidia,tegra194-gpcdma",
141 "nvidia,tegra186-gpcdma";
144 reset-names = "gpcdma";
176 #dma-cells = <1>;
178 dma-coherent;
183 compatible = "nvidia,tegra194-aconnect",
184 "nvidia,tegra210-aconnect";
187 clock-names = "ape", "apb2ape";
188 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>;
189 #address-cells = <1>;
190 #size-cells = <1>;
194 adma: dma-controller@2930000 {
195 compatible = "nvidia,tegra194-adma",
196 "nvidia,tegra186-adma";
198 interrupt-parent = <&agic>;
231 #dma-cells = <1>;
233 clock-names = "d_audio";
237 agic: interrupt-controller@2a40000 {
238 compatible = "nvidia,tegra194-agic",
239 "nvidia,tegra210-agic";
240 #interrupt-cells = <3>;
241 interrupt-controller;
248 clock-names = "clk";
253 compatible = "nvidia,tegra194-ahub",
254 "nvidia,tegra186-ahub";
257 clock-names = "ahub";
258 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>;
259 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
260 #address-cells = <1>;
261 #size-cells = <1>;
266 compatible = "nvidia,tegra194-admaif",
267 "nvidia,tegra186-admaif";
289 dma-names = "rx1", "tx1",
312 interconnect-names = "dma-mem", "write";
317 compatible = "nvidia,tegra194-i2s",
318 "nvidia,tegra210-i2s";
322 clock-names = "i2s", "sync_input";
323 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>;
324 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
325 assigned-clock-rates = <1536000>;
326 sound-name-prefix = "I2S1";
331 compatible = "nvidia,tegra194-i2s",
332 "nvidia,tegra210-i2s";
336 clock-names = "i2s", "sync_input";
337 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>;
338 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
339 assigned-clock-rates = <1536000>;
340 sound-name-prefix = "I2S2";
345 compatible = "nvidia,tegra194-i2s",
346 "nvidia,tegra210-i2s";
350 clock-names = "i2s", "sync_input";
351 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>;
352 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
353 assigned-clock-rates = <1536000>;
354 sound-name-prefix = "I2S3";
359 compatible = "nvidia,tegra194-i2s",
360 "nvidia,tegra210-i2s";
364 clock-names = "i2s", "sync_input";
365 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>;
366 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
367 assigned-clock-rates = <1536000>;
368 sound-name-prefix = "I2S4";
373 compatible = "nvidia,tegra194-i2s",
374 "nvidia,tegra210-i2s";
378 clock-names = "i2s", "sync_input";
379 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>;
380 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
381 assigned-clock-rates = <1536000>;
382 sound-name-prefix = "I2S5";
387 compatible = "nvidia,tegra194-i2s",
388 "nvidia,tegra210-i2s";
392 clock-names = "i2s", "sync_input";
393 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>;
394 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
395 assigned-clock-rates = <1536000>;
396 sound-name-prefix = "I2S6";
401 compatible = "nvidia,tegra194-dmic",
402 "nvidia,tegra210-dmic";
405 clock-names = "dmic";
406 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>;
407 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
408 assigned-clock-rates = <3072000>;
409 sound-name-prefix = "DMIC1";
414 compatible = "nvidia,tegra194-dmic",
415 "nvidia,tegra210-dmic";
418 clock-names = "dmic";
419 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>;
420 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
421 assigned-clock-rates = <3072000>;
422 sound-name-prefix = "DMIC2";
427 compatible = "nvidia,tegra194-dmic",
428 "nvidia,tegra210-dmic";
431 clock-names = "dmic";
432 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>;
433 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
434 assigned-clock-rates = <3072000>;
435 sound-name-prefix = "DMIC3";
440 compatible = "nvidia,tegra194-dmic",
441 "nvidia,tegra210-dmic";
444 clock-names = "dmic";
445 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>;
446 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
447 assigned-clock-rates = <3072000>;
448 sound-name-prefix = "DMIC4";
453 compatible = "nvidia,tegra194-dspk",
454 "nvidia,tegra186-dspk";
457 clock-names = "dspk";
458 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>;
459 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
460 assigned-clock-rates = <12288000>;
461 sound-name-prefix = "DSPK1";
466 compatible = "nvidia,tegra194-dspk",
467 "nvidia,tegra186-dspk";
470 clock-names = "dspk";
471 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>;
472 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
473 assigned-clock-rates = <12288000>;
474 sound-name-prefix = "DSPK2";
479 compatible = "nvidia,tegra194-sfc",
480 "nvidia,tegra210-sfc";
482 sound-name-prefix = "SFC1";
487 compatible = "nvidia,tegra194-sfc",
488 "nvidia,tegra210-sfc";
490 sound-name-prefix = "SFC2";
495 compatible = "nvidia,tegra194-sfc",
496 "nvidia,tegra210-sfc";
498 sound-name-prefix = "SFC3";
503 compatible = "nvidia,tegra194-sfc",
504 "nvidia,tegra210-sfc";
506 sound-name-prefix = "SFC4";
511 compatible = "nvidia,tegra194-mvc",
512 "nvidia,tegra210-mvc";
514 sound-name-prefix = "MVC1";
519 compatible = "nvidia,tegra194-mvc",
520 "nvidia,tegra210-mvc";
522 sound-name-prefix = "MVC2";
527 compatible = "nvidia,tegra194-amx";
529 sound-name-prefix = "AMX1";
534 compatible = "nvidia,tegra194-amx";
536 sound-name-prefix = "AMX2";
541 compatible = "nvidia,tegra194-amx";
543 sound-name-prefix = "AMX3";
548 compatible = "nvidia,tegra194-amx";
550 sound-name-prefix = "AMX4";
555 compatible = "nvidia,tegra194-adx",
556 "nvidia,tegra210-adx";
558 sound-name-prefix = "ADX1";
563 compatible = "nvidia,tegra194-adx",
564 "nvidia,tegra210-adx";
566 sound-name-prefix = "ADX2";
571 compatible = "nvidia,tegra194-adx",
572 "nvidia,tegra210-adx";
574 sound-name-prefix = "ADX3";
579 compatible = "nvidia,tegra194-adx",
580 "nvidia,tegra210-adx";
582 sound-name-prefix = "ADX4";
586 tegra_ope1: processing-engine@2908000 {
587 compatible = "nvidia,tegra194-ope",
588 "nvidia,tegra210-ope";
590 #address-cells = <1>;
591 #size-cells = <1>;
593 sound-name-prefix = "OPE1";
597 compatible = "nvidia,tegra194-peq",
598 "nvidia,tegra210-peq";
602 dynamic-range-compressor@2908200 {
603 compatible = "nvidia,tegra194-mbdrc",
604 "nvidia,tegra210-mbdrc";
610 compatible = "nvidia,tegra194-amixer",
611 "nvidia,tegra210-amixer";
613 sound-name-prefix = "MIXER1";
618 compatible = "nvidia,tegra194-asrc",
619 "nvidia,tegra186-asrc";
621 sound-name-prefix = "ASRC1";
628 compatible = "nvidia,tegra194-pinmux";
638 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
639 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
649 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
650 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
657 mc: memory-controller@2c00000 {
658 compatible = "nvidia,tegra194-mc";
659 reg = <0x02c00000 0x10000>, /* MC-SID */
677 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3",
681 #interconnect-cells = <1>;
684 #address-cells = <2>;
685 #size-cells = <2>;
706 dma-ranges = <0x0 0x0 0x0 0x80 0x0>;
708 emc: external-memory-controller@2c60000 {
709 compatible = "nvidia,tegra194-emc";
714 clock-names = "emc";
716 #interconnect-cells = <0>;
723 compatible = "nvidia,tegra186-timer";
739 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
741 reg-shift = <2>;
744 clock-names = "serial";
746 reset-names = "serial";
751 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
753 reg-shift = <2>;
756 clock-names = "serial";
758 reset-names = "serial";
763 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
765 reg-shift = <2>;
768 clock-names = "serial";
770 reset-names = "serial";
775 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
777 reg-shift = <2>;
780 clock-names = "serial";
782 reset-names = "serial";
787 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
789 reg-shift = <2>;
792 clock-names = "serial";
794 reset-names = "serial";
799 compatible = "nvidia,tegra194-i2c";
802 #address-cells = <1>;
803 #size-cells = <0>;
805 clock-names = "div-clk";
807 reset-names = "i2c";
809 dma-coherent;
811 dma-names = "rx", "tx";
816 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
818 reg-shift = <2>;
821 clock-names = "serial";
823 reset-names = "serial";
828 compatible = "nvidia,tegra194-i2c";
831 #address-cells = <1>;
832 #size-cells = <0>;
834 clock-names = "div-clk";
836 reset-names = "i2c";
838 dma-coherent;
840 dma-names = "rx", "tx";
846 compatible = "nvidia,tegra194-i2c";
849 #address-cells = <1>;
850 #size-cells = <0>;
852 clock-names = "div-clk";
854 reset-names = "i2c";
855 pinctrl-0 = <&state_dpaux1_i2c>;
856 pinctrl-1 = <&state_dpaux1_off>;
857 pinctrl-names = "default", "idle";
859 dma-coherent;
861 dma-names = "rx", "tx";
867 compatible = "nvidia,tegra194-i2c";
870 #address-cells = <1>;
871 #size-cells = <0>;
873 clock-names = "div-clk";
875 reset-names = "i2c";
876 pinctrl-0 = <&state_dpaux0_i2c>;
877 pinctrl-1 = <&state_dpaux0_off>;
878 pinctrl-names = "default", "idle";
880 dma-coherent;
882 dma-names = "rx", "tx";
888 compatible = "nvidia,tegra194-i2c";
891 #address-cells = <1>;
892 #size-cells = <0>;
894 clock-names = "div-clk";
896 reset-names = "i2c";
897 pinctrl-0 = <&state_dpaux2_i2c>;
898 pinctrl-1 = <&state_dpaux2_off>;
899 pinctrl-names = "default", "idle";
901 dma-coherent;
903 dma-names = "rx", "tx";
909 compatible = "nvidia,tegra194-i2c";
912 #address-cells = <1>;
913 #size-cells = <0>;
915 clock-names = "div-clk";
917 reset-names = "i2c";
918 pinctrl-0 = <&state_dpaux3_i2c>;
919 pinctrl-1 = <&state_dpaux3_off>;
920 pinctrl-names = "default", "idle";
922 dma-coherent;
924 dma-names = "rx", "tx";
929 compatible = "nvidia,tegra194-qspi";
932 #address-cells = <1>;
933 #size-cells = <0>;
936 clock-names = "qspi", "qspi_out";
938 reset-names = "qspi";
943 compatible = "nvidia,tegra194-qspi";
946 #address-cells = <1>;
947 #size-cells = <0>;
950 clock-names = "qspi", "qspi_out";
952 reset-names = "qspi";
957 compatible = "nvidia,tegra194-pwm",
958 "nvidia,tegra186-pwm";
961 clock-names = "pwm";
963 reset-names = "pwm";
965 #pwm-cells = <2>;
969 compatible = "nvidia,tegra194-pwm",
970 "nvidia,tegra186-pwm";
973 clock-names = "pwm";
975 reset-names = "pwm";
977 #pwm-cells = <2>;
981 compatible = "nvidia,tegra194-pwm",
982 "nvidia,tegra186-pwm";
985 clock-names = "pwm";
987 reset-names = "pwm";
989 #pwm-cells = <2>;
993 compatible = "nvidia,tegra194-pwm",
994 "nvidia,tegra186-pwm";
997 clock-names = "pwm";
999 reset-names = "pwm";
1001 #pwm-cells = <2>;
1005 compatible = "nvidia,tegra194-pwm",
1006 "nvidia,tegra186-pwm";
1009 clock-names = "pwm";
1011 reset-names = "pwm";
1013 #pwm-cells = <2>;
1017 compatible = "nvidia,tegra194-pwm",
1018 "nvidia,tegra186-pwm";
1021 clock-names = "pwm";
1023 reset-names = "pwm";
1025 #pwm-cells = <2>;
1029 compatible = "nvidia,tegra194-pwm",
1030 "nvidia,tegra186-pwm";
1033 clock-names = "pwm";
1035 reset-names = "pwm";
1037 #pwm-cells = <2>;
1041 compatible = "nvidia,tegra194-sdhci";
1046 clock-names = "sdhci", "tmclk";
1047 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC1>,
1049 assigned-clock-parents =
1053 reset-names = "sdhci";
1056 interconnect-names = "dma-mem", "write";
1058 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
1059 pinctrl-0 = <&sdmmc1_3v3>;
1060 pinctrl-1 = <&sdmmc1_1v8>;
1061 nvidia,pad-autocal-pull-up-offset-3v3-timeout =
1063 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
1065 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
1066 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
1068 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
1069 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
1070 nvidia,default-tap = <0x9>;
1071 nvidia,default-trim = <0x5>;
1072 sd-uhs-sdr25;
1073 sd-uhs-sdr50;
1074 sd-uhs-ddr50;
1075 sd-uhs-sdr104;
1080 compatible = "nvidia,tegra194-sdhci";
1085 clock-names = "sdhci", "tmclk";
1086 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC3>,
1088 assigned-clock-parents =
1092 reset-names = "sdhci";
1095 interconnect-names = "dma-mem", "write";
1097 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
1098 pinctrl-0 = <&sdmmc3_3v3>;
1099 pinctrl-1 = <&sdmmc3_1v8>;
1100 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
1101 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
1102 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
1103 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
1105 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
1106 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
1108 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
1109 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
1110 nvidia,default-tap = <0x9>;
1111 nvidia,default-trim = <0x5>;
1112 sd-uhs-sdr25;
1113 sd-uhs-sdr50;
1114 sd-uhs-ddr50;
1115 sd-uhs-sdr104;
1120 compatible = "nvidia,tegra194-sdhci";
1125 clock-names = "sdhci", "tmclk";
1126 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
1128 assigned-clock-parents =
1131 reset-names = "sdhci";
1134 interconnect-names = "dma-mem", "write";
1136 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
1137 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
1138 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
1139 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
1141 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
1142 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
1144 nvidia,default-tap = <0x8>;
1145 nvidia,default-trim = <0x14>;
1146 nvidia,dqs-trim = <40>;
1147 cap-mmc-highspeed;
1148 mmc-ddr-1_8v;
1149 mmc-hs200-1_8v;
1150 mmc-hs400-1_8v;
1151 mmc-hs400-enhanced-strobe;
1152 supports-cqe;
1157 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda";
1163 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
1166 reset-names = "hda", "hda2hdmi";
1167 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1170 interconnect-names = "dma-mem", "write";
1176 compatible = "nvidia,tegra194-xusb-padctl";
1179 reg-names = "padctl", "ao";
1183 reset-names = "padctl";
1190 clock-names = "trk";
1193 usb2-0 {
1196 #phy-cells = <0>;
1199 usb2-1 {
1202 #phy-cells = <0>;
1205 usb2-2 {
1208 #phy-cells = <0>;
1211 usb2-3 {
1214 #phy-cells = <0>;
1221 usb3-0 {
1224 #phy-cells = <0>;
1227 usb3-1 {
1230 #phy-cells = <0>;
1233 usb3-2 {
1236 #phy-cells = <0>;
1239 usb3-3 {
1242 #phy-cells = <0>;
1249 usb2-0 {
1253 usb2-1 {
1257 usb2-2 {
1261 usb2-3 {
1265 usb3-0 {
1269 usb3-1 {
1273 usb3-2 {
1277 usb3-3 {
1284 compatible = "nvidia,tegra194-xudc";
1287 reg-names = "base", "fpci";
1293 clock-names = "dev", "ss", "ss_src", "fs_src";
1296 interconnect-names = "dma-mem", "write";
1298 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>,
1300 power-domain-names = "dev", "ss";
1301 nvidia,xusb-padctl = <&xusb_padctl>;
1306 compatible = "nvidia,tegra194-xusb";
1309 reg-names = "hcd", "fpci";
1323 clock-names = "xusb_host", "xusb_falcon_src",
1329 interconnect-names = "dma-mem", "write";
1332 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>,
1334 power-domain-names = "xusb_host", "xusb_ss";
1336 nvidia,xusb-padctl = <&xusb_padctl>;
1341 compatible = "nvidia,tegra194-efuse";
1344 clock-names = "fuse";
1347 gic: interrupt-controller@3881000 {
1348 compatible = "arm,gic-400";
1349 #interrupt-cells = <3>;
1350 interrupt-controller;
1357 interrupt-parent = <&gic>;
1361 compatible = "nvidia,tegra194-cec";
1365 clock-names = "cec";
1370 compatible = "nvidia,tegra194-hsp";
1381 interrupt-names = "doorbell", "shared0", "shared1", "shared2",
1384 #mbox-cells = <2>;
1388 compatible = "nvidia,tegra194-p2u";
1390 reg-names = "ctl";
1392 #phy-cells = <0>;
1396 compatible = "nvidia,tegra194-p2u";
1398 reg-names = "ctl";
1400 #phy-cells = <0>;
1404 compatible = "nvidia,tegra194-p2u";
1406 reg-names = "ctl";
1408 #phy-cells = <0>;
1412 compatible = "nvidia,tegra194-p2u";
1414 reg-names = "ctl";
1416 #phy-cells = <0>;
1420 compatible = "nvidia,tegra194-p2u";
1422 reg-names = "ctl";
1424 #phy-cells = <0>;
1428 compatible = "nvidia,tegra194-p2u";
1430 reg-names = "ctl";
1432 #phy-cells = <0>;
1436 compatible = "nvidia,tegra194-p2u";
1438 reg-names = "ctl";
1440 #phy-cells = <0>;
1444 compatible = "nvidia,tegra194-p2u";
1446 reg-names = "ctl";
1448 #phy-cells = <0>;
1452 compatible = "nvidia,tegra194-p2u";
1454 reg-names = "ctl";
1456 #phy-cells = <0>;
1460 compatible = "nvidia,tegra194-p2u";
1462 reg-names = "ctl";
1464 #phy-cells = <0>;
1468 compatible = "nvidia,tegra194-p2u";
1470 reg-names = "ctl";
1472 #phy-cells = <0>;
1476 compatible = "nvidia,tegra194-p2u";
1478 reg-names = "ctl";
1480 #phy-cells = <0>;
1484 compatible = "nvidia,tegra194-p2u";
1486 reg-names = "ctl";
1488 #phy-cells = <0>;
1492 compatible = "nvidia,tegra194-p2u";
1494 reg-names = "ctl";
1496 #phy-cells = <0>;
1500 compatible = "nvidia,tegra194-p2u";
1502 reg-names = "ctl";
1504 #phy-cells = <0>;
1508 compatible = "nvidia,tegra194-p2u";
1510 reg-names = "ctl";
1512 #phy-cells = <0>;
1516 compatible = "nvidia,tegra194-p2u";
1518 reg-names = "ctl";
1520 #phy-cells = <0>;
1524 compatible = "nvidia,tegra194-p2u";
1526 reg-names = "ctl";
1528 #phy-cells = <0>;
1532 compatible = "nvidia,tegra194-p2u";
1534 reg-names = "ctl";
1536 #phy-cells = <0>;
1540 compatible = "nvidia,tegra194-p2u";
1542 reg-names = "ctl";
1544 #phy-cells = <0>;
1547 sce-noc@b600000 {
1548 compatible = "nvidia,tegra194-sce-noc";
1557 rce-noc@be00000 {
1558 compatible = "nvidia,tegra194-rce-noc";
1568 compatible = "nvidia,tegra194-hsp";
1578 interrupt-names = "shared1", "shared2", "shared3", "shared4";
1579 #mbox-cells = <2>;
1583 compatible = "nvidia,tegra194-i2c";
1586 #address-cells = <1>;
1587 #size-cells = <0>;
1589 clock-names = "div-clk";
1591 reset-names = "i2c";
1593 dma-coherent;
1595 dma-names = "rx", "tx";
1600 compatible = "nvidia,tegra194-i2c";
1603 #address-cells = <1>;
1604 #size-cells = <0>;
1606 clock-names = "div-clk";
1608 reset-names = "i2c";
1610 dma-coherent;
1612 dma-names = "rx", "tx";
1617 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
1619 reg-shift = <2>;
1622 clock-names = "serial";
1624 reset-names = "serial";
1629 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
1631 reg-shift = <2>;
1634 clock-names = "serial";
1636 reset-names = "serial";
1641 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc";
1643 interrupt-parent = <&pmc>;
1646 clock-names = "rtc";
1651 compatible = "nvidia,tegra194-gpio-aon";
1652 reg-names = "security", "gpio";
1659 gpio-controller;
1660 #gpio-cells = <2>;
1661 interrupt-controller;
1662 #interrupt-cells = <2>;
1666 compatible = "nvidia,tegra194-pwm",
1667 "nvidia,tegra186-pwm";
1670 clock-names = "pwm";
1672 reset-names = "pwm";
1674 #pwm-cells = <2>;
1678 compatible = "nvidia,tegra194-pmc";
1684 reg-names = "pmc", "wake", "aotag", "scratch", "misc";
1686 #interrupt-cells = <2>;
1687 interrupt-controller;
1688 sdmmc1_3v3: sdmmc1-3v3 {
1689 pins = "sdmmc1-hv";
1690 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1693 sdmmc1_1v8: sdmmc1-1v8 {
1694 pins = "sdmmc1-hv";
1695 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1697 sdmmc3_3v3: sdmmc3-3v3 {
1698 pins = "sdmmc3-hv";
1699 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1702 sdmmc3_1v8: sdmmc3-1v8 {
1703 pins = "sdmmc3-hv";
1704 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1709 aon-noc@c600000 {
1710 compatible = "nvidia,tegra194-aon-noc";
1718 bpmp-noc@d600000 {
1719 compatible = "nvidia,tegra194-bpmp-noc";
1729 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500";
1796 stream-match-mask = <0x7f80>;
1797 #global-interrupts = <1>;
1798 #iommu-cells = <1>;
1800 nvidia,memory-controller = <&mc>;
1805 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500";
1874 stream-match-mask = <0x7f80>;
1875 #global-interrupts = <2>;
1876 #iommu-cells = <1>;
1878 nvidia,memory-controller = <&mc>;
1883 compatible = "nvidia,tegra194-host1x";
1886 reg-names = "hypervisor", "vm";
1889 interrupt-names = "syncpt", "host1x";
1891 clock-names = "host1x";
1893 reset-names = "host1x";
1895 #address-cells = <1>;
1896 #size-cells = <1>;
1900 interconnect-names = "dma-mem";
1904 iommu-map = <0 &smmu TEGRA194_SID_HOST1X_CTX0 1>,
1914 compatible = "nvidia,tegra194-nvdec";
1917 clock-names = "nvdec";
1919 reset-names = "nvdec";
1921 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>;
1925 interconnect-names = "dma-mem", "read-1", "write";
1927 dma-coherent;
1929 nvidia,host1x-class = <0xf5>;
1932 display-hub@15200000 {
1933 compatible = "nvidia,tegra194-display";
1942 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
1946 clock-names = "disp", "hub";
1949 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1951 #address-cells = <1>;
1952 #size-cells = <1>;
1957 compatible = "nvidia,tegra194-dc";
1961 clock-names = "dc";
1963 reset-names = "dc";
1965 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1968 interconnect-names = "dma-mem", "read-1";
1975 compatible = "nvidia,tegra194-dc";
1979 clock-names = "dc";
1981 reset-names = "dc";
1983 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
1986 interconnect-names = "dma-mem", "read-1";
1993 compatible = "nvidia,tegra194-dc";
1997 clock-names = "dc";
1999 reset-names = "dc";
2001 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
2004 interconnect-names = "dma-mem", "read-1";
2011 compatible = "nvidia,tegra194-dc";
2015 clock-names = "dc";
2017 reset-names = "dc";
2019 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
2022 interconnect-names = "dma-mem", "read-1";
2030 compatible = "nvidia,tegra194-vic";
2034 clock-names = "vic";
2036 reset-names = "vic";
2038 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>;
2041 interconnect-names = "dma-mem", "write";
2043 dma-coherent;
2047 compatible = "nvidia,tegra194-nvjpg";
2050 clock-names = "nvjpg";
2052 reset-names = "nvjpg";
2054 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>;
2057 interconnect-names = "dma-mem", "write";
2059 dma-coherent;
2063 compatible = "nvidia,tegra194-nvdec";
2066 clock-names = "nvdec";
2068 reset-names = "nvdec";
2070 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>;
2074 interconnect-names = "dma-mem", "read-1", "write";
2076 dma-coherent;
2078 nvidia,host1x-class = <0xf0>;
2082 compatible = "nvidia,tegra194-nvenc";
2085 clock-names = "nvenc";
2087 reset-names = "nvenc";
2089 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>;
2093 interconnect-names = "dma-mem", "read-1", "write";
2095 dma-coherent;
2097 nvidia,host1x-class = <0x21>;
2101 compatible = "nvidia,tegra194-dpaux";
2106 clock-names = "dpaux", "parent";
2108 reset-names = "dpaux";
2111 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2113 state_dpaux0_aux: pinmux-aux {
2114 groups = "dpaux-io";
2118 state_dpaux0_i2c: pinmux-i2c {
2119 groups = "dpaux-io";
2123 state_dpaux0_off: pinmux-off {
2124 groups = "dpaux-io";
2128 i2c-bus {
2129 #address-cells = <1>;
2130 #size-cells = <0>;
2135 compatible = "nvidia,tegra194-dpaux";
2140 clock-names = "dpaux", "parent";
2142 reset-names = "dpaux";
2145 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2147 state_dpaux1_aux: pinmux-aux {
2148 groups = "dpaux-io";
2152 state_dpaux1_i2c: pinmux-i2c {
2153 groups = "dpaux-io";
2157 state_dpaux1_off: pinmux-off {
2158 groups = "dpaux-io";
2162 i2c-bus {
2163 #address-cells = <1>;
2164 #size-cells = <0>;
2169 compatible = "nvidia,tegra194-dpaux";
2174 clock-names = "dpaux", "parent";
2176 reset-names = "dpaux";
2179 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2181 state_dpaux2_aux: pinmux-aux {
2182 groups = "dpaux-io";
2186 state_dpaux2_i2c: pinmux-i2c {
2187 groups = "dpaux-io";
2191 state_dpaux2_off: pinmux-off {
2192 groups = "dpaux-io";
2196 i2c-bus {
2197 #address-cells = <1>;
2198 #size-cells = <0>;
2203 compatible = "nvidia,tegra194-dpaux";
2208 clock-names = "dpaux", "parent";
2210 reset-names = "dpaux";
2213 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2215 state_dpaux3_aux: pinmux-aux {
2216 groups = "dpaux-io";
2220 state_dpaux3_i2c: pinmux-i2c {
2221 groups = "dpaux-io";
2225 state_dpaux3_off: pinmux-off {
2226 groups = "dpaux-io";
2230 i2c-bus {
2231 #address-cells = <1>;
2232 #size-cells = <0>;
2237 compatible = "nvidia,tegra194-nvenc";
2240 clock-names = "nvenc";
2242 reset-names = "nvenc";
2244 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>;
2248 interconnect-names = "dma-mem", "read-1", "write";
2250 dma-coherent;
2252 nvidia,host1x-class = <0x22>;
2256 compatible = "nvidia,tegra194-sor";
2265 clock-names = "sor", "out", "parent", "dp", "safe",
2268 reset-names = "sor";
2269 pinctrl-0 = <&state_dpaux0_aux>;
2270 pinctrl-1 = <&state_dpaux0_i2c>;
2271 pinctrl-2 = <&state_dpaux0_off>;
2272 pinctrl-names = "aux", "i2c", "off";
2275 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2280 compatible = "nvidia,tegra194-sor";
2289 clock-names = "sor", "out", "parent", "dp", "safe",
2292 reset-names = "sor";
2293 pinctrl-0 = <&state_dpaux1_aux>;
2294 pinctrl-1 = <&state_dpaux1_i2c>;
2295 pinctrl-2 = <&state_dpaux1_off>;
2296 pinctrl-names = "aux", "i2c", "off";
2299 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2304 compatible = "nvidia,tegra194-sor";
2313 clock-names = "sor", "out", "parent", "dp", "safe",
2316 reset-names = "sor";
2317 pinctrl-0 = <&state_dpaux2_aux>;
2318 pinctrl-1 = <&state_dpaux2_i2c>;
2319 pinctrl-2 = <&state_dpaux2_off>;
2320 pinctrl-names = "aux", "i2c", "off";
2323 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2328 compatible = "nvidia,tegra194-sor";
2337 clock-names = "sor", "out", "parent", "dp", "safe",
2340 reset-names = "sor";
2341 pinctrl-0 = <&state_dpaux3_aux>;
2342 pinctrl-1 = <&state_dpaux3_i2c>;
2343 pinctrl-2 = <&state_dpaux3_off>;
2344 pinctrl-names = "aux", "i2c", "off";
2347 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2358 interrupt-names = "stall", "nonstall";
2362 clock-names = "gpu", "pwr", "fuse";
2364 reset-names = "gpu";
2365 dma-coherent;
2367 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;
2380 interconnect-names = "dma-mem", "read-0-hp", "write-0",
2381 "read-1", "read-1-hp", "write-1",
2382 "read-2", "read-2-hp", "write-2",
2383 "read-3", "read-3-hp", "write-3";
2388 compatible = "nvidia,tegra194-pcie";
2389 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
2394 reg-names = "appl", "config", "atu_dma", "dbi";
2398 #address-cells = <3>;
2399 #size-cells = <2>;
2401 num-lanes = <1>;
2402 linux,pci-domain = <1>;
2405 clock-names = "core";
2409 reset-names = "apb", "core";
2413 interrupt-names = "intr", "msi";
2415 #interrupt-cells = <1>;
2416 interrupt-map-mask = <0 0 0 0>;
2417 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
2421 nvidia,aspm-cmrt-us = <60>;
2422 nvidia,aspm-pwr-on-t-us = <20>;
2423 nvidia,aspm-l0s-entrance-latency-us = <3>;
2425 bus-range = <0x0 0xff>;
2428 …00000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 Ki…
2433 interconnect-names = "dma-mem", "write";
2434 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>;
2435 iommu-map-mask = <0x0>;
2436 dma-coherent;
2440 compatible = "nvidia,tegra194-pcie";
2441 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
2446 reg-names = "appl", "config", "atu_dma", "dbi";
2450 #address-cells = <3>;
2451 #size-cells = <2>;
2453 num-lanes = <1>;
2454 linux,pci-domain = <2>;
2457 clock-names = "core";
2461 reset-names = "apb", "core";
2465 interrupt-names = "intr", "msi";
2467 #interrupt-cells = <1>;
2468 interrupt-map-mask = <0 0 0 0>;
2469 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
2473 nvidia,aspm-cmrt-us = <60>;
2474 nvidia,aspm-pwr-on-t-us = <20>;
2475 nvidia,aspm-l0s-entrance-latency-us = <3>;
2477 bus-range = <0x0 0xff>;
2480 …00000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 Ki…
2485 interconnect-names = "dma-mem", "write";
2486 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>;
2487 iommu-map-mask = <0x0>;
2488 dma-coherent;
2492 compatible = "nvidia,tegra194-pcie";
2493 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
2498 reg-names = "appl", "config", "atu_dma", "dbi";
2502 #address-cells = <3>;
2503 #size-cells = <2>;
2505 num-lanes = <1>;
2506 linux,pci-domain = <3>;
2509 clock-names = "core";
2513 reset-names = "apb", "core";
2517 interrupt-names = "intr", "msi";
2519 #interrupt-cells = <1>;
2520 interrupt-map-mask = <0 0 0 0>;
2521 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
2525 nvidia,aspm-cmrt-us = <60>;
2526 nvidia,aspm-pwr-on-t-us = <20>;
2527 nvidia,aspm-l0s-entrance-latency-us = <3>;
2529 bus-range = <0x0 0xff>;
2532 …<0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB +…
2537 interconnect-names = "dma-mem", "write";
2538 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>;
2539 iommu-map-mask = <0x0>;
2540 dma-coherent;
2544 compatible = "nvidia,tegra194-pcie";
2545 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
2550 reg-names = "appl", "config", "atu_dma", "dbi";
2554 #address-cells = <3>;
2555 #size-cells = <2>;
2557 num-lanes = <4>;
2558 linux,pci-domain = <4>;
2561 clock-names = "core";
2565 reset-names = "apb", "core";
2569 interrupt-names = "intr", "msi";
2571 #interrupt-cells = <1>;
2572 interrupt-map-mask = <0 0 0 0>;
2573 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
2577 nvidia,aspm-cmrt-us = <60>;
2578 nvidia,aspm-pwr-on-t-us = <20>;
2579 nvidia,aspm-l0s-entrance-latency-us = <3>;
2581 bus-range = <0x0 0xff>;
2584 …000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB…
2589 interconnect-names = "dma-mem", "write";
2590 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
2591 iommu-map-mask = <0x0>;
2592 dma-coherent;
2596 compatible = "nvidia,tegra194-pcie";
2597 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
2602 reg-names = "appl", "config", "atu_dma", "dbi";
2606 #address-cells = <3>;
2607 #size-cells = <2>;
2609 num-lanes = <8>;
2610 linux,pci-domain = <0>;
2613 clock-names = "core";
2617 reset-names = "apb", "core";
2621 interrupt-names = "intr", "msi";
2623 #interrupt-cells = <1>;
2624 interrupt-map-mask = <0 0 0 0>;
2625 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
2629 nvidia,aspm-cmrt-us = <60>;
2630 nvidia,aspm-pwr-on-t-us = <20>;
2631 nvidia,aspm-l0s-entrance-latency-us = <3>;
2633 bus-range = <0x0 0xff>;
2636 …000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB…
2641 interconnect-names = "dma-mem", "write";
2642 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
2643 iommu-map-mask = <0x0>;
2644 dma-coherent;
2648 compatible = "nvidia,tegra194-pcie";
2649 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
2654 reg-names = "appl", "config", "atu_dma", "dbi";
2658 #address-cells = <3>;
2659 #size-cells = <2>;
2661 num-lanes = <8>;
2662 linux,pci-domain = <5>;
2664 pinctrl-names = "default";
2665 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
2668 clock-names = "core";
2672 reset-names = "apb", "core";
2676 interrupt-names = "intr", "msi";
2680 #interrupt-cells = <1>;
2681 interrupt-map-mask = <0 0 0 0>;
2682 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2684 nvidia,aspm-cmrt-us = <60>;
2685 nvidia,aspm-pwr-on-t-us = <20>;
2686 nvidia,aspm-l0s-entrance-latency-us = <3>;
2688 bus-range = <0x0 0xff>;
2691 …000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB…
2696 interconnect-names = "dma-mem", "write";
2697 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
2698 iommu-map-mask = <0x0>;
2699 dma-coherent;
2702 pcie-ep@14160000 {
2703 compatible = "nvidia,tegra194-pcie-ep";
2704 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
2709 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2713 num-lanes = <4>;
2714 num-ib-windows = <2>;
2715 num-ob-windows = <8>;
2718 clock-names = "core";
2722 reset-names = "apb", "core";
2725 interrupt-names = "intr";
2729 nvidia,aspm-cmrt-us = <60>;
2730 nvidia,aspm-pwr-on-t-us = <20>;
2731 nvidia,aspm-l0s-entrance-latency-us = <3>;
2735 interconnect-names = "dma-mem", "write";
2736 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
2737 iommu-map-mask = <0x0>;
2738 dma-coherent;
2741 pcie-ep@14180000 {
2742 compatible = "nvidia,tegra194-pcie-ep";
2743 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
2748 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2752 num-lanes = <8>;
2753 num-ib-windows = <2>;
2754 num-ob-windows = <8>;
2757 clock-names = "core";
2761 reset-names = "apb", "core";
2764 interrupt-names = "intr";
2768 nvidia,aspm-cmrt-us = <60>;
2769 nvidia,aspm-pwr-on-t-us = <20>;
2770 nvidia,aspm-l0s-entrance-latency-us = <3>;
2774 interconnect-names = "dma-mem", "write";
2775 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
2776 iommu-map-mask = <0x0>;
2777 dma-coherent;
2780 pcie-ep@141a0000 {
2781 compatible = "nvidia,tegra194-pcie-ep";
2782 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
2787 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2791 num-lanes = <8>;
2792 num-ib-windows = <2>;
2793 num-ob-windows = <8>;
2795 pinctrl-names = "default";
2796 pinctrl-0 = <&clkreq_c5_bi_dir_state>;
2799 clock-names = "core";
2803 reset-names = "apb", "core";
2806 interrupt-names = "intr";
2810 nvidia,aspm-cmrt-us = <60>;
2811 nvidia,aspm-pwr-on-t-us = <20>;
2812 nvidia,aspm-l0s-entrance-latency-us = <3>;
2816 interconnect-names = "dma-mem", "write";
2817 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
2818 iommu-map-mask = <0x0>;
2819 dma-coherent;
2823 compatible = "nvidia,tegra194-sysram", "mmio-sram";
2825 #address-cells = <1>;
2826 #size-cells = <1>;
2828 no-memory-wc;
2832 label = "cpu-bpmp-tx";
2838 label = "cpu-bpmp-rx";
2844 compatible = "nvidia,tegra186-bpmp";
2848 #clock-cells = <1>;
2849 #reset-cells = <1>;
2850 #power-domain-cells = <1>;
2855 interconnect-names = "read", "write", "dma-mem", "dma-write";
2859 compatible = "nvidia,tegra186-bpmp-i2c";
2860 nvidia,bpmp-bus-id = <5>;
2861 #address-cells = <1>;
2862 #size-cells = <0>;
2866 compatible = "nvidia,tegra186-bpmp-thermal";
2867 #thermal-sensor-cells = <1>;
2872 compatible = "nvidia,tegra194-ccplex";
2874 #address-cells = <1>;
2875 #size-cells = <0>;
2878 compatible = "nvidia,tegra194-carmel";
2881 enable-method = "psci";
2882 i-cache-size = <131072>;
2883 i-cache-line-size = <64>;
2884 i-cache-sets = <512>;
2885 d-cache-size = <65536>;
2886 d-cache-line-size = <64>;
2887 d-cache-sets = <256>;
2888 next-level-cache = <&l2c_0>;
2892 compatible = "nvidia,tegra194-carmel";
2895 enable-method = "psci";
2896 i-cache-size = <131072>;
2897 i-cache-line-size = <64>;
2898 i-cache-sets = <512>;
2899 d-cache-size = <65536>;
2900 d-cache-line-size = <64>;
2901 d-cache-sets = <256>;
2902 next-level-cache = <&l2c_0>;
2906 compatible = "nvidia,tegra194-carmel";
2909 enable-method = "psci";
2910 i-cache-size = <131072>;
2911 i-cache-line-size = <64>;
2912 i-cache-sets = <512>;
2913 d-cache-size = <65536>;
2914 d-cache-line-size = <64>;
2915 d-cache-sets = <256>;
2916 next-level-cache = <&l2c_1>;
2920 compatible = "nvidia,tegra194-carmel";
2923 enable-method = "psci";
2924 i-cache-size = <131072>;
2925 i-cache-line-size = <64>;
2926 i-cache-sets = <512>;
2927 d-cache-size = <65536>;
2928 d-cache-line-size = <64>;
2929 d-cache-sets = <256>;
2930 next-level-cache = <&l2c_1>;
2934 compatible = "nvidia,tegra194-carmel";
2937 enable-method = "psci";
2938 i-cache-size = <131072>;
2939 i-cache-line-size = <64>;
2940 i-cache-sets = <512>;
2941 d-cache-size = <65536>;
2942 d-cache-line-size = <64>;
2943 d-cache-sets = <256>;
2944 next-level-cache = <&l2c_2>;
2948 compatible = "nvidia,tegra194-carmel";
2951 enable-method = "psci";
2952 i-cache-size = <131072>;
2953 i-cache-line-size = <64>;
2954 i-cache-sets = <512>;
2955 d-cache-size = <65536>;
2956 d-cache-line-size = <64>;
2957 d-cache-sets = <256>;
2958 next-level-cache = <&l2c_2>;
2962 compatible = "nvidia,tegra194-carmel";
2965 enable-method = "psci";
2966 i-cache-size = <131072>;
2967 i-cache-line-size = <64>;
2968 i-cache-sets = <512>;
2969 d-cache-size = <65536>;
2970 d-cache-line-size = <64>;
2971 d-cache-sets = <256>;
2972 next-level-cache = <&l2c_3>;
2976 compatible = "nvidia,tegra194-carmel";
2979 enable-method = "psci";
2980 i-cache-size = <131072>;
2981 i-cache-line-size = <64>;
2982 i-cache-sets = <512>;
2983 d-cache-size = <65536>;
2984 d-cache-line-size = <64>;
2985 d-cache-sets = <256>;
2986 next-level-cache = <&l2c_3>;
2989 cpu-map {
3031 l2c_0: l2-cache0 {
3032 cache-size = <2097152>;
3033 cache-line-size = <64>;
3034 cache-sets = <2048>;
3035 next-level-cache = <&l3c>;
3038 l2c_1: l2-cache1 {
3039 cache-size = <2097152>;
3040 cache-line-size = <64>;
3041 cache-sets = <2048>;
3042 next-level-cache = <&l3c>;
3045 l2c_2: l2-cache2 {
3046 cache-size = <2097152>;
3047 cache-line-size = <64>;
3048 cache-sets = <2048>;
3049 next-level-cache = <&l3c>;
3052 l2c_3: l2-cache3 {
3053 cache-size = <2097152>;
3054 cache-line-size = <64>;
3055 cache-sets = <2048>;
3056 next-level-cache = <&l3c>;
3059 l3c: l3-cache {
3060 cache-size = <4194304>;
3061 cache-line-size = <64>;
3062 cache-sets = <4096>;
3067 compatible = "nvidia,carmel-pmu";
3076 interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1
3081 compatible = "arm,psci-1.0";
3091 clock-names = "pll_a", "plla_out0";
3092 assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>,
3095 assigned-clock-parents = <0>,
3103 assigned-clock-rates = <258000000>;
3107 compatible = "nvidia,tegra194-tcu";
3110 mbox-names = "rx", "tx";
3113 thermal-zones {
3114 cpu-thermal {
3115 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>;
3119 gpu-thermal {
3120 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>;
3124 aux-thermal {
3125 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>;
3129 pllx-thermal {
3130 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>;
3134 ao-thermal {
3135 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>;
3139 tj-thermal {
3140 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>;
3146 compatible = "arm,armv8-timer";
3155 interrupt-parent = <&gic>;
3156 always-on;