Lines Matching +full:1 +full:e60000
22 #address-cells = <1>;
23 #size-cells = <1>;
132 snps,write-requests = <1>;
176 #dma-cells = <1>;
189 #address-cells = <1>;
190 #size-cells = <1>;
200 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
231 #dma-cells = <1>;
260 #address-cells = <1>;
261 #size-cells = <1>;
269 dmas = <&adma 1>, <&adma 1>,
590 #address-cells = <1>;
591 #size-cells = <1>;
681 #interconnect-cells = <1>;
726 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
802 #address-cells = <1>;
831 #address-cells = <1>;
849 #address-cells = <1>;
856 pinctrl-1 = <&state_dpaux1_off>;
870 #address-cells = <1>;
877 pinctrl-1 = <&state_dpaux0_off>;
891 #address-cells = <1>;
898 pinctrl-1 = <&state_dpaux2_off>;
912 #address-cells = <1>;
919 pinctrl-1 = <&state_dpaux3_off>;
932 #address-cells = <1>;
946 #address-cells = <1>;
1058 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
1060 pinctrl-1 = <&sdmmc1_1v8>;
1065 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
1066 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
1097 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
1099 pinctrl-1 = <&sdmmc3_1v8>;
1100 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
1101 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
1105 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
1106 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
1138 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
1139 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
1148 mmc-ddr-1_8v;
1149 mmc-hs200-1_8v;
1150 mmc-hs400-1_8v;
1199 usb2-1 {
1227 usb3-1 {
1253 usb2-1 {
1269 usb3-1 {
1427 p2u_hsio_5: phy@3e60000 {
1586 #address-cells = <1>;
1603 #address-cells = <1>;
1693 sdmmc1_1v8: sdmmc1-1v8 {
1702 sdmmc3_1v8: sdmmc3-1v8 {
1797 #global-interrupts = <1>;
1798 #iommu-cells = <1>;
1876 #iommu-cells = <1>;
1895 #address-cells = <1>;
1896 #size-cells = <1>;
1904 iommu-map = <0 &smmu TEGRA194_SID_HOST1X_CTX0 1>,
1905 <1 &smmu TEGRA194_SID_HOST1X_CTX1 1>,
1906 <2 &smmu TEGRA194_SID_HOST1X_CTX2 1>,
1907 <3 &smmu TEGRA194_SID_HOST1X_CTX3 1>,
1908 <4 &smmu TEGRA194_SID_HOST1X_CTX4 1>,
1909 <5 &smmu TEGRA194_SID_HOST1X_CTX5 1>,
1910 <6 &smmu TEGRA194_SID_HOST1X_CTX6 1>,
1911 <7 &smmu TEGRA194_SID_HOST1X_CTX7 1>;
1925 interconnect-names = "dma-mem", "read-1", "write";
1951 #address-cells = <1>;
1952 #size-cells = <1>;
1968 interconnect-names = "dma-mem", "read-1";
1986 interconnect-names = "dma-mem", "read-1";
1989 nvidia,head = <1>;
2004 interconnect-names = "dma-mem", "read-1";
2022 interconnect-names = "dma-mem", "read-1";
2074 interconnect-names = "dma-mem", "read-1", "write";
2093 interconnect-names = "dma-mem", "read-1", "write";
2129 #address-cells = <1>;
2163 #address-cells = <1>;
2197 #address-cells = <1>;
2231 #address-cells = <1>;
2248 interconnect-names = "dma-mem", "read-1", "write";
2270 pinctrl-1 = <&state_dpaux0_i2c>;
2294 pinctrl-1 = <&state_dpaux1_i2c>;
2300 nvidia,interface = <1>;
2318 pinctrl-1 = <&state_dpaux2_i2c>;
2342 pinctrl-1 = <&state_dpaux3_i2c>;
2381 "read-1", "read-1-hp", "write-1",
2401 num-lanes = <1>;
2402 linux,pci-domain = <1>;
2415 #interrupt-cells = <1>;
2419 nvidia,bpmp = <&bpmp 1>;
2453 num-lanes = <1>;
2467 #interrupt-cells = <1>;
2505 num-lanes = <1>;
2519 #interrupt-cells = <1>;
2571 #interrupt-cells = <1>;
2623 #interrupt-cells = <1>;
2680 #interrupt-cells = <1>;
2825 #address-cells = <1>;
2826 #size-cells = <1>;
2848 #clock-cells = <1>;
2849 #reset-cells = <1>;
2850 #power-domain-cells = <1>;
2861 #address-cells = <1>;
2867 #thermal-sensor-cells = <1>;
2874 #address-cells = <1>;
2891 cpu0_1: cpu@1 {
3109 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>;