Lines Matching +full:tegra186 +full:- +full:bpmp
1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/memory/tegra186-mc.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8 #include <dt-bindings/power/tegra186-powergate.h>
9 #include <dt-bindings/reset/tegra186-reset.h>
10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
13 compatible = "nvidia,tegra186";
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "nvidia,tegra186-misc";
25 compatible = "nvidia,tegra186-gpio";
26 reg-names = "security", "gpio";
35 #interrupt-cells = <2>;
36 interrupt-controller;
37 #gpio-cells = <2>;
38 gpio-controller;
42 compatible = "nvidia,tegra186-eqos",
43 "snps,dwc-qos-ethernet-4.10";
55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
56 <&bpmp TEGRA186_CLK_EQOS_AXI>,
57 <&bpmp TEGRA186_CLK_EQOS_RX>,
58 <&bpmp TEGRA186_CLK_EQOS_TX>,
59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>;
60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
61 resets = <&bpmp TEGRA186_RESET_EQOS>;
62 reset-names = "eqos";
65 interconnect-names = "dma-mem", "write";
69 snps,write-requests = <1>;
70 snps,read-requests = <3>;
71 snps,burst-map = <0x7>;
76 gpcdma: dma-controller@2600000 {
77 compatible = "nvidia,tegra186-gpcdma";
79 resets = <&bpmp TEGRA186_RESET_GPCDMA>;
80 reset-names = "gpcdma";
112 #dma-cells = <1>;
114 dma-coherent;
119 compatible = "nvidia,tegra186-aconnect",
120 "nvidia,tegra210-aconnect";
121 clocks = <&bpmp TEGRA186_CLK_APE>,
122 <&bpmp TEGRA186_CLK_APB2APE>;
123 clock-names = "ape", "apb2ape";
124 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;
125 #address-cells = <1>;
126 #size-cells = <1>;
130 adma: dma-controller@2930000 {
131 compatible = "nvidia,tegra186-adma";
133 interrupt-parent = <&agic>;
166 #dma-cells = <1>;
167 clocks = <&bpmp TEGRA186_CLK_AHUB>;
168 clock-names = "d_audio";
172 agic: interrupt-controller@2a40000 {
173 compatible = "nvidia,tegra186-agic",
174 "nvidia,tegra210-agic";
175 #interrupt-cells = <3>;
176 interrupt-controller;
181 clocks = <&bpmp TEGRA186_CLK_APE>;
182 clock-names = "clk";
187 compatible = "nvidia,tegra186-ahub";
189 clocks = <&bpmp TEGRA186_CLK_AHUB>;
190 clock-names = "ahub";
191 assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>;
192 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
193 #address-cells = <1>;
194 #size-cells = <1>;
199 compatible = "nvidia,tegra186-admaif";
221 dma-names = "rx1", "tx1",
245 compatible = "nvidia,tegra186-i2s",
246 "nvidia,tegra210-i2s";
248 clocks = <&bpmp TEGRA186_CLK_I2S1>,
249 <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>;
250 clock-names = "i2s", "sync_input";
251 assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>;
252 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
253 assigned-clock-rates = <1536000>;
254 sound-name-prefix = "I2S1";
259 compatible = "nvidia,tegra186-i2s",
260 "nvidia,tegra210-i2s";
262 clocks = <&bpmp TEGRA186_CLK_I2S2>,
263 <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>;
264 clock-names = "i2s", "sync_input";
265 assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>;
266 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
267 assigned-clock-rates = <1536000>;
268 sound-name-prefix = "I2S2";
273 compatible = "nvidia,tegra186-i2s",
274 "nvidia,tegra210-i2s";
276 clocks = <&bpmp TEGRA186_CLK_I2S3>,
277 <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>;
278 clock-names = "i2s", "sync_input";
279 assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>;
280 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
281 assigned-clock-rates = <1536000>;
282 sound-name-prefix = "I2S3";
287 compatible = "nvidia,tegra186-i2s",
288 "nvidia,tegra210-i2s";
290 clocks = <&bpmp TEGRA186_CLK_I2S4>,
291 <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>;
292 clock-names = "i2s", "sync_input";
293 assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>;
294 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
295 assigned-clock-rates = <1536000>;
296 sound-name-prefix = "I2S4";
301 compatible = "nvidia,tegra186-i2s",
302 "nvidia,tegra210-i2s";
304 clocks = <&bpmp TEGRA186_CLK_I2S5>,
305 <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>;
306 clock-names = "i2s", "sync_input";
307 assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>;
308 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
309 assigned-clock-rates = <1536000>;
310 sound-name-prefix = "I2S5";
315 compatible = "nvidia,tegra186-i2s",
316 "nvidia,tegra210-i2s";
318 clocks = <&bpmp TEGRA186_CLK_I2S6>,
319 <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>;
320 clock-names = "i2s", "sync_input";
321 assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>;
322 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
323 assigned-clock-rates = <1536000>;
324 sound-name-prefix = "I2S6";
329 compatible = "nvidia,tegra210-dmic";
331 clocks = <&bpmp TEGRA186_CLK_DMIC1>;
332 clock-names = "dmic";
333 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>;
334 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
335 assigned-clock-rates = <3072000>;
336 sound-name-prefix = "DMIC1";
341 compatible = "nvidia,tegra210-dmic";
343 clocks = <&bpmp TEGRA186_CLK_DMIC2>;
344 clock-names = "dmic";
345 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>;
346 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
347 assigned-clock-rates = <3072000>;
348 sound-name-prefix = "DMIC2";
353 compatible = "nvidia,tegra210-dmic";
355 clocks = <&bpmp TEGRA186_CLK_DMIC3>;
356 clock-names = "dmic";
357 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>;
358 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
359 assigned-clock-rates = <3072000>;
360 sound-name-prefix = "DMIC3";
365 compatible = "nvidia,tegra210-dmic";
367 clocks = <&bpmp TEGRA186_CLK_DMIC4>;
368 clock-names = "dmic";
369 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>;
370 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
371 assigned-clock-rates = <3072000>;
372 sound-name-prefix = "DMIC4";
377 compatible = "nvidia,tegra186-dspk";
379 clocks = <&bpmp TEGRA186_CLK_DSPK1>;
380 clock-names = "dspk";
381 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>;
382 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
383 assigned-clock-rates = <12288000>;
384 sound-name-prefix = "DSPK1";
389 compatible = "nvidia,tegra186-dspk";
391 clocks = <&bpmp TEGRA186_CLK_DSPK2>;
392 clock-names = "dspk";
393 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>;
394 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
395 assigned-clock-rates = <12288000>;
396 sound-name-prefix = "DSPK2";
401 compatible = "nvidia,tegra186-sfc",
402 "nvidia,tegra210-sfc";
404 sound-name-prefix = "SFC1";
409 compatible = "nvidia,tegra186-sfc",
410 "nvidia,tegra210-sfc";
412 sound-name-prefix = "SFC2";
417 compatible = "nvidia,tegra186-sfc",
418 "nvidia,tegra210-sfc";
420 sound-name-prefix = "SFC3";
425 compatible = "nvidia,tegra186-sfc",
426 "nvidia,tegra210-sfc";
428 sound-name-prefix = "SFC4";
433 compatible = "nvidia,tegra186-mvc",
434 "nvidia,tegra210-mvc";
436 sound-name-prefix = "MVC1";
441 compatible = "nvidia,tegra186-mvc",
442 "nvidia,tegra210-mvc";
444 sound-name-prefix = "MVC2";
449 compatible = "nvidia,tegra186-amx",
450 "nvidia,tegra210-amx";
452 sound-name-prefix = "AMX1";
457 compatible = "nvidia,tegra186-amx",
458 "nvidia,tegra210-amx";
460 sound-name-prefix = "AMX2";
465 compatible = "nvidia,tegra186-amx",
466 "nvidia,tegra210-amx";
468 sound-name-prefix = "AMX3";
473 compatible = "nvidia,tegra186-amx",
474 "nvidia,tegra210-amx";
476 sound-name-prefix = "AMX4";
481 compatible = "nvidia,tegra186-adx",
482 "nvidia,tegra210-adx";
484 sound-name-prefix = "ADX1";
489 compatible = "nvidia,tegra186-adx",
490 "nvidia,tegra210-adx";
492 sound-name-prefix = "ADX2";
497 compatible = "nvidia,tegra186-adx",
498 "nvidia,tegra210-adx";
500 sound-name-prefix = "ADX3";
505 compatible = "nvidia,tegra186-adx",
506 "nvidia,tegra210-adx";
508 sound-name-prefix = "ADX4";
512 tegra_ope1: processing-engine@2908000 {
513 compatible = "nvidia,tegra186-ope",
514 "nvidia,tegra210-ope";
516 #address-cells = <1>;
517 #size-cells = <1>;
519 sound-name-prefix = "OPE1";
523 compatible = "nvidia,tegra186-peq",
524 "nvidia,tegra210-peq";
528 dynamic-range-compressor@2908200 {
529 compatible = "nvidia,tegra186-mbdrc",
530 "nvidia,tegra210-mbdrc";
536 compatible = "nvidia,tegra186-amixer",
537 "nvidia,tegra210-amixer";
539 sound-name-prefix = "MIXER1";
544 compatible = "nvidia,tegra186-asrc";
546 sound-name-prefix = "ASRC1";
552 mc: memory-controller@2c00000 {
553 compatible = "nvidia,tegra186-mc";
554 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */
560 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3";
564 #interconnect-cells = <1>;
565 #address-cells = <2>;
566 #size-cells = <2>;
574 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
576 emc: external-memory-controller@2c60000 {
577 compatible = "nvidia,tegra186-emc";
580 clocks = <&bpmp TEGRA186_CLK_EMC>;
581 clock-names = "emc";
583 #interconnect-cells = <0>;
585 nvidia,bpmp = <&bpmp>;
590 compatible = "nvidia,tegra186-timer";
606 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
608 reg-shift = <2>;
610 clocks = <&bpmp TEGRA186_CLK_UARTA>;
611 clock-names = "serial";
612 resets = <&bpmp TEGRA186_RESET_UARTA>;
613 reset-names = "serial";
618 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
620 reg-shift = <2>;
622 clocks = <&bpmp TEGRA186_CLK_UARTB>;
623 clock-names = "serial";
624 resets = <&bpmp TEGRA186_RESET_UARTB>;
625 reset-names = "serial";
630 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
632 reg-shift = <2>;
634 clocks = <&bpmp TEGRA186_CLK_UARTD>;
635 clock-names = "serial";
636 resets = <&bpmp TEGRA186_RESET_UARTD>;
637 reset-names = "serial";
642 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
644 reg-shift = <2>;
646 clocks = <&bpmp TEGRA186_CLK_UARTE>;
647 clock-names = "serial";
648 resets = <&bpmp TEGRA186_RESET_UARTE>;
649 reset-names = "serial";
654 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
656 reg-shift = <2>;
658 clocks = <&bpmp TEGRA186_CLK_UARTF>;
659 clock-names = "serial";
660 resets = <&bpmp TEGRA186_RESET_UARTF>;
661 reset-names = "serial";
666 compatible = "nvidia,tegra186-i2c";
669 #address-cells = <1>;
670 #size-cells = <0>;
671 clocks = <&bpmp TEGRA186_CLK_I2C1>;
672 clock-names = "div-clk";
673 resets = <&bpmp TEGRA186_RESET_I2C1>;
674 reset-names = "i2c";
676 dma-coherent;
678 dma-names = "rx", "tx";
683 compatible = "nvidia,tegra186-i2c";
686 #address-cells = <1>;
687 #size-cells = <0>;
688 clocks = <&bpmp TEGRA186_CLK_I2C3>;
689 clock-names = "div-clk";
690 resets = <&bpmp TEGRA186_RESET_I2C3>;
691 reset-names = "i2c";
693 dma-coherent;
695 dma-names = "rx", "tx";
701 compatible = "nvidia,tegra186-i2c";
704 #address-cells = <1>;
705 #size-cells = <0>;
706 clocks = <&bpmp TEGRA186_CLK_I2C4>;
707 clock-names = "div-clk";
708 resets = <&bpmp TEGRA186_RESET_I2C4>;
709 reset-names = "i2c";
710 pinctrl-names = "default", "idle";
711 pinctrl-0 = <&state_dpaux1_i2c>;
712 pinctrl-1 = <&state_dpaux1_off>;
714 dma-coherent;
716 dma-names = "rx", "tx";
720 /* controlled by BPMP, should not be enabled */
722 compatible = "nvidia,tegra186-i2c";
725 #address-cells = <1>;
726 #size-cells = <0>;
727 clocks = <&bpmp TEGRA186_CLK_I2C5>;
728 clock-names = "div-clk";
729 resets = <&bpmp TEGRA186_RESET_I2C5>;
730 reset-names = "i2c";
736 compatible = "nvidia,tegra186-i2c";
739 #address-cells = <1>;
740 #size-cells = <0>;
741 clocks = <&bpmp TEGRA186_CLK_I2C6>;
742 clock-names = "div-clk";
743 resets = <&bpmp TEGRA186_RESET_I2C6>;
744 reset-names = "i2c";
745 pinctrl-names = "default", "idle";
746 pinctrl-0 = <&state_dpaux_i2c>;
747 pinctrl-1 = <&state_dpaux_off>;
749 dma-coherent;
751 dma-names = "rx", "tx";
756 compatible = "nvidia,tegra186-i2c";
759 #address-cells = <1>;
760 #size-cells = <0>;
761 clocks = <&bpmp TEGRA186_CLK_I2C7>;
762 clock-names = "div-clk";
763 resets = <&bpmp TEGRA186_RESET_I2C7>;
764 reset-names = "i2c";
766 dma-coherent;
768 dma-names = "rx", "tx";
773 compatible = "nvidia,tegra186-i2c";
776 #address-cells = <1>;
777 #size-cells = <0>;
778 clocks = <&bpmp TEGRA186_CLK_I2C9>;
779 clock-names = "div-clk";
780 resets = <&bpmp TEGRA186_RESET_I2C9>;
781 reset-names = "i2c";
783 dma-coherent;
785 dma-names = "rx", "tx";
790 compatible = "nvidia,tegra186-pwm";
792 clocks = <&bpmp TEGRA186_CLK_PWM1>;
793 clock-names = "pwm";
794 resets = <&bpmp TEGRA186_RESET_PWM1>;
795 reset-names = "pwm";
797 #pwm-cells = <2>;
801 compatible = "nvidia,tegra186-pwm";
803 clocks = <&bpmp TEGRA186_CLK_PWM2>;
804 clock-names = "pwm";
805 resets = <&bpmp TEGRA186_RESET_PWM2>;
806 reset-names = "pwm";
808 #pwm-cells = <2>;
812 compatible = "nvidia,tegra186-pwm";
814 clocks = <&bpmp TEGRA186_CLK_PWM3>;
815 clock-names = "pwm";
816 resets = <&bpmp TEGRA186_RESET_PWM3>;
817 reset-names = "pwm";
819 #pwm-cells = <2>;
823 compatible = "nvidia,tegra186-pwm";
825 clocks = <&bpmp TEGRA186_CLK_PWM5>;
826 clock-names = "pwm";
827 resets = <&bpmp TEGRA186_RESET_PWM5>;
828 reset-names = "pwm";
830 #pwm-cells = <2>;
834 compatible = "nvidia,tegra186-pwm";
836 clocks = <&bpmp TEGRA186_CLK_PWM6>;
837 clock-names = "pwm";
838 resets = <&bpmp TEGRA186_RESET_PWM6>;
839 reset-names = "pwm";
841 #pwm-cells = <2>;
845 compatible = "nvidia,tegra186-pwm";
847 clocks = <&bpmp TEGRA186_CLK_PWM7>;
848 clock-names = "pwm";
849 resets = <&bpmp TEGRA186_RESET_PWM7>;
850 reset-names = "pwm";
852 #pwm-cells = <2>;
856 compatible = "nvidia,tegra186-pwm";
858 clocks = <&bpmp TEGRA186_CLK_PWM8>;
859 clock-names = "pwm";
860 resets = <&bpmp TEGRA186_RESET_PWM8>;
861 reset-names = "pwm";
863 #pwm-cells = <2>;
867 compatible = "nvidia,tegra186-sdhci";
870 clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
871 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
872 clock-names = "sdhci", "tmclk";
873 resets = <&bpmp TEGRA186_RESET_SDMMC1>;
874 reset-names = "sdhci";
877 interconnect-names = "dma-mem", "write";
879 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
880 pinctrl-0 = <&sdmmc1_3v3>;
881 pinctrl-1 = <&sdmmc1_1v8>;
882 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
883 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
884 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
885 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
886 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>;
887 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>;
888 nvidia,default-tap = <0x5>;
889 nvidia,default-trim = <0xb>;
890 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
891 <&bpmp TEGRA186_CLK_PLLP_OUT0>;
892 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
897 compatible = "nvidia,tegra186-sdhci";
900 clocks = <&bpmp TEGRA186_CLK_SDMMC2>,
901 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
902 clock-names = "sdhci", "tmclk";
903 resets = <&bpmp TEGRA186_RESET_SDMMC2>;
904 reset-names = "sdhci";
907 interconnect-names = "dma-mem", "write";
909 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
910 pinctrl-0 = <&sdmmc2_3v3>;
911 pinctrl-1 = <&sdmmc2_1v8>;
912 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
913 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
914 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
915 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
916 nvidia,default-tap = <0x5>;
917 nvidia,default-trim = <0xb>;
922 compatible = "nvidia,tegra186-sdhci";
925 clocks = <&bpmp TEGRA186_CLK_SDMMC3>,
926 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
927 clock-names = "sdhci", "tmclk";
928 resets = <&bpmp TEGRA186_RESET_SDMMC3>;
929 reset-names = "sdhci";
932 interconnect-names = "dma-mem", "write";
934 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
935 pinctrl-0 = <&sdmmc3_3v3>;
936 pinctrl-1 = <&sdmmc3_1v8>;
937 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
938 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
939 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
940 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
941 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
942 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
943 nvidia,default-tap = <0x5>;
944 nvidia,default-trim = <0xb>;
949 compatible = "nvidia,tegra186-sdhci";
952 clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
953 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
954 clock-names = "sdhci", "tmclk";
955 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
956 <&bpmp TEGRA186_CLK_PLLC4_VCO>;
957 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>;
958 resets = <&bpmp TEGRA186_RESET_SDMMC4>;
959 reset-names = "sdhci";
962 interconnect-names = "dma-mem", "write";
964 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>;
965 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>;
966 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
967 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
968 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
969 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
970 nvidia,default-tap = <0x9>;
971 nvidia,default-trim = <0x5>;
972 nvidia,dqs-trim = <63>;
973 mmc-hs400-1_8v;
974 supports-cqe;
979 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda";
982 clocks = <&bpmp TEGRA186_CLK_HDA>,
983 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>,
984 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>;
985 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
986 resets = <&bpmp TEGRA186_RESET_HDA>,
987 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>,
988 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>;
989 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
990 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
993 interconnect-names = "dma-mem", "write";
999 compatible = "nvidia,tegra186-xusb-padctl";
1002 reg-names = "padctl", "ao";
1005 resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>;
1006 reset-names = "padctl";
1012 clocks = <&bpmp TEGRA186_CLK_USB2_TRK>;
1013 clock-names = "trk";
1017 usb2-0 {
1019 #phy-cells = <0>;
1022 usb2-1 {
1024 #phy-cells = <0>;
1027 usb2-2 {
1029 #phy-cells = <0>;
1035 clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>;
1036 clock-names = "trk";
1040 hsic-0 {
1042 #phy-cells = <0>;
1051 usb3-0 {
1053 #phy-cells = <0>;
1056 usb3-1 {
1058 #phy-cells = <0>;
1061 usb3-2 {
1063 #phy-cells = <0>;
1070 usb2-0 {
1074 usb2-1 {
1078 usb2-2 {
1082 hsic-0 {
1086 usb3-0 {
1090 usb3-1 {
1094 usb3-2 {
1101 compatible = "nvidia,tegra186-xusb";
1104 reg-names = "hcd", "fpci";
1107 clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>,
1108 <&bpmp TEGRA186_CLK_XUSB_FALCON>,
1109 <&bpmp TEGRA186_CLK_XUSB_SS>,
1110 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
1111 <&bpmp TEGRA186_CLK_CLK_M>,
1112 <&bpmp TEGRA186_CLK_XUSB_FS>,
1113 <&bpmp TEGRA186_CLK_PLLU>,
1114 <&bpmp TEGRA186_CLK_CLK_M>,
1115 <&bpmp TEGRA186_CLK_PLLE>;
1116 clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss",
1119 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>,
1120 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
1121 power-domain-names = "xusb_host", "xusb_ss";
1124 interconnect-names = "dma-mem", "write";
1126 #address-cells = <1>;
1127 #size-cells = <0>;
1130 nvidia,xusb-padctl = <&padctl>;
1134 compatible = "nvidia,tegra186-xudc";
1137 reg-names = "base", "fpci";
1139 clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>,
1140 <&bpmp TEGRA186_CLK_XUSB_SS>,
1141 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
1142 <&bpmp TEGRA186_CLK_XUSB_FS>;
1143 clock-names = "dev", "ss", "ss_src", "fs_src";
1146 interconnect-names = "dma-mem", "write";
1148 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>,
1149 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
1150 power-domain-names = "dev", "ss";
1151 nvidia,xusb-padctl = <&padctl>;
1156 compatible = "nvidia,tegra186-efuse";
1158 clocks = <&bpmp TEGRA186_CLK_FUSE>;
1159 clock-names = "fuse";
1162 gic: interrupt-controller@3881000 {
1163 compatible = "arm,gic-400";
1164 #interrupt-cells = <3>;
1165 interrupt-controller;
1172 interrupt-parent = <&gic>;
1176 compatible = "nvidia,tegra186-cec";
1179 clocks = <&bpmp TEGRA186_CLK_CEC>;
1180 clock-names = "cec";
1185 compatible = "nvidia,tegra186-hsp";
1188 interrupt-names = "doorbell";
1189 #mbox-cells = <2>;
1194 compatible = "nvidia,tegra186-i2c";
1197 #address-cells = <1>;
1198 #size-cells = <0>;
1199 clocks = <&bpmp TEGRA186_CLK_I2C2>;
1200 clock-names = "div-clk";
1201 resets = <&bpmp TEGRA186_RESET_I2C2>;
1202 reset-names = "i2c";
1204 dma-coherent;
1206 dma-names = "rx", "tx";
1211 compatible = "nvidia,tegra186-i2c";
1214 #address-cells = <1>;
1215 #size-cells = <0>;
1216 clocks = <&bpmp TEGRA186_CLK_I2C8>;
1217 clock-names = "div-clk";
1218 resets = <&bpmp TEGRA186_RESET_I2C8>;
1219 reset-names = "i2c";
1221 dma-coherent;
1223 dma-names = "rx", "tx";
1228 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
1230 reg-shift = <2>;
1232 clocks = <&bpmp TEGRA186_CLK_UARTC>;
1233 clock-names = "serial";
1234 resets = <&bpmp TEGRA186_RESET_UARTC>;
1235 reset-names = "serial";
1240 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
1242 reg-shift = <2>;
1244 clocks = <&bpmp TEGRA186_CLK_UARTG>;
1245 clock-names = "serial";
1246 resets = <&bpmp TEGRA186_RESET_UARTG>;
1247 reset-names = "serial";
1252 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc";
1254 interrupt-parent = <&pmc>;
1256 clocks = <&bpmp TEGRA186_CLK_CLK_32K>;
1257 clock-names = "rtc";
1262 compatible = "nvidia,tegra186-gpio-aon";
1263 reg-names = "security", "gpio";
1267 gpio-controller;
1268 #gpio-cells = <2>;
1269 interrupt-controller;
1270 #interrupt-cells = <2>;
1274 compatible = "nvidia,tegra186-pwm";
1276 clocks = <&bpmp TEGRA186_CLK_PWM4>;
1277 clock-names = "pwm";
1278 resets = <&bpmp TEGRA186_RESET_PWM4>;
1279 reset-names = "pwm";
1281 #pwm-cells = <2>;
1285 compatible = "nvidia,tegra186-pmc";
1290 reg-names = "pmc", "wake", "aotag", "scratch";
1292 #interrupt-cells = <2>;
1293 interrupt-controller;
1295 sdmmc1_3v3: sdmmc1-3v3 {
1296 pins = "sdmmc1-hv";
1297 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1300 sdmmc1_1v8: sdmmc1-1v8 {
1301 pins = "sdmmc1-hv";
1302 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1305 sdmmc2_3v3: sdmmc2-3v3 {
1306 pins = "sdmmc2-hv";
1307 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1310 sdmmc2_1v8: sdmmc2-1v8 {
1311 pins = "sdmmc2-hv";
1312 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1315 sdmmc3_3v3: sdmmc3-3v3 {
1316 pins = "sdmmc3-hv";
1317 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1320 sdmmc3_1v8: sdmmc3-1v8 {
1321 pins = "sdmmc3-hv";
1322 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1327 compatible = "nvidia,tegra186-ccplex-cluster";
1330 nvidia,bpmp = <&bpmp>;
1334 compatible = "nvidia,tegra186-pcie";
1335 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
1340 reg-names = "pads", "afi", "cs";
1344 interrupt-names = "intr", "msi";
1346 #interrupt-cells = <1>;
1347 interrupt-map-mask = <0 0 0 0>;
1348 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1350 bus-range = <0x00 0xff>;
1351 #address-cells = <3>;
1352 #size-cells = <2>;
1358 <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */
1361 clocks = <&bpmp TEGRA186_CLK_PCIE>,
1362 <&bpmp TEGRA186_CLK_AFI>,
1363 <&bpmp TEGRA186_CLK_PLLE>;
1364 clock-names = "pex", "afi", "pll_e";
1366 resets = <&bpmp TEGRA186_RESET_PCIE>,
1367 <&bpmp TEGRA186_RESET_AFI>,
1368 <&bpmp TEGRA186_RESET_PCIEXCLK>;
1369 reset-names = "pex", "afi", "pcie_x";
1373 interconnect-names = "dma-mem", "write";
1376 iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>;
1377 iommu-map-mask = <0x0>;
1383 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
1387 #address-cells = <3>;
1388 #size-cells = <2>;
1391 nvidia,num-lanes = <2>;
1396 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
1400 #address-cells = <3>;
1401 #size-cells = <2>;
1404 nvidia,num-lanes = <1>;
1409 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
1413 #address-cells = <3>;
1414 #size-cells = <2>;
1417 nvidia,num-lanes = <1>;
1422 compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500";
1489 stream-match-mask = <0x7f80>;
1490 #global-interrupts = <1>;
1491 #iommu-cells = <1>;
1493 nvidia,memory-controller = <&mc>;
1497 compatible = "nvidia,tegra186-host1x";
1500 reg-names = "hypervisor", "vm";
1503 interrupt-names = "syncpt", "host1x";
1504 clocks = <&bpmp TEGRA186_CLK_HOST1X>;
1505 clock-names = "host1x";
1506 resets = <&bpmp TEGRA186_RESET_HOST1X>;
1507 reset-names = "host1x";
1509 #address-cells = <1>;
1510 #size-cells = <1>;
1515 interconnect-names = "dma-mem";
1520 iommu-map = <0 &smmu TEGRA186_SID_HOST1X_CTX0 1>,
1530 compatible = "nvidia,tegra186-dpaux";
1533 clocks = <&bpmp TEGRA186_CLK_DPAUX1>,
1534 <&bpmp TEGRA186_CLK_PLLDP>;
1535 clock-names = "dpaux", "parent";
1536 resets = <&bpmp TEGRA186_RESET_DPAUX1>;
1537 reset-names = "dpaux";
1540 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1542 state_dpaux1_aux: pinmux-aux {
1543 groups = "dpaux-io";
1547 state_dpaux1_i2c: pinmux-i2c {
1548 groups = "dpaux-io";
1552 state_dpaux1_off: pinmux-off {
1553 groups = "dpaux-io";
1557 i2c-bus {
1558 #address-cells = <1>;
1559 #size-cells = <0>;
1563 display-hub@15200000 {
1564 compatible = "nvidia,tegra186-display";
1566 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
1567 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
1568 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
1569 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>,
1570 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>,
1571 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>,
1572 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>;
1573 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
1575 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>,
1576 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,
1577 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>;
1578 clock-names = "disp", "dsc", "hub";
1581 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1583 #address-cells = <1>;
1584 #size-cells = <1>;
1589 compatible = "nvidia,tegra186-dc";
1592 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;
1593 clock-names = "dc";
1594 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>;
1595 reset-names = "dc";
1597 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1600 interconnect-names = "dma-mem", "read-1";
1608 compatible = "nvidia,tegra186-dc";
1611 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;
1612 clock-names = "dc";
1613 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>;
1614 reset-names = "dc";
1616 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
1619 interconnect-names = "dma-mem", "read-1";
1627 compatible = "nvidia,tegra186-dc";
1630 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;
1631 clock-names = "dc";
1632 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>;
1633 reset-names = "dc";
1635 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
1638 interconnect-names = "dma-mem", "read-1";
1647 compatible = "nvidia,tegra186-dsi";
1650 clocks = <&bpmp TEGRA186_CLK_DSI>,
1651 <&bpmp TEGRA186_CLK_DSIA_LP>,
1652 <&bpmp TEGRA186_CLK_PLLD>;
1653 clock-names = "dsi", "lp", "parent";
1654 resets = <&bpmp TEGRA186_RESET_DSI>;
1655 reset-names = "dsi";
1658 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1662 compatible = "nvidia,tegra186-vic";
1665 clocks = <&bpmp TEGRA186_CLK_VIC>;
1666 clock-names = "vic";
1667 resets = <&bpmp TEGRA186_RESET_VIC>;
1668 reset-names = "vic";
1670 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;
1673 interconnect-names = "dma-mem", "write";
1678 compatible = "nvidia,tegra186-nvjpg";
1680 clocks = <&bpmp TEGRA186_CLK_NVJPG>;
1681 clock-names = "nvjpg";
1682 resets = <&bpmp TEGRA186_RESET_NVJPG>;
1683 reset-names = "nvjpg";
1685 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>;
1688 interconnect-names = "dma-mem", "write";
1693 compatible = "nvidia,tegra186-dsi";
1696 clocks = <&bpmp TEGRA186_CLK_DSIB>,
1697 <&bpmp TEGRA186_CLK_DSIB_LP>,
1698 <&bpmp TEGRA186_CLK_PLLD>;
1699 clock-names = "dsi", "lp", "parent";
1700 resets = <&bpmp TEGRA186_RESET_DSIB>;
1701 reset-names = "dsi";
1704 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1708 compatible = "nvidia,tegra186-nvdec";
1710 clocks = <&bpmp TEGRA186_CLK_NVDEC>;
1711 clock-names = "nvdec";
1712 resets = <&bpmp TEGRA186_RESET_NVDEC>;
1713 reset-names = "nvdec";
1715 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>;
1719 interconnect-names = "dma-mem", "read-1", "write";
1724 compatible = "nvidia,tegra186-nvenc";
1726 clocks = <&bpmp TEGRA186_CLK_NVENC>;
1727 clock-names = "nvenc";
1728 resets = <&bpmp TEGRA186_RESET_NVENC>;
1729 reset-names = "nvenc";
1731 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>;
1734 interconnect-names = "dma-mem", "write";
1739 compatible = "nvidia,tegra186-sor";
1742 clocks = <&bpmp TEGRA186_CLK_SOR0>,
1743 <&bpmp TEGRA186_CLK_SOR0_OUT>,
1744 <&bpmp TEGRA186_CLK_PLLD2>,
1745 <&bpmp TEGRA186_CLK_PLLDP>,
1746 <&bpmp TEGRA186_CLK_SOR_SAFE>,
1747 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>;
1748 clock-names = "sor", "out", "parent", "dp", "safe",
1750 resets = <&bpmp TEGRA186_RESET_SOR0>;
1751 reset-names = "sor";
1752 pinctrl-0 = <&state_dpaux_aux>;
1753 pinctrl-1 = <&state_dpaux_i2c>;
1754 pinctrl-2 = <&state_dpaux_off>;
1755 pinctrl-names = "aux", "i2c", "off";
1758 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1763 compatible = "nvidia,tegra186-sor";
1766 clocks = <&bpmp TEGRA186_CLK_SOR1>,
1767 <&bpmp TEGRA186_CLK_SOR1_OUT>,
1768 <&bpmp TEGRA186_CLK_PLLD3>,
1769 <&bpmp TEGRA186_CLK_PLLDP>,
1770 <&bpmp TEGRA186_CLK_SOR_SAFE>,
1771 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>;
1772 clock-names = "sor", "out", "parent", "dp", "safe",
1774 resets = <&bpmp TEGRA186_RESET_SOR1>;
1775 reset-names = "sor";
1776 pinctrl-0 = <&state_dpaux1_aux>;
1777 pinctrl-1 = <&state_dpaux1_i2c>;
1778 pinctrl-2 = <&state_dpaux1_off>;
1779 pinctrl-names = "aux", "i2c", "off";
1782 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1787 compatible = "nvidia,tegra186-dpaux";
1790 clocks = <&bpmp TEGRA186_CLK_DPAUX>,
1791 <&bpmp TEGRA186_CLK_PLLDP>;
1792 clock-names = "dpaux", "parent";
1793 resets = <&bpmp TEGRA186_RESET_DPAUX>;
1794 reset-names = "dpaux";
1797 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1799 state_dpaux_aux: pinmux-aux {
1800 groups = "dpaux-io";
1804 state_dpaux_i2c: pinmux-i2c {
1805 groups = "dpaux-io";
1809 state_dpaux_off: pinmux-off {
1810 groups = "dpaux-io";
1814 i2c-bus {
1815 #address-cells = <1>;
1816 #size-cells = <0>;
1821 compatible = "nvidia,tegra186-dsi-padctl";
1823 resets = <&bpmp TEGRA186_RESET_DSI>;
1824 reset-names = "dsi";
1829 compatible = "nvidia,tegra186-dsi";
1832 clocks = <&bpmp TEGRA186_CLK_DSIC>,
1833 <&bpmp TEGRA186_CLK_DSIC_LP>,
1834 <&bpmp TEGRA186_CLK_PLLD>;
1835 clock-names = "dsi", "lp", "parent";
1836 resets = <&bpmp TEGRA186_RESET_DSIC>;
1837 reset-names = "dsi";
1840 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1844 compatible = "nvidia,tegra186-dsi";
1847 clocks = <&bpmp TEGRA186_CLK_DSID>,
1848 <&bpmp TEGRA186_CLK_DSID_LP>,
1849 <&bpmp TEGRA186_CLK_PLLD>;
1850 clock-names = "dsi", "lp", "parent";
1851 resets = <&bpmp TEGRA186_RESET_DSID>;
1852 reset-names = "dsi";
1855 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1865 interrupt-names = "stall", "nonstall";
1867 clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
1868 <&bpmp TEGRA186_CLK_GPU>;
1869 clock-names = "gpu", "pwr";
1870 resets = <&bpmp TEGRA186_RESET_GPU>;
1871 reset-names = "gpu";
1874 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
1879 interconnect-names = "dma-mem", "write-0", "read-1", "write-1";
1883 compatible = "nvidia,tegra186-sysram", "mmio-sram";
1885 #address-cells = <1>;
1886 #size-cells = <1>;
1888 no-memory-wc;
1892 label = "cpu-bpmp-tx";
1898 label = "cpu-bpmp-rx";
1904 compatible = "nvidia,tegra186-ahci";
1910 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>;
1913 interconnect-names = "dma-mem", "write";
1916 clocks = <&bpmp TEGRA186_CLK_SATA>,
1917 <&bpmp TEGRA186_CLK_SATA_OOB>;
1918 clock-names = "sata", "sata-oob";
1919 assigned-clocks = <&bpmp TEGRA186_CLK_SATA>,
1920 <&bpmp TEGRA186_CLK_SATA_OOB>;
1921 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>,
1922 <&bpmp TEGRA186_CLK_PLLP>;
1923 assigned-clock-rates = <102000000>,
1925 resets = <&bpmp TEGRA186_RESET_SATA>,
1926 <&bpmp TEGRA186_RESET_SATACOLD>;
1927 reset-names = "sata", "sata-cold";
1931 bpmp: bpmp { label
1932 compatible = "nvidia,tegra186-bpmp";
1937 interconnect-names = "read", "write", "dma-mem", "dma-write";
1942 #clock-cells = <1>;
1943 #reset-cells = <1>;
1944 #power-domain-cells = <1>;
1947 compatible = "nvidia,tegra186-bpmp-i2c";
1948 nvidia,bpmp-bus-id = <5>;
1949 #address-cells = <1>;
1950 #size-cells = <0>;
1955 compatible = "nvidia,tegra186-bpmp-thermal";
1956 #thermal-sensor-cells = <1>;
1961 #address-cells = <1>;
1962 #size-cells = <0>;
1965 compatible = "nvidia,tegra186-denver";
1967 i-cache-size = <0x20000>;
1968 i-cache-line-size = <64>;
1969 i-cache-sets = <512>;
1970 d-cache-size = <0x10000>;
1971 d-cache-line-size = <64>;
1972 d-cache-sets = <256>;
1973 next-level-cache = <&L2_DENVER>;
1978 compatible = "nvidia,tegra186-denver";
1980 i-cache-size = <0x20000>;
1981 i-cache-line-size = <64>;
1982 i-cache-sets = <512>;
1983 d-cache-size = <0x10000>;
1984 d-cache-line-size = <64>;
1985 d-cache-sets = <256>;
1986 next-level-cache = <&L2_DENVER>;
1991 compatible = "arm,cortex-a57";
1993 i-cache-size = <0xC000>;
1994 i-cache-line-size = <64>;
1995 i-cache-sets = <256>;
1996 d-cache-size = <0x8000>;
1997 d-cache-line-size = <64>;
1998 d-cache-sets = <256>;
1999 next-level-cache = <&L2_A57>;
2004 compatible = "arm,cortex-a57";
2006 i-cache-size = <0xC000>;
2007 i-cache-line-size = <64>;
2008 i-cache-sets = <256>;
2009 d-cache-size = <0x8000>;
2010 d-cache-line-size = <64>;
2011 d-cache-sets = <256>;
2012 next-level-cache = <&L2_A57>;
2017 compatible = "arm,cortex-a57";
2019 i-cache-size = <0xC000>;
2020 i-cache-line-size = <64>;
2021 i-cache-sets = <256>;
2022 d-cache-size = <0x8000>;
2023 d-cache-line-size = <64>;
2024 d-cache-sets = <256>;
2025 next-level-cache = <&L2_A57>;
2030 compatible = "arm,cortex-a57";
2032 i-cache-size = <0xC000>;
2033 i-cache-line-size = <64>;
2034 i-cache-sets = <256>;
2035 d-cache-size = <0x8000>;
2036 d-cache-line-size = <64>;
2037 d-cache-sets = <256>;
2038 next-level-cache = <&L2_A57>;
2042 L2_DENVER: l2-cache0 {
2044 cache-unified;
2045 cache-level = <2>;
2046 cache-size = <0x200000>;
2047 cache-line-size = <64>;
2048 cache-sets = <2048>;
2051 L2_A57: l2-cache1 {
2053 cache-unified;
2054 cache-level = <2>;
2055 cache-size = <0x200000>;
2056 cache-line-size = <64>;
2057 cache-sets = <2048>;
2062 compatible = "nvidia,denver-pmu";
2065 interrupt-affinity = <&denver_0 &denver_1>;
2069 compatible = "arm,cortex-a57-pmu";
2074 interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>;
2080 clocks = <&bpmp TEGRA186_CLK_PLLA>,
2081 <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
2082 clock-names = "pll_a", "plla_out0";
2083 assigned-clocks = <&bpmp TEGRA186_CLK_PLLA>,
2084 <&bpmp TEGRA186_CLK_PLL_A_OUT0>,
2085 <&bpmp TEGRA186_CLK_AUD_MCLK>;
2086 assigned-clock-parents = <0>,
2087 <&bpmp TEGRA186_CLK_PLLA>,
2088 <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
2094 assigned-clock-rates = <258000000>;
2099 thermal-zones {
2100 /* Cortex-A57 cluster */
2101 cpu-thermal {
2102 polling-delay = <0>;
2103 polling-delay-passive = <1000>;
2105 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>;
2115 cooling-maps {
2120 aux-thermal {
2121 polling-delay = <0>;
2122 polling-delay-passive = <1000>;
2124 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>;
2134 cooling-maps {
2138 gpu-thermal {
2139 polling-delay = <0>;
2140 polling-delay-passive = <1000>;
2142 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>;
2152 cooling-maps {
2156 pll-thermal {
2157 polling-delay = <0>;
2158 polling-delay-passive = <1000>;
2160 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>;
2170 cooling-maps {
2174 ao-thermal {
2175 polling-delay = <0>;
2176 polling-delay-passive = <1000>;
2178 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>;
2188 cooling-maps {
2194 compatible = "arm,armv8-timer";
2203 interrupt-parent = <&gic>;
2204 always-on;