Lines Matching +full:0 +full:xc2f1000
20 reg = <0x0 0x00100000 0x0 0xf000>,
21 <0x0 0x0010f000 0x0 0x1000>;
27 reg = <0x0 0x2200000 0x0 0x10000>,
28 <0x0 0x2210000 0x0 0x10000>;
44 reg = <0x0 0x02490000 0x0 0x10000>;
71 snps,burst-map = <0x7>;
78 reg = <0x0 0x2600000 0x0 0x210000>;
127 ranges = <0x02900000 0x0 0x02900000 0x200000>;
132 reg = <0x02930000 0x20000>;
134 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
177 reg = <0x02a41000 0x1000>,
178 <0x02a42000 0x2000>;
188 reg = <0x02900800 0x800>;
195 ranges = <0x02900800 0x02900800 0x11800>;
200 reg = <0x0290f000 0x1000>;
247 reg = <0x2901000 0x100>;
261 reg = <0x2901100 0x100>;
275 reg = <0x2901200 0x100>;
289 reg = <0x2901300 0x100>;
303 reg = <0x2901400 0x100>;
317 reg = <0x2901500 0x100>;
330 reg = <0x2904000 0x100>;
342 reg = <0x2904100 0x100>;
354 reg = <0x2904200 0x100>;
366 reg = <0x2904300 0x100>;
378 reg = <0x2905000 0x100>;
390 reg = <0x2905100 0x100>;
403 reg = <0x2902000 0x200>;
411 reg = <0x2902200 0x200>;
419 reg = <0x2902400 0x200>;
427 reg = <0x2902600 0x200>;
435 reg = <0x290a000 0x200>;
443 reg = <0x290a200 0x200>;
451 reg = <0x2903000 0x100>;
459 reg = <0x2903100 0x100>;
467 reg = <0x2903200 0x100>;
475 reg = <0x2903300 0x100>;
483 reg = <0x2903800 0x100>;
491 reg = <0x2903900 0x100>;
499 reg = <0x2903a00 0x100>;
507 reg = <0x2903b00 0x100>;
515 reg = <0x2908000 0x100>;
525 reg = <0x2908100 0x100>;
531 reg = <0x2908200 0x200>;
538 reg = <0x290bb00 0x800>;
545 reg = <0x2910000 0x2000>;
554 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */
555 <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */
556 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */
557 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */
558 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */
559 <0x0 0x02c50000 0x0 0x10000>; /* MC3 */
568 ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>;
574 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
578 reg = <0x0 0x02c60000 0x0 0x50000>;
583 #interconnect-cells = <0>;
591 reg = <0x0 0x03010000 0x0 0x000e0000>;
592 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
607 reg = <0x0 0x03100000 0x0 0x40>;
619 reg = <0x0 0x03110000 0x0 0x40>;
631 reg = <0x0 0x03130000 0x0 0x40>;
643 reg = <0x0 0x03140000 0x0 0x40>;
655 reg = <0x0 0x03150000 0x0 0x40>;
667 reg = <0x0 0x03160000 0x0 0x10000>;
670 #size-cells = <0>;
684 reg = <0x0 0x03180000 0x0 0x10000>;
687 #size-cells = <0>;
702 reg = <0x0 0x03190000 0x0 0x10000>;
705 #size-cells = <0>;
711 pinctrl-0 = <&state_dpaux1_i2c>;
723 reg = <0x0 0x031a0000 0x0 0x10000>;
726 #size-cells = <0>;
737 reg = <0x0 0x031b0000 0x0 0x10000>;
740 #size-cells = <0>;
746 pinctrl-0 = <&state_dpaux_i2c>;
757 reg = <0x0 0x031c0000 0x0 0x10000>;
760 #size-cells = <0>;
774 reg = <0x0 0x031e0000 0x0 0x10000>;
777 #size-cells = <0>;
791 reg = <0x0 0x3280000 0x0 0x10000>;
802 reg = <0x0 0x3290000 0x0 0x10000>;
813 reg = <0x0 0x32a0000 0x0 0x10000>;
824 reg = <0x0 0x32c0000 0x0 0x10000>;
835 reg = <0x0 0x32d0000 0x0 0x10000>;
846 reg = <0x0 0x32e0000 0x0 0x10000>;
857 reg = <0x0 0x32f0000 0x0 0x10000>;
868 reg = <0x0 0x03400000 0x0 0x10000>;
880 pinctrl-0 = <&sdmmc1_3v3>;
882 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
883 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
884 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
885 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
886 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>;
887 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>;
888 nvidia,default-tap = <0x5>;
889 nvidia,default-trim = <0xb>;
898 reg = <0x0 0x03420000 0x0 0x10000>;
910 pinctrl-0 = <&sdmmc2_3v3>;
912 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
913 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
914 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
915 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
916 nvidia,default-tap = <0x5>;
917 nvidia,default-trim = <0xb>;
923 reg = <0x0 0x03440000 0x0 0x10000>;
935 pinctrl-0 = <&sdmmc3_3v3>;
937 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
938 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
939 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
940 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
941 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
942 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
943 nvidia,default-tap = <0x5>;
944 nvidia,default-trim = <0xb>;
950 reg = <0x0 0x03460000 0x0 0x10000>;
964 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>;
965 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>;
966 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
967 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
968 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
969 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
970 nvidia,default-tap = <0x9>;
971 nvidia,default-trim = <0x5>;
980 reg = <0x0 0x03510000 0x0 0x10000>;
1000 reg = <0x0 0x03520000 0x0 0x1000>,
1001 <0x0 0x03540000 0x0 0x1000>;
1017 usb2-0 {
1019 #phy-cells = <0>;
1024 #phy-cells = <0>;
1029 #phy-cells = <0>;
1040 hsic-0 {
1042 #phy-cells = <0>;
1051 usb3-0 {
1053 #phy-cells = <0>;
1058 #phy-cells = <0>;
1063 #phy-cells = <0>;
1070 usb2-0 {
1082 hsic-0 {
1086 usb3-0 {
1102 reg = <0x0 0x03530000 0x0 0x8000>,
1103 <0x0 0x03538000 0x0 0x1000>;
1127 #size-cells = <0>;
1135 reg = <0x0 0x03550000 0x0 0x8000>,
1136 <0x0 0x03558000 0x0 0x1000>;
1157 reg = <0x0 0x03820000 0x0 0x10000>;
1166 reg = <0x0 0x03881000 0x0 0x1000>,
1167 <0x0 0x03882000 0x0 0x2000>,
1168 <0x0 0x03884000 0x0 0x2000>,
1169 <0x0 0x03886000 0x0 0x2000>;
1177 reg = <0x0 0x03960000 0x0 0x10000>;
1186 reg = <0x0 0x03c00000 0x0 0xa0000>;
1195 reg = <0x0 0x0c240000 0x0 0x10000>;
1198 #size-cells = <0>;
1212 reg = <0x0 0x0c250000 0x0 0x10000>;
1215 #size-cells = <0>;
1222 dmas = <&gpcdma 0>, <&gpcdma 0>;
1229 reg = <0x0 0x0c280000 0x0 0x40>;
1241 reg = <0x0 0x0c290000 0x0 0x40>;
1253 reg = <0 0x0c2a0000 0 0x10000>;
1264 reg = <0x0 0xc2f0000 0x0 0x1000>,
1265 <0x0 0xc2f1000 0x0 0x1000>;
1275 reg = <0x0 0xc340000 0x0 0x10000>;
1286 reg = <0 0x0c360000 0 0x10000>,
1287 <0 0x0c370000 0 0x10000>,
1288 <0 0x0c380000 0 0x10000>,
1289 <0 0x0c390000 0 0x10000>;
1328 reg = <0x0 0x0e000000 0x0 0x400000>;
1337 reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */
1338 <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */
1339 <0x0 0x40000000 0x0 0x10000000>; /* configuration space */
1347 interrupt-map-mask = <0 0 0 0>;
1348 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1350 bus-range = <0x00 0xff>;
1354 ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */
1355 <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */
1356 <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */
1357 <0x01000000 0 0x0 0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */
1358 <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */
1359 <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
1376 iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>;
1377 iommu-map-mask = <0x0>;
1381 pci@1,0 {
1383 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
1384 reg = <0x000800 0 0 0 0>;
1394 pci@2,0 {
1396 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
1397 reg = <0x001000 0 0 0 0>;
1407 pci@3,0 {
1409 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
1410 reg = <0x001800 0 0 0 0>;
1423 reg = <0 0x12000000 0 0x800000>;
1489 stream-match-mask = <0x7f80>;
1498 reg = <0x0 0x13e00000 0x0 0x10000>,
1499 <0x0 0x13e10000 0x0 0x10000>;
1512 ranges = <0x15000000 0x0 0x15000000 0x01000000>;
1520 iommu-map = <0 &smmu TEGRA186_SID_HOST1X_CTX0 1>,
1531 reg = <0x15040000 0x10000>;
1559 #size-cells = <0>;
1565 reg = <0x15200000 0x00040000>;
1586 ranges = <0x15200000 0x15200000 0x40000>;
1590 reg = <0x15200000 0x10000>;
1604 nvidia,head = <0>;
1609 reg = <0x15210000 0x10000>;
1628 reg = <0x15220000 0x10000>;
1648 reg = <0x15300000 0x10000>;
1663 reg = <0x15340000 0x40000>;
1679 reg = <0x15380000 0x40000>;
1694 reg = <0x15400000 0x10000>;
1709 reg = <0x15480000 0x40000>;
1725 reg = <0x154c0000 0x40000>;
1740 reg = <0x15540000 0x10000>;
1752 pinctrl-0 = <&state_dpaux_aux>;
1759 nvidia,interface = <0>;
1764 reg = <0x15580000 0x10000>;
1776 pinctrl-0 = <&state_dpaux1_aux>;
1788 reg = <0x155c0000 0x10000>;
1816 #size-cells = <0>;
1822 reg = <0x15880000 0x10000>;
1830 reg = <0x15900000 0x10000>;
1845 reg = <0x15940000 0x10000>;
1861 reg = <0x0 0x17000000 0x0 0x1000000>,
1862 <0x0 0x18000000 0x0 0x1000000>;
1879 interconnect-names = "dma-mem", "write-0", "read-1", "write-1";
1884 reg = <0x0 0x30000000 0x0 0x50000>;
1887 ranges = <0x0 0x0 0x30000000 0x50000>;
1891 reg = <0x4e000 0x1000>;
1897 reg = <0x4f000 0x1000>;
1905 reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */
1906 <0x0 0x03500000 0x0 0x00007000>, /* SATA */
1907 <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */
1950 #size-cells = <0>;
1962 #size-cells = <0>;
1964 denver_0: cpu@0 {
1967 i-cache-size = <0x20000>;
1970 d-cache-size = <0x10000>;
1974 reg = <0x000>;
1980 i-cache-size = <0x20000>;
1983 d-cache-size = <0x10000>;
1987 reg = <0x001>;
1993 i-cache-size = <0xC000>;
1996 d-cache-size = <0x8000>;
2000 reg = <0x100>;
2006 i-cache-size = <0xC000>;
2009 d-cache-size = <0x8000>;
2013 reg = <0x101>;
2019 i-cache-size = <0xC000>;
2022 d-cache-size = <0x8000>;
2026 reg = <0x102>;
2032 i-cache-size = <0xC000>;
2035 d-cache-size = <0x8000>;
2039 reg = <0x103>;
2046 cache-size = <0x200000>;
2055 cache-size = <0x200000>;
2086 assigned-clock-parents = <0>,
2102 polling-delay = <0>;
2110 hysteresis = <0>;
2121 polling-delay = <0>;
2129 hysteresis = <0>;
2139 polling-delay = <0>;
2147 hysteresis = <0>;
2157 polling-delay = <0>;
2165 hysteresis = <0>;
2175 polling-delay = <0>;
2183 hysteresis = <0>;