Lines Matching +full:0 +full:x70000800
22 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
23 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
24 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
31 interrupt-map-mask = <0 0 0 0>;
32 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
34 bus-range = <0x00 0xff>;
38 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
39 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
40 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
41 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
42 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
55 pci@1,0 {
57 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
58 reg = <0x000800 0 0 0 0>;
59 bus-range = <0x00 0xff>;
69 pci@2,0 {
71 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
72 reg = <0x001000 0 0 0 0>;
73 bus-range = <0x00 0xff>;
87 reg = <0x0 0x50000000 0x0 0x00034000>;
99 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
103 reg = <0x0 0x54200000 0x0 0x00040000>;
112 nvidia,head = <0>;
117 reg = <0x0 0x54240000 0x0 0x00040000>;
131 reg = <0x0 0x54280000 0x0 0x00040000>;
143 reg = <0x0 0x54540000 0x0 0x00040000>;
158 reg = <0x0 0x545c0000 0x0 0x00040000>;
169 #size-cells = <0>;
178 reg = <0x0 0x50041000 0x0 0x1000>,
179 <0x0 0x50042000 0x0 0x2000>,
180 <0x0 0x50044000 0x0 0x2000>,
181 <0x0 0x50046000 0x0 0x2000>;
189 reg = <0x0 0x57000000 0x0 0x01000000>,
190 <0x0 0x58000000 0x0 0x01000000>;
204 reg = <0x0 0x60004000 0x0 0x100>,
205 <0x0 0x60004100 0x0 0x100>,
206 <0x0 0x60004200 0x0 0x100>,
207 <0x0 0x60004300 0x0 0x100>,
208 <0x0 0x60004400 0x0 0x100>;
216 reg = <0x0 0x60005000 0x0 0x400>;
217 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
229 reg = <0x0 0x60006000 0x0 0x1000>;
237 reg = <0x0 0x60007000 0x0 0x1000>;
242 reg = <0x0 0x6000c800 0x0 0x400>;
257 reg = <0x0 0x6000d000 0x0 0x1000>;
274 reg = <0x0 0x60020000 0x0 0x1400>;
316 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
317 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */
322 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
323 <0x0 0x70003000 0x0 0x434>, /* Mux registers */
324 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
337 reg = <0x0 0x70006000 0x0 0x40>;
351 reg = <0x0 0x70006040 0x0 0x40>;
365 reg = <0x0 0x70006200 0x0 0x40>;
379 reg = <0x0 0x70006300 0x0 0x40>;
393 reg = <0x0 0x7000a000 0x0 0x100>;
404 reg = <0x0 0x7000c000 0x0 0x100>;
407 #size-cells = <0>;
419 reg = <0x0 0x7000c400 0x0 0x100>;
422 #size-cells = <0>;
434 reg = <0x0 0x7000c500 0x0 0x100>;
437 #size-cells = <0>;
449 reg = <0x0 0x7000c700 0x0 0x100>;
452 #size-cells = <0>;
464 reg = <0x0 0x7000d000 0x0 0x100>;
467 #size-cells = <0>;
479 reg = <0x0 0x7000d100 0x0 0x100>;
482 #size-cells = <0>;
494 reg = <0x0 0x7000d400 0x0 0x200>;
497 #size-cells = <0>;
509 reg = <0x0 0x7000d600 0x0 0x200>;
512 #size-cells = <0>;
524 reg = <0x0 0x7000d800 0x0 0x200>;
527 #size-cells = <0>;
539 reg = <0x0 0x7000da00 0x0 0x200>;
542 #size-cells = <0>;
554 reg = <0x0 0x7000dc00 0x0 0x200>;
557 #size-cells = <0>;
569 reg = <0x0 0x7000de00 0x0 0x200>;
572 #size-cells = <0>;
584 reg = <0x0 0x7000e000 0x0 0x100>;
592 reg = <0x0 0x7000e400 0x0 0x400>;
600 reg = <0x0 0x7000f800 0x0 0x400>;
609 reg = <0x0 0x70019000 0x0 0x1000>;
622 reg = <0x0 0x7001b000 0x0 0x1000>;
629 #interconnect-cells = <0>;
634 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
635 <0x0 0x70020000 0x0 0x7000>; /* SATA */
650 reg = <0x0 0x70030000 0x0 0x10000>;
665 reg = <0x0 0x70090000 0x0 0x8000>,
666 <0x0 0x70098000 0x0 0x1000>,
667 <0x0 0x70099000 0x0 0x1000>;
701 reg = <0x0 0x7009f000 0x0 0x1000>;
710 usb2-0 {
712 #phy-cells = <0>;
717 #phy-cells = <0>;
722 #phy-cells = <0>;
731 ulpi-0 {
733 #phy-cells = <0>;
742 hsic-0 {
744 #phy-cells = <0>;
749 #phy-cells = <0>;
758 pcie-0 {
760 #phy-cells = <0>;
765 #phy-cells = <0>;
770 #phy-cells = <0>;
775 #phy-cells = <0>;
780 #phy-cells = <0>;
789 sata-0 {
791 #phy-cells = <0>;
798 usb2-0 {
810 hsic-0 {
818 usb3-0 {
830 reg = <0x0 0x700b0000 0x0 0x200>;
841 reg = <0x0 0x700b0200 0x0 0x200>;
852 reg = <0x0 0x700b0400 0x0 0x200>;
863 reg = <0x0 0x700b0600 0x0 0x200>;
874 reg = <0x0 0x700e2000 0x0 0x600>, /* 0: SOC_THERM reg_base */
875 <0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */
900 polling-delay = <0>;
928 polling-delay-passive = <0>;
929 polling-delay = <0>;
957 polling-delay = <0>;
985 polling-delay-passive = <0>;
986 polling-delay = <0>;
1015 reg = <0x0 0x70300000 0x0 0x200>,
1016 <0x0 0x70300800 0x0 0x800>,
1017 <0x0 0x70300200 0x0 0x600>;
1067 reg = <0x0 0x70301000 0x0 0x100>;
1078 reg = <0x0 0x70301100 0x0 0x100>;
1089 reg = <0x0 0x70301200 0x0 0x100>;
1100 reg = <0x0 0x70301300 0x0 0x100>;
1111 reg = <0x0 0x70301400 0x0 0x100>;
1123 reg = <0x0 0x7d000000 0x0 0x4000>;
1136 reg = <0x0 0x7d000000 0x0 0x4000>,
1137 <0x0 0x7d000000 0x0 0x4000>;
1146 #phy-cells = <0>;
1147 nvidia,hssync-start-delay = <0>;
1152 nvidia,xcvr-lsfslew = <0>;
1158 nvidia,pmc = <&tegra_pmc 0>;
1164 reg = <0x0 0x7d004000 0x0 0x4000>;
1177 reg = <0x0 0x7d004000 0x0 0x4000>,
1178 <0x0 0x7d000000 0x0 0x4000>;
1187 #phy-cells = <0>;
1188 nvidia,hssync-start-delay = <0>;
1193 nvidia,xcvr-lsfslew = <0>;
1204 reg = <0x0 0x7d008000 0x0 0x4000>;
1217 reg = <0x0 0x7d008000 0x0 0x4000>,
1218 <0x0 0x7d000000 0x0 0x4000>;
1227 #phy-cells = <0>;
1228 nvidia,hssync-start-delay = <0>;
1233 nvidia,xcvr-lsfslew = <0>;
1244 #size-cells = <0>;
1246 cpu@0 {
1249 reg = <0>;