Lines Matching +full:ppi +full:- +full:partitions
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8195-clk.h>
9 #include <dt-bindings/gce/mt8195-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8195-memory-port.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
15 #include <dt-bindings/power/mt8195-power.h>
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
29 #address-cells = <1>;
30 #size-cells = <0>;
34 compatible = "arm,cortex-a55";
36 enable-method = "psci";
37 performance-domains = <&performance 0>;
38 clock-frequency = <1701000000>;
39 capacity-dmips-mhz = <578>;
40 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
41 next-level-cache = <&l2_0>;
42 #cooling-cells = <2>;
47 compatible = "arm,cortex-a55";
49 enable-method = "psci";
50 performance-domains = <&performance 0>;
51 clock-frequency = <1701000000>;
52 capacity-dmips-mhz = <578>;
53 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
54 next-level-cache = <&l2_0>;
55 #cooling-cells = <2>;
60 compatible = "arm,cortex-a55";
62 enable-method = "psci";
63 performance-domains = <&performance 0>;
64 clock-frequency = <1701000000>;
65 capacity-dmips-mhz = <578>;
66 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
67 next-level-cache = <&l2_0>;
68 #cooling-cells = <2>;
73 compatible = "arm,cortex-a55";
75 enable-method = "psci";
76 performance-domains = <&performance 0>;
77 clock-frequency = <1701000000>;
78 capacity-dmips-mhz = <578>;
79 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
80 next-level-cache = <&l2_0>;
81 #cooling-cells = <2>;
86 compatible = "arm,cortex-a78";
88 enable-method = "psci";
89 performance-domains = <&performance 1>;
90 clock-frequency = <2171000000>;
91 capacity-dmips-mhz = <1024>;
92 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
93 next-level-cache = <&l2_1>;
94 #cooling-cells = <2>;
99 compatible = "arm,cortex-a78";
101 enable-method = "psci";
102 performance-domains = <&performance 1>;
103 clock-frequency = <2171000000>;
104 capacity-dmips-mhz = <1024>;
105 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
106 next-level-cache = <&l2_1>;
107 #cooling-cells = <2>;
112 compatible = "arm,cortex-a78";
114 enable-method = "psci";
115 performance-domains = <&performance 1>;
116 clock-frequency = <2171000000>;
117 capacity-dmips-mhz = <1024>;
118 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
119 next-level-cache = <&l2_1>;
120 #cooling-cells = <2>;
125 compatible = "arm,cortex-a78";
127 enable-method = "psci";
128 performance-domains = <&performance 1>;
129 clock-frequency = <2171000000>;
130 capacity-dmips-mhz = <1024>;
131 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
132 next-level-cache = <&l2_1>;
133 #cooling-cells = <2>;
136 cpu-map {
174 idle-states {
175 entry-method = "psci";
177 cpu_off_l: cpu-off-l {
178 compatible = "arm,idle-state";
179 arm,psci-suspend-param = <0x00010001>;
180 local-timer-stop;
181 entry-latency-us = <50>;
182 exit-latency-us = <95>;
183 min-residency-us = <580>;
186 cpu_off_b: cpu-off-b {
187 compatible = "arm,idle-state";
188 arm,psci-suspend-param = <0x00010001>;
189 local-timer-stop;
190 entry-latency-us = <45>;
191 exit-latency-us = <140>;
192 min-residency-us = <740>;
195 cluster_off_l: cluster-off-l {
196 compatible = "arm,idle-state";
197 arm,psci-suspend-param = <0x01010002>;
198 local-timer-stop;
199 entry-latency-us = <55>;
200 exit-latency-us = <155>;
201 min-residency-us = <840>;
204 cluster_off_b: cluster-off-b {
205 compatible = "arm,idle-state";
206 arm,psci-suspend-param = <0x01010002>;
207 local-timer-stop;
208 entry-latency-us = <50>;
209 exit-latency-us = <200>;
210 min-residency-us = <1000>;
214 l2_0: l2-cache0 {
216 next-level-cache = <&l3_0>;
219 l2_1: l2-cache1 {
221 next-level-cache = <&l3_0>;
224 l3_0: l3-cache {
229 dsu-pmu {
230 compatible = "arm,dsu-pmu";
236 dmic_codec: dmic-codec {
237 compatible = "dmic-codec";
238 num-channels = <2>;
239 wakeup-delay-ms = <50>;
242 sound: mt8195-sound {
247 clk26m: oscillator-26m {
248 compatible = "fixed-clock";
249 #clock-cells = <0>;
250 clock-frequency = <26000000>;
251 clock-output-names = "clk26m";
254 clk32k: oscillator-32k {
255 compatible = "fixed-clock";
256 #clock-cells = <0>;
257 clock-frequency = <32768>;
258 clock-output-names = "clk32k";
261 performance: performance-controller@11bc10 {
262 compatible = "mediatek,cpufreq-hw";
264 #performance-domain-cells = <1>;
267 pmu-a55 {
268 compatible = "arm,cortex-a55-pmu";
269 interrupt-parent = <&gic>;
273 pmu-a78 {
274 compatible = "arm,cortex-a78-pmu";
275 interrupt-parent = <&gic>;
280 compatible = "arm,psci-1.0";
285 compatible = "arm,armv8-timer";
286 interrupt-parent = <&gic>;
294 #address-cells = <2>;
295 #size-cells = <2>;
296 compatible = "simple-bus";
299 gic: interrupt-controller@c000000 {
300 compatible = "arm,gic-v3";
301 #interrupt-cells = <4>;
302 #redistributor-regions = <1>;
303 interrupt-parent = <&gic>;
304 interrupt-controller;
309 ppi-partitions {
310 ppi_cluster0: interrupt-partition-0 {
314 ppi_cluster1: interrupt-partition-1 {
321 compatible = "mediatek,mt8195-topckgen", "syscon";
323 #clock-cells = <1>;
327 compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd";
329 #clock-cells = <1>;
330 #reset-cells = <1>;
334 compatible = "mediatek,mt8195-pericfg", "syscon";
336 #clock-cells = <1>;
340 compatible = "mediatek,mt8195-pinctrl";
349 reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
352 gpio-controller;
353 #gpio-cells = <2>;
354 gpio-ranges = <&pio 0 0 144>;
355 interrupt-controller;
357 #interrupt-cells = <2>;
361 compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd";
365 spm: power-controller {
366 compatible = "mediatek,mt8195-power-controller";
367 #address-cells = <1>;
368 #size-cells = <0>;
369 #power-domain-cells = <1>;
372 mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 {
374 #address-cells = <1>;
375 #size-cells = <0>;
376 #power-domain-cells = <1>;
378 power-domain@MT8195_POWER_DOMAIN_MFG1 {
381 clock-names = "mfg";
383 #address-cells = <1>;
384 #size-cells = <0>;
385 #power-domain-cells = <1>;
387 power-domain@MT8195_POWER_DOMAIN_MFG2 {
389 #power-domain-cells = <0>;
392 power-domain@MT8195_POWER_DOMAIN_MFG3 {
394 #power-domain-cells = <0>;
397 power-domain@MT8195_POWER_DOMAIN_MFG4 {
399 #power-domain-cells = <0>;
402 power-domain@MT8195_POWER_DOMAIN_MFG5 {
404 #power-domain-cells = <0>;
407 power-domain@MT8195_POWER_DOMAIN_MFG6 {
409 #power-domain-cells = <0>;
414 power-domain@MT8195_POWER_DOMAIN_VPPSYS0 {
443 clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3",
445 "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3",
446 "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7",
447 "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11",
448 "vppsys0-12", "vppsys0-13", "vppsys0-14",
449 "vppsys0-15", "vppsys0-16", "vppsys0-17",
450 "vppsys0-18";
452 #address-cells = <1>;
453 #size-cells = <0>;
454 #power-domain-cells = <1>;
456 power-domain@MT8195_POWER_DOMAIN_VDEC1 {
459 clock-names = "vdec1-0";
461 #power-domain-cells = <0>;
464 power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 {
467 #power-domain-cells = <0>;
470 power-domain@MT8195_POWER_DOMAIN_VDOSYS0 {
479 clock-names = "vdosys0", "vdosys0-0", "vdosys0-1",
480 "vdosys0-2", "vdosys0-3",
481 "vdosys0-4", "vdosys0-5";
483 #address-cells = <1>;
484 #size-cells = <0>;
485 #power-domain-cells = <1>;
487 power-domain@MT8195_POWER_DOMAIN_VPPSYS1 {
492 clock-names = "vppsys1", "vppsys1-0",
493 "vppsys1-1";
495 #power-domain-cells = <0>;
498 power-domain@MT8195_POWER_DOMAIN_WPESYS {
504 clock-names = "wepsys-0", "wepsys-1", "wepsys-2",
505 "wepsys-3";
507 #power-domain-cells = <0>;
510 power-domain@MT8195_POWER_DOMAIN_VDEC0 {
513 clock-names = "vdec0-0";
515 #power-domain-cells = <0>;
518 power-domain@MT8195_POWER_DOMAIN_VDEC2 {
521 clock-names = "vdec2-0";
523 #power-domain-cells = <0>;
526 power-domain@MT8195_POWER_DOMAIN_VENC {
529 #power-domain-cells = <0>;
532 power-domain@MT8195_POWER_DOMAIN_VDOSYS1 {
538 clock-names = "vdosys1", "vdosys1-0",
539 "vdosys1-1", "vdosys1-2";
541 #address-cells = <1>;
542 #size-cells = <0>;
543 #power-domain-cells = <1>;
545 power-domain@MT8195_POWER_DOMAIN_DP_TX {
548 #power-domain-cells = <0>;
551 power-domain@MT8195_POWER_DOMAIN_EPD_TX {
554 #power-domain-cells = <0>;
557 power-domain@MT8195_POWER_DOMAIN_HDMI_TX {
560 clock-names = "hdmi_tx";
561 #power-domain-cells = <0>;
565 power-domain@MT8195_POWER_DOMAIN_IMG {
569 clock-names = "img-0", "img-1";
571 #address-cells = <1>;
572 #size-cells = <0>;
573 #power-domain-cells = <1>;
575 power-domain@MT8195_POWER_DOMAIN_DIP {
577 #power-domain-cells = <0>;
580 power-domain@MT8195_POWER_DOMAIN_IPE {
585 clock-names = "ipe", "ipe-0", "ipe-1";
587 #power-domain-cells = <0>;
591 power-domain@MT8195_POWER_DOMAIN_CAM {
598 clock-names = "cam-0", "cam-1", "cam-2", "cam-3",
599 "cam-4";
601 #address-cells = <1>;
602 #size-cells = <0>;
603 #power-domain-cells = <1>;
605 power-domain@MT8195_POWER_DOMAIN_CAM_RAWA {
607 #power-domain-cells = <0>;
610 power-domain@MT8195_POWER_DOMAIN_CAM_RAWB {
612 #power-domain-cells = <0>;
615 power-domain@MT8195_POWER_DOMAIN_CAM_MRAW {
617 #power-domain-cells = <0>;
623 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 {
626 #power-domain-cells = <0>;
629 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 {
632 #power-domain-cells = <0>;
635 power-domain@MT8195_POWER_DOMAIN_PCIE_PHY {
637 #power-domain-cells = <0>;
640 power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY {
642 #power-domain-cells = <0>;
645 power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP {
649 clock-names = "csi_rx_top", "csi_rx_top1";
650 #power-domain-cells = <0>;
653 power-domain@MT8195_POWER_DOMAIN_ETHER {
656 clock-names = "ether";
657 #power-domain-cells = <0>;
660 power-domain@MT8195_POWER_DOMAIN_ADSP {
664 clock-names = "adsp", "adsp1";
665 #address-cells = <1>;
666 #size-cells = <0>;
668 #power-domain-cells = <1>;
670 power-domain@MT8195_POWER_DOMAIN_AUDIO {
676 clock-names = "audio", "audio1", "audio2",
679 #power-domain-cells = <0>;
686 compatible = "mediatek,mt8195-wdt",
687 "mediatek,mt6589-wdt";
688 mediatek,disable-extrst;
690 #reset-cells = <1>;
694 compatible = "mediatek,mt8195-apmixedsys", "syscon";
696 #clock-cells = <1>;
700 compatible = "mediatek,mt8195-timer",
701 "mediatek,mt6765-timer";
708 compatible = "mediatek,mt8195-pwrap", "syscon";
710 reg-names = "pwrap";
714 clock-names = "spi", "wrap";
715 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
716 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
720 compatible = "mediatek,mt8195-spmi";
723 reg-names = "pmif", "spmimst";
727 clock-names = "pmif_sys_ck",
730 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
731 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
734 iommu_infra: infra-iommu@10315000 {
735 compatible = "mediatek,mt8195-iommu-infra";
742 #iommu-cells = <1>;
746 compatible = "mediatek,mt8195-gce";
749 #mbox-cells = <2>;
754 compatible = "mediatek,mt8195-gce";
757 #mbox-cells = <2>;
762 compatible = "mediatek,mt8195-scp";
766 reg-names = "sram", "cfg", "l1tcm";
771 scp_adsp: clock-controller@10720000 {
772 compatible = "mediatek,mt8195-scp_adsp";
774 #clock-cells = <1>;
778 compatible = "mediatek,mt8195-dsp";
781 reg-names = "cfg", "sram";
788 clock-names = "adsp_sel",
794 power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>;
795 mbox-names = "rx", "tx";
801 compatible = "mediatek,mt8195-adsp-mbox";
802 #mbox-cells = <0>;
808 compatible = "mediatek,mt8195-adsp-mbox";
809 #mbox-cells = <0>;
814 afe: mt8195-afe-pcm@10890000 {
815 compatible = "mediatek,mt8195-audio";
818 power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>;
821 reset-names = "audiosys";
841 clock-names = "clk26m",
864 compatible = "mediatek,mt8195-uart",
865 "mediatek,mt6577-uart";
869 clock-names = "baud", "bus";
874 compatible = "mediatek,mt8195-uart",
875 "mediatek,mt6577-uart";
879 clock-names = "baud", "bus";
884 compatible = "mediatek,mt8195-uart",
885 "mediatek,mt6577-uart";
889 clock-names = "baud", "bus";
894 compatible = "mediatek,mt8195-uart",
895 "mediatek,mt6577-uart";
899 clock-names = "baud", "bus";
904 compatible = "mediatek,mt8195-uart",
905 "mediatek,mt6577-uart";
909 clock-names = "baud", "bus";
914 compatible = "mediatek,mt8195-uart",
915 "mediatek,mt6577-uart";
919 clock-names = "baud", "bus";
924 compatible = "mediatek,mt8195-auxadc",
925 "mediatek,mt8173-auxadc";
928 clock-names = "main";
929 #io-channel-cells = <1>;
934 compatible = "mediatek,mt8195-pericfg_ao", "syscon";
936 #clock-cells = <1>;
940 compatible = "mediatek,mt8195-spi",
941 "mediatek,mt6765-spi";
942 #address-cells = <1>;
943 #size-cells = <0>;
949 clock-names = "parent-clk", "sel-clk", "spi-clk";
954 compatible = "mediatek,mt8195-spi",
955 "mediatek,mt6765-spi";
956 #address-cells = <1>;
957 #size-cells = <0>;
963 clock-names = "parent-clk", "sel-clk", "spi-clk";
968 compatible = "mediatek,mt8195-spi",
969 "mediatek,mt6765-spi";
970 #address-cells = <1>;
971 #size-cells = <0>;
977 clock-names = "parent-clk", "sel-clk", "spi-clk";
982 compatible = "mediatek,mt8195-spi",
983 "mediatek,mt6765-spi";
984 #address-cells = <1>;
985 #size-cells = <0>;
991 clock-names = "parent-clk", "sel-clk", "spi-clk";
996 compatible = "mediatek,mt8195-spi",
997 "mediatek,mt6765-spi";
998 #address-cells = <1>;
999 #size-cells = <0>;
1005 clock-names = "parent-clk", "sel-clk", "spi-clk";
1010 compatible = "mediatek,mt8195-spi",
1011 "mediatek,mt6765-spi";
1012 #address-cells = <1>;
1013 #size-cells = <0>;
1019 clock-names = "parent-clk", "sel-clk", "spi-clk";
1024 compatible = "mediatek,mt8195-spi-slave";
1028 clock-names = "spi";
1029 assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1030 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1035 compatible = "mediatek,mt8195-spi-slave";
1039 clock-names = "spi";
1040 assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1041 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1046 compatible = "mediatek,mt8195-xhci",
1047 "mediatek,mtk-xhci";
1050 reg-names = "mac", "ippc";
1054 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
1056 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1063 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1065 mediatek,syscon-wakeup = <&pericfg 0x400 103>;
1066 wakeup-source;
1071 compatible = "mediatek,mt8195-mmc",
1072 "mediatek,mt8183-mmc";
1079 clock-names = "source", "hclk", "source_cg";
1084 compatible = "mediatek,mt8195-mmc",
1085 "mediatek,mt8183-mmc";
1092 clock-names = "source", "hclk", "source_cg";
1093 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
1094 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1099 compatible = "mediatek,mt8195-mmc",
1100 "mediatek,mt8183-mmc";
1107 clock-names = "source", "hclk", "source_cg";
1108 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>;
1109 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1114 compatible = "mediatek,mt8195-xhci",
1115 "mediatek,mtk-xhci";
1118 reg-names = "mac", "ippc";
1121 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>,
1123 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1130 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1132 mediatek,syscon-wakeup = <&pericfg 0x400 104>;
1133 wakeup-source;
1138 compatible = "mediatek,mt8195-xhci",
1139 "mediatek,mtk-xhci";
1142 reg-names = "mac", "ippc";
1145 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>,
1147 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1154 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1156 mediatek,syscon-wakeup = <&pericfg 0x400 105>;
1157 wakeup-source;
1162 compatible = "mediatek,mt8195-xhci",
1163 "mediatek,mtk-xhci";
1166 reg-names = "mac", "ippc";
1169 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>,
1171 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1178 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1180 mediatek,syscon-wakeup = <&pericfg 0x400 106>;
1181 wakeup-source;
1186 compatible = "mediatek,mt8195-nor",
1187 "mediatek,mt8173-nor";
1193 clock-names = "spi", "sf", "axi";
1194 #address-cells = <1>;
1195 #size-cells = <0>;
1200 compatible = "mediatek,mt8195-efuse", "mediatek,efuse";
1202 #address-cells = <1>;
1203 #size-cells = <1>;
1204 u3_tx_imp_p0: usb3-tx-imp@184,1 {
1208 u3_rx_imp_p0: usb3-rx-imp@184,2 {
1212 u3_intr_p0: usb3-intr@185 {
1216 comb_tx_imp_p1: usb3-tx-imp@186,1 {
1220 comb_rx_imp_p1: usb3-rx-imp@186,2 {
1224 comb_intr_p1: usb3-intr@187 {
1228 u2_intr_p0: usb2-intr-p0@188,1 {
1232 u2_intr_p1: usb2-intr-p1@188,2 {
1236 u2_intr_p2: usb2-intr-p2@189,1 {
1240 u2_intr_p3: usb2-intr-p3@189,2 {
1246 u3phy2: t-phy@11c40000 {
1247 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1248 #address-cells = <1>;
1249 #size-cells = <1>;
1253 u2port2: usb-phy@0 {
1256 clock-names = "ref";
1257 #phy-cells = <1>;
1261 u3phy3: t-phy@11c50000 {
1262 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1263 #address-cells = <1>;
1264 #size-cells = <1>;
1268 u2port3: usb-phy@0 {
1271 clock-names = "ref";
1272 #phy-cells = <1>;
1277 compatible = "mediatek,mt8195-i2c",
1278 "mediatek,mt8192-i2c";
1282 clock-div = <1>;
1285 clock-names = "main", "dma";
1286 #address-cells = <1>;
1287 #size-cells = <0>;
1292 compatible = "mediatek,mt8195-i2c",
1293 "mediatek,mt8192-i2c";
1297 clock-div = <1>;
1300 clock-names = "main", "dma";
1301 #address-cells = <1>;
1302 #size-cells = <0>;
1307 compatible = "mediatek,mt8195-i2c",
1308 "mediatek,mt8192-i2c";
1312 clock-div = <1>;
1315 clock-names = "main", "dma";
1316 #address-cells = <1>;
1317 #size-cells = <0>;
1321 imp_iic_wrap_s: clock-controller@11d03000 {
1322 compatible = "mediatek,mt8195-imp_iic_wrap_s";
1324 #clock-cells = <1>;
1328 compatible = "mediatek,mt8195-i2c",
1329 "mediatek,mt8192-i2c";
1333 clock-div = <1>;
1336 clock-names = "main", "dma";
1337 #address-cells = <1>;
1338 #size-cells = <0>;
1343 compatible = "mediatek,mt8195-i2c",
1344 "mediatek,mt8192-i2c";
1348 clock-div = <1>;
1351 clock-names = "main", "dma";
1352 #address-cells = <1>;
1353 #size-cells = <0>;
1358 compatible = "mediatek,mt8195-i2c",
1359 "mediatek,mt8192-i2c";
1363 clock-div = <1>;
1366 clock-names = "main", "dma";
1367 #address-cells = <1>;
1368 #size-cells = <0>;
1373 compatible = "mediatek,mt8195-i2c",
1374 "mediatek,mt8192-i2c";
1378 clock-div = <1>;
1381 clock-names = "main", "dma";
1382 #address-cells = <1>;
1383 #size-cells = <0>;
1388 compatible = "mediatek,mt8195-i2c",
1389 "mediatek,mt8192-i2c";
1393 clock-div = <1>;
1396 clock-names = "main", "dma";
1397 #address-cells = <1>;
1398 #size-cells = <0>;
1402 imp_iic_wrap_w: clock-controller@11e05000 {
1403 compatible = "mediatek,mt8195-imp_iic_wrap_w";
1405 #clock-cells = <1>;
1408 u3phy1: t-phy@11e30000 {
1409 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1410 #address-cells = <1>;
1411 #size-cells = <1>;
1415 u2port1: usb-phy@0 {
1419 clock-names = "ref", "da_ref";
1420 #phy-cells = <1>;
1423 u3port1: usb-phy@700 {
1427 clock-names = "ref", "da_ref";
1428 nvmem-cells = <&comb_intr_p1>,
1431 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
1432 #phy-cells = <1>;
1436 u3phy0: t-phy@11e40000 {
1437 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1438 #address-cells = <1>;
1439 #size-cells = <1>;
1443 u2port0: usb-phy@0 {
1447 clock-names = "ref", "da_ref";
1448 #phy-cells = <1>;
1451 u3port0: usb-phy@700 {
1455 clock-names = "ref", "da_ref";
1456 nvmem-cells = <&u3_intr_p0>,
1459 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
1460 #phy-cells = <1>;
1464 ufsphy: ufs-phy@11fa0000 {
1465 compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy";
1468 clock-names = "unipro", "mp";
1469 #phy-cells = <0>;
1473 mfgcfg: clock-controller@13fbf000 {
1474 compatible = "mediatek,mt8195-mfgcfg";
1476 #clock-cells = <1>;
1479 vppsys0: clock-controller@14000000 {
1480 compatible = "mediatek,mt8195-vppsys0";
1482 #clock-cells = <1>;
1486 compatible = "mediatek,mt8195-smi-sub-common";
1491 clock-names = "apb", "smi", "gals0";
1493 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
1497 compatible = "mediatek,mt8195-smi-sub-common";
1502 clock-names = "apb", "smi", "gals0";
1504 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
1508 compatible = "mediatek,mt8195-smi-common-vpp";
1514 clock-names = "apb", "smi", "gals0", "gals1";
1515 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
1519 compatible = "mediatek,mt8195-smi-larb";
1521 mediatek,larb-id = <4>;
1525 clock-names = "apb", "smi";
1526 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
1530 compatible = "mediatek,mt8195-iommu-vpp";
1538 clock-names = "bclk";
1539 #iommu-cells = <1>;
1540 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
1543 wpesys: clock-controller@14e00000 {
1544 compatible = "mediatek,mt8195-wpesys";
1546 #clock-cells = <1>;
1549 wpesys_vpp0: clock-controller@14e02000 {
1550 compatible = "mediatek,mt8195-wpesys_vpp0";
1552 #clock-cells = <1>;
1555 wpesys_vpp1: clock-controller@14e03000 {
1556 compatible = "mediatek,mt8195-wpesys_vpp1";
1558 #clock-cells = <1>;
1562 compatible = "mediatek,mt8195-smi-larb";
1564 mediatek,larb-id = <7>;
1568 clock-names = "apb", "smi";
1569 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
1573 compatible = "mediatek,mt8195-smi-larb";
1575 mediatek,larb-id = <8>;
1580 clock-names = "apb", "smi", "gals";
1581 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
1584 vppsys1: clock-controller@14f00000 {
1585 compatible = "mediatek,mt8195-vppsys1";
1587 #clock-cells = <1>;
1591 compatible = "mediatek,mt8195-smi-larb";
1593 mediatek,larb-id = <5>;
1598 clock-names = "apb", "smi", "gals";
1599 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
1603 compatible = "mediatek,mt8195-smi-larb";
1605 mediatek,larb-id = <6>;
1610 clock-names = "apb", "smi", "gals";
1611 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
1614 imgsys: clock-controller@15000000 {
1615 compatible = "mediatek,mt8195-imgsys";
1617 #clock-cells = <1>;
1621 compatible = "mediatek,mt8195-smi-larb";
1623 mediatek,larb-id = <9>;
1628 clock-names = "apb", "smi", "gals";
1629 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
1633 compatible = "mediatek,mt8195-smi-sub-common";
1638 clock-names = "apb", "smi", "gals0";
1640 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
1644 compatible = "mediatek,mt8195-smi-sub-common";
1649 clock-names = "apb", "smi", "gals0";
1651 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
1654 imgsys1_dip_top: clock-controller@15110000 {
1655 compatible = "mediatek,mt8195-imgsys1_dip_top";
1657 #clock-cells = <1>;
1661 compatible = "mediatek,mt8195-smi-larb";
1663 mediatek,larb-id = <10>;
1667 clock-names = "apb", "smi";
1668 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
1671 imgsys1_dip_nr: clock-controller@15130000 {
1672 compatible = "mediatek,mt8195-imgsys1_dip_nr";
1674 #clock-cells = <1>;
1677 imgsys1_wpe: clock-controller@15220000 {
1678 compatible = "mediatek,mt8195-imgsys1_wpe";
1680 #clock-cells = <1>;
1684 compatible = "mediatek,mt8195-smi-larb";
1686 mediatek,larb-id = <11>;
1690 clock-names = "apb", "smi";
1691 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
1694 ipesys: clock-controller@15330000 {
1695 compatible = "mediatek,mt8195-ipesys";
1697 #clock-cells = <1>;
1701 compatible = "mediatek,mt8195-smi-larb";
1703 mediatek,larb-id = <12>;
1707 clock-names = "apb", "smi";
1708 power-domains = <&spm MT8195_POWER_DOMAIN_IPE>;
1711 camsys: clock-controller@16000000 {
1712 compatible = "mediatek,mt8195-camsys";
1714 #clock-cells = <1>;
1718 compatible = "mediatek,mt8195-smi-larb";
1720 mediatek,larb-id = <13>;
1725 clock-names = "apb", "smi", "gals";
1726 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
1730 compatible = "mediatek,mt8195-smi-larb";
1732 mediatek,larb-id = <14>;
1736 clock-names = "apb", "smi";
1737 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
1741 compatible = "mediatek,mt8195-smi-sub-common";
1746 clock-names = "apb", "smi", "gals0";
1748 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
1752 compatible = "mediatek,mt8195-smi-sub-common";
1757 clock-names = "apb", "smi", "gals0";
1759 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
1763 compatible = "mediatek,mt8195-smi-larb";
1765 mediatek,larb-id = <16>;
1769 clock-names = "apb", "smi";
1770 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
1774 compatible = "mediatek,mt8195-smi-larb";
1776 mediatek,larb-id = <17>;
1780 clock-names = "apb", "smi";
1781 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
1785 compatible = "mediatek,mt8195-smi-larb";
1787 mediatek,larb-id = <27>;
1791 clock-names = "apb", "smi";
1792 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
1796 compatible = "mediatek,mt8195-smi-larb";
1798 mediatek,larb-id = <28>;
1802 clock-names = "apb", "smi";
1803 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
1806 camsys_rawa: clock-controller@1604f000 {
1807 compatible = "mediatek,mt8195-camsys_rawa";
1809 #clock-cells = <1>;
1812 camsys_yuva: clock-controller@1606f000 {
1813 compatible = "mediatek,mt8195-camsys_yuva";
1815 #clock-cells = <1>;
1818 camsys_rawb: clock-controller@1608f000 {
1819 compatible = "mediatek,mt8195-camsys_rawb";
1821 #clock-cells = <1>;
1824 camsys_yuvb: clock-controller@160af000 {
1825 compatible = "mediatek,mt8195-camsys_yuvb";
1827 #clock-cells = <1>;
1830 camsys_mraw: clock-controller@16140000 {
1831 compatible = "mediatek,mt8195-camsys_mraw";
1833 #clock-cells = <1>;
1837 compatible = "mediatek,mt8195-smi-larb";
1839 mediatek,larb-id = <25>;
1844 clock-names = "apb", "smi", "gals";
1845 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
1849 compatible = "mediatek,mt8195-smi-larb";
1851 mediatek,larb-id = <26>;
1855 clock-names = "apb", "smi";
1856 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
1860 ccusys: clock-controller@17200000 {
1861 compatible = "mediatek,mt8195-ccusys";
1863 #clock-cells = <1>;
1867 compatible = "mediatek,mt8195-smi-larb";
1869 mediatek,larb-id = <18>;
1873 clock-names = "apb", "smi";
1874 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
1878 compatible = "mediatek,mt8195-smi-larb";
1880 mediatek,larb-id = <24>;
1884 clock-names = "apb", "smi";
1885 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
1889 compatible = "mediatek,mt8195-smi-larb";
1891 mediatek,larb-id = <23>;
1895 clock-names = "apb", "smi";
1896 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
1899 vdecsys_soc: clock-controller@1800f000 {
1900 compatible = "mediatek,mt8195-vdecsys_soc";
1902 #clock-cells = <1>;
1906 compatible = "mediatek,mt8195-smi-larb";
1908 mediatek,larb-id = <21>;
1912 clock-names = "apb", "smi";
1913 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
1916 vdecsys: clock-controller@1802f000 {
1917 compatible = "mediatek,mt8195-vdecsys";
1919 #clock-cells = <1>;
1923 compatible = "mediatek,mt8195-smi-larb";
1925 mediatek,larb-id = <22>;
1929 clock-names = "apb", "smi";
1930 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
1933 vdecsys_core1: clock-controller@1803f000 {
1934 compatible = "mediatek,mt8195-vdecsys_core1";
1936 #clock-cells = <1>;
1939 apusys_pll: clock-controller@190f3000 {
1940 compatible = "mediatek,mt8195-apusys_pll";
1942 #clock-cells = <1>;
1945 vencsys: clock-controller@1a000000 {
1946 compatible = "mediatek,mt8195-vencsys";
1948 #clock-cells = <1>;
1952 compatible = "mediatek,mt8195-smi-larb";
1954 mediatek,larb-id = <19>;
1958 clock-names = "apb", "smi";
1959 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
1962 vencsys_core1: clock-controller@1b000000 {
1963 compatible = "mediatek,mt8195-vencsys_core1";
1965 #clock-cells = <1>;
1969 compatible = "mediatek,mt8195-mmsys", "syscon";
1972 #clock-cells = <1>;
1976 compatible = "mediatek,mt8195-smi-larb";
1978 mediatek,larb-id = <20>;
1983 clock-names = "apb", "smi", "gals";
1984 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
1988 compatible = "mediatek,mt8195-disp-ovl", "mediatek,mt8183-disp-ovl";
1991 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
1994 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>;
1998 compatible = "mediatek,mt8195-disp-rdma";
2001 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2004 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>;
2008 compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-color";
2011 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2013 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>;
2017 compatible = "mediatek,mt8195-disp-ccorr", "mediatek,mt8192-disp-ccorr";
2020 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2022 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>;
2026 compatible = "mediatek,mt8195-disp-aal", "mediatek,mt8183-disp-aal";
2029 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2031 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>;
2035 compatible = "mediatek,mt8195-disp-gamma", "mediatek,mt8183-disp-gamma";
2038 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2040 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>;
2044 compatible = "mediatek,mt8195-disp-dither", "mediatek,mt8183-disp-dither";
2047 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2049 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>;
2053 compatible = "mediatek,mt8195-disp-dsc";
2056 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2058 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>;
2062 compatible = "mediatek,mt8195-disp-merge";
2065 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2067 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>;
2071 compatible = "mediatek,mt8195-disp-mutex";
2074 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2076 mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
2080 compatible = "mediatek,mt8195-smi-larb";
2082 mediatek,larb-id = <0>;
2087 clock-names = "apb", "smi", "gals";
2088 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2092 compatible = "mediatek,mt8195-smi-larb";
2094 mediatek,larb-id = <1>;
2099 clock-names = "apb", "smi", "gals";
2100 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2104 compatible = "mediatek,mt8195-mmsys", "syscon";
2106 #clock-cells = <1>;
2110 compatible = "mediatek,mt8195-smi-common-vdo";
2116 clock-names = "apb", "smi", "gals0", "gals1";
2117 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2122 compatible = "mediatek,mt8195-iommu-vdo";
2129 #iommu-cells = <1>;
2131 clock-names = "bclk";
2132 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2136 compatible = "mediatek,mt8195-smi-larb";
2138 mediatek,larb-id = <2>;
2143 clock-names = "apb", "smi", "gals";
2144 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2148 compatible = "mediatek,mt8195-smi-larb";
2150 mediatek,larb-id = <3>;
2155 clock-names = "apb", "smi", "gals";
2156 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;