Lines Matching +full:ppi +full:- +full:partitions
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8192-clk.h>
9 #include <dt-bindings/gce/mt8192-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8192-larb-port.h>
13 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
14 #include <dt-bindings/phy/phy.h>
15 #include <dt-bindings/power/mt8192-power.h>
16 #include <dt-bindings/reset/mt8192-resets.h>
20 interrupt-parent = <&gic>;
21 #address-cells = <2>;
22 #size-cells = <2>;
26 ovl-2l0 = &ovl_2l0;
27 ovl-2l2 = &ovl_2l2;
33 compatible = "fixed-clock";
34 #clock-cells = <0>;
35 clock-frequency = <26000000>;
36 clock-output-names = "clk26m";
40 compatible = "fixed-clock";
41 #clock-cells = <0>;
42 clock-frequency = <32768>;
43 clock-output-names = "clk32k";
47 #address-cells = <1>;
48 #size-cells = <0>;
52 compatible = "arm,cortex-a55";
54 enable-method = "psci";
55 clock-frequency = <1701000000>;
56 cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
57 next-level-cache = <&l2_0>;
58 capacity-dmips-mhz = <530>;
63 compatible = "arm,cortex-a55";
65 enable-method = "psci";
66 clock-frequency = <1701000000>;
67 cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
68 next-level-cache = <&l2_0>;
69 capacity-dmips-mhz = <530>;
74 compatible = "arm,cortex-a55";
76 enable-method = "psci";
77 clock-frequency = <1701000000>;
78 cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
79 next-level-cache = <&l2_0>;
80 capacity-dmips-mhz = <530>;
85 compatible = "arm,cortex-a55";
87 enable-method = "psci";
88 clock-frequency = <1701000000>;
89 cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
90 next-level-cache = <&l2_0>;
91 capacity-dmips-mhz = <530>;
96 compatible = "arm,cortex-a76";
98 enable-method = "psci";
99 clock-frequency = <2171000000>;
100 cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
101 next-level-cache = <&l2_1>;
102 capacity-dmips-mhz = <1024>;
107 compatible = "arm,cortex-a76";
109 enable-method = "psci";
110 clock-frequency = <2171000000>;
111 cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
112 next-level-cache = <&l2_1>;
113 capacity-dmips-mhz = <1024>;
118 compatible = "arm,cortex-a76";
120 enable-method = "psci";
121 clock-frequency = <2171000000>;
122 cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
123 next-level-cache = <&l2_1>;
124 capacity-dmips-mhz = <1024>;
129 compatible = "arm,cortex-a76";
131 enable-method = "psci";
132 clock-frequency = <2171000000>;
133 cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
134 next-level-cache = <&l2_1>;
135 capacity-dmips-mhz = <1024>;
138 cpu-map {
170 l2_0: l2-cache0 {
172 next-level-cache = <&l3_0>;
175 l2_1: l2-cache1 {
177 next-level-cache = <&l3_0>;
180 l3_0: l3-cache {
184 idle-states {
185 entry-method = "psci";
186 cpu_sleep_l: cpu-sleep-l {
187 compatible = "arm,idle-state";
188 arm,psci-suspend-param = <0x00010001>;
189 local-timer-stop;
190 entry-latency-us = <55>;
191 exit-latency-us = <140>;
192 min-residency-us = <780>;
194 cpu_sleep_b: cpu-sleep-b {
195 compatible = "arm,idle-state";
196 arm,psci-suspend-param = <0x00010001>;
197 local-timer-stop;
198 entry-latency-us = <35>;
199 exit-latency-us = <145>;
200 min-residency-us = <720>;
202 cluster_sleep_l: cluster-sleep-l {
203 compatible = "arm,idle-state";
204 arm,psci-suspend-param = <0x01010002>;
205 local-timer-stop;
206 entry-latency-us = <60>;
207 exit-latency-us = <155>;
208 min-residency-us = <860>;
210 cluster_sleep_b: cluster-sleep-b {
211 compatible = "arm,idle-state";
212 arm,psci-suspend-param = <0x01010002>;
213 local-timer-stop;
214 entry-latency-us = <40>;
215 exit-latency-us = <155>;
216 min-residency-us = <780>;
221 pmu-a55 {
222 compatible = "arm,cortex-a55-pmu";
223 interrupt-parent = <&gic>;
227 pmu-a76 {
228 compatible = "arm,cortex-a76-pmu";
229 interrupt-parent = <&gic>;
234 compatible = "arm,psci-1.0";
239 compatible = "arm,armv8-timer";
240 interrupt-parent = <&gic>;
245 clock-frequency = <13000000>;
249 #address-cells = <2>;
250 #size-cells = <2>;
251 compatible = "simple-bus";
254 gic: interrupt-controller@c000000 {
255 compatible = "arm,gic-v3";
256 #interrupt-cells = <4>;
257 #redistributor-regions = <1>;
258 interrupt-parent = <&gic>;
259 interrupt-controller;
264 ppi-partitions {
265 ppi_cluster0: interrupt-partition-0 {
268 ppi_cluster1: interrupt-partition-1 {
275 compatible = "mediatek,mt8192-topckgen", "syscon";
277 #clock-cells = <1>;
281 compatible = "mediatek,mt8192-infracfg", "syscon";
283 #clock-cells = <1>;
284 #reset-cells = <1>;
288 compatible = "mediatek,mt8192-pericfg", "syscon";
290 #clock-cells = <1>;
294 compatible = "mediatek,mt8192-pinctrl";
306 reg-names = "iocfg0", "iocfg_rm", "iocfg_bm",
310 gpio-controller;
311 #gpio-cells = <2>;
312 gpio-ranges = <&pio 0 0 220>;
313 interrupt-controller;
315 #interrupt-cells = <2>;
319 compatible = "mediatek,mt8192-scpsys", "syscon", "simple-mfd";
323 spm: power-controller {
324 compatible = "mediatek,mt8192-power-controller";
325 #address-cells = <1>;
326 #size-cells = <0>;
327 #power-domain-cells = <1>;
330 power-domain@MT8192_POWER_DOMAIN_AUDIO {
335 clock-names = "audio", "audio1", "audio2";
337 #power-domain-cells = <0>;
340 power-domain@MT8192_POWER_DOMAIN_CONN {
343 clock-names = "conn";
345 #power-domain-cells = <0>;
348 power-domain@MT8192_POWER_DOMAIN_MFG0 {
351 clock-names = "mfg";
352 #address-cells = <1>;
353 #size-cells = <0>;
354 #power-domain-cells = <1>;
356 power-domain@MT8192_POWER_DOMAIN_MFG1 {
359 #address-cells = <1>;
360 #size-cells = <0>;
361 #power-domain-cells = <1>;
363 power-domain@MT8192_POWER_DOMAIN_MFG2 {
365 #power-domain-cells = <0>;
368 power-domain@MT8192_POWER_DOMAIN_MFG3 {
370 #power-domain-cells = <0>;
373 power-domain@MT8192_POWER_DOMAIN_MFG4 {
375 #power-domain-cells = <0>;
378 power-domain@MT8192_POWER_DOMAIN_MFG5 {
380 #power-domain-cells = <0>;
383 power-domain@MT8192_POWER_DOMAIN_MFG6 {
385 #power-domain-cells = <0>;
390 power-domain@MT8192_POWER_DOMAIN_DISP {
397 clock-names = "disp", "disp-0", "disp-1", "disp-2",
398 "disp-3";
400 #address-cells = <1>;
401 #size-cells = <0>;
402 #power-domain-cells = <1>;
404 power-domain@MT8192_POWER_DOMAIN_IPE {
411 clock-names = "ipe", "ipe-0", "ipe-1", "ipe-2",
412 "ipe-3";
414 #power-domain-cells = <0>;
417 power-domain@MT8192_POWER_DOMAIN_ISP {
422 clock-names = "isp", "isp-0", "isp-1";
424 #power-domain-cells = <0>;
427 power-domain@MT8192_POWER_DOMAIN_ISP2 {
432 clock-names = "isp2", "isp2-0", "isp2-1";
434 #power-domain-cells = <0>;
437 power-domain@MT8192_POWER_DOMAIN_MDP {
441 clock-names = "mdp", "mdp-0";
443 #power-domain-cells = <0>;
446 power-domain@MT8192_POWER_DOMAIN_VENC {
450 clock-names = "venc", "venc-0";
452 #power-domain-cells = <0>;
455 power-domain@MT8192_POWER_DOMAIN_VDEC {
461 clock-names = "vdec", "vdec-0", "vdec-1", "vdec-2";
463 #address-cells = <1>;
464 #size-cells = <0>;
465 #power-domain-cells = <1>;
467 power-domain@MT8192_POWER_DOMAIN_VDEC2 {
472 clock-names = "vdec2-0", "vdec2-1",
473 "vdec2-2";
474 #power-domain-cells = <0>;
478 power-domain@MT8192_POWER_DOMAIN_CAM {
485 clock-names = "cam", "cam-0", "cam-1", "cam-2",
486 "cam-3";
488 #address-cells = <1>;
489 #size-cells = <0>;
490 #power-domain-cells = <1>;
492 power-domain@MT8192_POWER_DOMAIN_CAM_RAWA {
495 clock-names = "cam_rawa-0";
496 #power-domain-cells = <0>;
499 power-domain@MT8192_POWER_DOMAIN_CAM_RAWB {
502 clock-names = "cam_rawb-0";
503 #power-domain-cells = <0>;
506 power-domain@MT8192_POWER_DOMAIN_CAM_RAWC {
509 clock-names = "cam_rawc-0";
510 #power-domain-cells = <0>;
518 compatible = "mediatek,mt8192-wdt";
520 #reset-cells = <1>;
524 compatible = "mediatek,mt8192-apmixedsys", "syscon";
526 #clock-cells = <1>;
530 compatible = "mediatek,mt8192-timer",
531 "mediatek,mt6765-timer";
535 clock-names = "clk13m";
539 compatible = "mediatek,mt6873-pwrap";
541 reg-names = "pwrap";
545 clock-names = "spi", "wrap";
546 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
547 assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
551 compatible = "mediatek,mt6873-spmi";
554 reg-names = "pmif", "spmimst";
558 clock-names = "pmif_sys_ck",
561 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
562 assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
566 compatible = "mediatek,mt8192-gce";
569 #mbox-cells = <2>;
571 clock-names = "gce";
574 scp_adsp: clock-controller@10720000 {
575 compatible = "mediatek,mt8192-scp_adsp";
577 #clock-cells = <1>;
581 compatible = "mediatek,mt8192-uart",
582 "mediatek,mt6577-uart";
586 clock-names = "baud", "bus";
591 compatible = "mediatek,mt8192-uart",
592 "mediatek,mt6577-uart";
596 clock-names = "baud", "bus";
600 imp_iic_wrap_c: clock-controller@11007000 {
601 compatible = "mediatek,mt8192-imp_iic_wrap_c";
603 #clock-cells = <1>;
607 compatible = "mediatek,mt8192-spi",
608 "mediatek,mt6765-spi";
609 #address-cells = <1>;
610 #size-cells = <0>;
616 clock-names = "parent-clk", "sel-clk", "spi-clk";
621 compatible = "mediatek,mt8183-disp-pwm";
624 #pwm-cells = <2>;
627 clock-names = "main", "mm";
632 compatible = "mediatek,mt8192-spi",
633 "mediatek,mt6765-spi";
634 #address-cells = <1>;
635 #size-cells = <0>;
641 clock-names = "parent-clk", "sel-clk", "spi-clk";
646 compatible = "mediatek,mt8192-spi",
647 "mediatek,mt6765-spi";
648 #address-cells = <1>;
649 #size-cells = <0>;
655 clock-names = "parent-clk", "sel-clk", "spi-clk";
660 compatible = "mediatek,mt8192-spi",
661 "mediatek,mt6765-spi";
662 #address-cells = <1>;
663 #size-cells = <0>;
669 clock-names = "parent-clk", "sel-clk", "spi-clk";
674 compatible = "mediatek,mt8192-spi",
675 "mediatek,mt6765-spi";
676 #address-cells = <1>;
677 #size-cells = <0>;
683 clock-names = "parent-clk", "sel-clk", "spi-clk";
688 compatible = "mediatek,mt8192-spi",
689 "mediatek,mt6765-spi";
690 #address-cells = <1>;
691 #size-cells = <0>;
697 clock-names = "parent-clk", "sel-clk", "spi-clk";
702 compatible = "mediatek,mt8192-spi",
703 "mediatek,mt6765-spi";
704 #address-cells = <1>;
705 #size-cells = <0>;
711 clock-names = "parent-clk", "sel-clk", "spi-clk";
716 compatible = "mediatek,mt8192-spi",
717 "mediatek,mt6765-spi";
718 #address-cells = <1>;
719 #size-cells = <0>;
725 clock-names = "parent-clk", "sel-clk", "spi-clk";
730 compatible = "mediatek,mt8192-scp";
734 reg-names = "sram", "cfg", "l1tcm";
737 clock-names = "main";
742 compatible = "mediatek,mt8192-xhci",
743 "mediatek,mtk-xhci";
746 reg-names = "mac", "ippc";
747 interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
748 interrupt-names = "host";
751 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>,
753 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
760 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
762 wakeup-source;
763 mediatek,syscon-wakeup = <&pericfg 0x420 102>;
768 compatible = "mediatek,mt8192-audsys", "syscon";
770 #clock-cells = <1>;
772 afe: mt8192-afe-pcm {
773 compatible = "mediatek,mt8192-audio";
776 reset-names = "audiosys";
780 power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>;
837 clock-names = "aud_afe_clk",
897 compatible = "mediatek,mt8192-pcie";
900 reg-names = "pcie-mac";
901 #address-cells = <3>;
902 #size-cells = <2>;
909 clock-names = "pl_250m", "tl_26m", "tl_96m",
911 assigned-clocks = <&topckgen CLK_TOP_TL_SEL>;
912 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>;
914 bus-range = <0x00 0xff>;
917 #interrupt-cells = <1>;
918 interrupt-map-mask = <0 0 0 7>;
919 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
924 pcie_intc0: interrupt-controller {
925 interrupt-controller;
926 #address-cells = <0>;
927 #interrupt-cells = <1>;
932 compatible = "mediatek,mt8192-nor";
938 clock-names = "spi", "sf", "axi";
939 assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>;
940 assigned-clock-parents = <&clk26m>;
941 #address-cells = <1>;
942 #size-cells = <0>;
947 compatible = "mediatek,mt8192-efuse", "mediatek,efuse";
949 #address-cells = <1>;
950 #size-cells = <1>;
962 compatible = "mediatek,mt8192-i2c";
968 clock-names = "main", "dma";
969 clock-div = <1>;
970 #address-cells = <1>;
971 #size-cells = <0>;
975 imp_iic_wrap_e: clock-controller@11cb1000 {
976 compatible = "mediatek,mt8192-imp_iic_wrap_e";
978 #clock-cells = <1>;
982 compatible = "mediatek,mt8192-i2c";
988 clock-names = "main", "dma";
989 clock-div = <1>;
990 #address-cells = <1>;
991 #size-cells = <0>;
996 compatible = "mediatek,mt8192-i2c";
1002 clock-names = "main", "dma";
1003 clock-div = <1>;
1004 #address-cells = <1>;
1005 #size-cells = <0>;
1010 compatible = "mediatek,mt8192-i2c";
1016 clock-names = "main", "dma";
1017 clock-div = <1>;
1018 #address-cells = <1>;
1019 #size-cells = <0>;
1023 imp_iic_wrap_s: clock-controller@11d03000 {
1024 compatible = "mediatek,mt8192-imp_iic_wrap_s";
1026 #clock-cells = <1>;
1030 compatible = "mediatek,mt8192-i2c";
1036 clock-names = "main", "dma";
1037 clock-div = <1>;
1038 #address-cells = <1>;
1039 #size-cells = <0>;
1044 compatible = "mediatek,mt8192-i2c";
1050 clock-names = "main", "dma";
1051 clock-div = <1>;
1052 #address-cells = <1>;
1053 #size-cells = <0>;
1058 compatible = "mediatek,mt8192-i2c";
1064 clock-names = "main", "dma";
1065 clock-div = <1>;
1066 #address-cells = <1>;
1067 #size-cells = <0>;
1071 imp_iic_wrap_ws: clock-controller@11d23000 {
1072 compatible = "mediatek,mt8192-imp_iic_wrap_ws";
1074 #clock-cells = <1>;
1078 compatible = "mediatek,mt8192-i2c";
1084 clock-names = "main", "dma";
1085 clock-div = <1>;
1086 #address-cells = <1>;
1087 #size-cells = <0>;
1091 imp_iic_wrap_w: clock-controller@11e01000 {
1092 compatible = "mediatek,mt8192-imp_iic_wrap_w";
1094 #clock-cells = <1>;
1097 u3phy0: t-phy@11e40000 {
1098 compatible = "mediatek,mt8192-tphy",
1099 "mediatek,generic-tphy-v2";
1100 #address-cells = <1>;
1101 #size-cells = <1>;
1104 u2port0: usb-phy@0 {
1107 clock-names = "ref";
1108 #phy-cells = <1>;
1111 u3port0: usb-phy@700 {
1114 clock-names = "ref";
1115 #phy-cells = <1>;
1119 mipi_tx0: dsi-phy@11e50000 {
1120 compatible = "mediatek,mt8183-mipi-tx";
1123 #clock-cells = <0>;
1124 #phy-cells = <0>;
1125 clock-output-names = "mipi_tx0_pll";
1130 compatible = "mediatek,mt8192-i2c";
1136 clock-names = "main", "dma";
1137 clock-div = <1>;
1138 #address-cells = <1>;
1139 #size-cells = <0>;
1144 compatible = "mediatek,mt8192-i2c";
1150 clock-names = "main", "dma";
1151 clock-div = <1>;
1152 #address-cells = <1>;
1153 #size-cells = <0>;
1157 imp_iic_wrap_n: clock-controller@11f02000 {
1158 compatible = "mediatek,mt8192-imp_iic_wrap_n";
1160 #clock-cells = <1>;
1163 msdc_top: clock-controller@11f10000 {
1164 compatible = "mediatek,mt8192-msdc_top";
1166 #clock-cells = <1>;
1170 compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
1180 clock-names = "source", "hclk", "source_cg", "sys_cg",
1186 compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
1196 clock-names = "source", "hclk", "source_cg", "sys_cg",
1201 mfgcfg: clock-controller@13fbf000 {
1202 compatible = "mediatek,mt8192-mfgcfg";
1204 #clock-cells = <1>;
1208 compatible = "mediatek,mt8192-mmsys", "syscon";
1210 #clock-cells = <1>;
1211 #reset-cells = <1>;
1214 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1218 compatible = "mediatek,mt8192-disp-mutex";
1222 mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
1224 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1228 compatible = "mediatek,mt8192-smi-common";
1234 clock-names = "apb", "smi", "gals0", "gals1";
1235 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1239 compatible = "mediatek,mt8192-smi-larb";
1241 mediatek,larb-id = <0>;
1244 clock-names = "apb", "smi";
1245 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1249 compatible = "mediatek,mt8192-smi-larb";
1251 mediatek,larb-id = <1>;
1254 clock-names = "apb", "smi";
1255 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1259 compatible = "mediatek,mt8192-disp-ovl";
1265 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1266 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
1270 compatible = "mediatek,mt8192-disp-ovl-2l";
1273 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1277 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
1281 compatible = "mediatek,mt8192-disp-rdma",
1282 "mediatek,mt8183-disp-rdma";
1287 mediatek,rdma-fifo-size = <5120>;
1288 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1289 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
1293 compatible = "mediatek,mt8192-disp-color",
1294 "mediatek,mt8173-disp-color";
1297 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1299 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
1303 compatible = "mediatek,mt8192-disp-ccorr";
1306 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1308 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
1312 compatible = "mediatek,mt8192-disp-aal",
1313 "mediatek,mt8183-disp-aal";
1316 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1318 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
1322 compatible = "mediatek,mt8192-disp-gamma",
1323 "mediatek,mt8183-disp-gamma";
1326 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1328 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1332 compatible = "mediatek,mt8192-disp-postmask";
1335 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1337 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
1341 compatible = "mediatek,mt8192-disp-dither",
1342 "mediatek,mt8183-disp-dither";
1345 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1347 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1351 compatible = "mediatek,mt8183-dsi";
1357 clock-names = "engine", "digital", "hs";
1359 phy-names = "dphy";
1360 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1370 compatible = "mediatek,mt8192-disp-ovl-2l";
1373 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1377 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
1381 compatible = "mediatek,mt8192-disp-rdma",
1382 "mediatek,mt8183-disp-rdma";
1385 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1388 mediatek,rdma-fifo-size = <2048>;
1389 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
1393 compatible = "mediatek,mt8192-dpi";
1399 clock-names = "pixel", "engine", "pll";
1404 compatible = "mediatek,mt8192-m4u";
1413 clock-names = "bclk";
1414 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1415 #iommu-cells = <1>;
1418 imgsys: clock-controller@15020000 {
1419 compatible = "mediatek,mt8192-imgsys";
1421 #clock-cells = <1>;
1425 compatible = "mediatek,mt8192-smi-larb";
1427 mediatek,larb-id = <9>;
1431 clock-names = "apb", "smi";
1432 power-domains = <&spm MT8192_POWER_DOMAIN_ISP>;
1435 imgsys2: clock-controller@15820000 {
1436 compatible = "mediatek,mt8192-imgsys2";
1438 #clock-cells = <1>;
1442 compatible = "mediatek,mt8192-smi-larb";
1444 mediatek,larb-id = <11>;
1448 clock-names = "apb", "smi";
1449 power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
1453 compatible = "mediatek,mt8192-smi-larb";
1455 mediatek,larb-id = <5>;
1459 clock-names = "apb", "smi";
1460 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
1463 vdecsys_soc: clock-controller@1600f000 {
1464 compatible = "mediatek,mt8192-vdecsys_soc";
1466 #clock-cells = <1>;
1470 compatible = "mediatek,mt8192-smi-larb";
1472 mediatek,larb-id = <4>;
1476 clock-names = "apb", "smi";
1477 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
1480 vdecsys: clock-controller@1602f000 {
1481 compatible = "mediatek,mt8192-vdecsys";
1483 #clock-cells = <1>;
1486 vencsys: clock-controller@17000000 {
1487 compatible = "mediatek,mt8192-vencsys";
1489 #clock-cells = <1>;
1493 compatible = "mediatek,mt8192-smi-larb";
1495 mediatek,larb-id = <7>;
1499 clock-names = "apb", "smi";
1500 power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
1504 compatible = "mediatek,mt8192-vcodec-enc";
1519 power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
1521 clock-names = "venc-set1";
1522 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
1523 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
1526 camsys: clock-controller@1a000000 {
1527 compatible = "mediatek,mt8192-camsys";
1529 #clock-cells = <1>;
1533 compatible = "mediatek,mt8192-smi-larb";
1535 mediatek,larb-id = <13>;
1539 clock-names = "apb", "smi";
1540 power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
1544 compatible = "mediatek,mt8192-smi-larb";
1546 mediatek,larb-id = <14>;
1550 clock-names = "apb", "smi";
1551 power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
1555 compatible = "mediatek,mt8192-smi-larb";
1557 mediatek,larb-id = <16>;
1561 clock-names = "apb", "smi";
1562 power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWA>;
1566 compatible = "mediatek,mt8192-smi-larb";
1568 mediatek,larb-id = <17>;
1572 clock-names = "apb", "smi";
1573 power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWB>;
1577 compatible = "mediatek,mt8192-smi-larb";
1579 mediatek,larb-id = <18>;
1583 clock-names = "apb", "smi";
1584 power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWC>;
1587 camsys_rawa: clock-controller@1a04f000 {
1588 compatible = "mediatek,mt8192-camsys_rawa";
1590 #clock-cells = <1>;
1593 camsys_rawb: clock-controller@1a06f000 {
1594 compatible = "mediatek,mt8192-camsys_rawb";
1596 #clock-cells = <1>;
1599 camsys_rawc: clock-controller@1a08f000 {
1600 compatible = "mediatek,mt8192-camsys_rawc";
1602 #clock-cells = <1>;
1605 ipesys: clock-controller@1b000000 {
1606 compatible = "mediatek,mt8192-ipesys";
1608 #clock-cells = <1>;
1612 compatible = "mediatek,mt8192-smi-larb";
1614 mediatek,larb-id = <20>;
1618 clock-names = "apb", "smi";
1619 power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
1623 compatible = "mediatek,mt8192-smi-larb";
1625 mediatek,larb-id = <19>;
1629 clock-names = "apb", "smi";
1630 power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
1633 mdpsys: clock-controller@1f000000 {
1634 compatible = "mediatek,mt8192-mdpsys";
1636 #clock-cells = <1>;
1640 compatible = "mediatek,mt8192-smi-larb";
1642 mediatek,larb-id = <2>;
1646 clock-names = "apb", "smi";
1647 power-domains = <&spm MT8192_POWER_DOMAIN_MDP>;