Lines Matching +full:ppi +full:- +full:partitions
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
6 /dts-v1/;
7 #include <dt-bindings/clock/mt8186-clk.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/mt8186-pinfunc.h>
11 #include <dt-bindings/power/mt8186-power.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/reset/mt8186-resets.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
65 compatible = "arm,cortex-a55";
67 enable-method = "psci";
68 clock-frequency = <2000000000>;
69 capacity-dmips-mhz = <382>;
70 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
71 next-level-cache = <&l2_0>;
72 #cooling-cells = <2>;
77 compatible = "arm,cortex-a55";
79 enable-method = "psci";
80 clock-frequency = <2000000000>;
81 capacity-dmips-mhz = <382>;
82 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
83 next-level-cache = <&l2_0>;
84 #cooling-cells = <2>;
89 compatible = "arm,cortex-a55";
91 enable-method = "psci";
92 clock-frequency = <2000000000>;
93 capacity-dmips-mhz = <382>;
94 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
95 next-level-cache = <&l2_0>;
96 #cooling-cells = <2>;
101 compatible = "arm,cortex-a55";
103 enable-method = "psci";
104 clock-frequency = <2000000000>;
105 capacity-dmips-mhz = <382>;
106 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
107 next-level-cache = <&l2_0>;
108 #cooling-cells = <2>;
113 compatible = "arm,cortex-a55";
115 enable-method = "psci";
116 clock-frequency = <2000000000>;
117 capacity-dmips-mhz = <382>;
118 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
119 next-level-cache = <&l2_0>;
120 #cooling-cells = <2>;
125 compatible = "arm,cortex-a55";
127 enable-method = "psci";
128 clock-frequency = <2000000000>;
129 capacity-dmips-mhz = <382>;
130 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
131 next-level-cache = <&l2_0>;
132 #cooling-cells = <2>;
137 compatible = "arm,cortex-a76";
139 enable-method = "psci";
140 clock-frequency = <2050000000>;
141 capacity-dmips-mhz = <1024>;
142 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
143 next-level-cache = <&l2_1>;
144 #cooling-cells = <2>;
149 compatible = "arm,cortex-a76";
151 enable-method = "psci";
152 clock-frequency = <2050000000>;
153 capacity-dmips-mhz = <1024>;
154 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
155 next-level-cache = <&l2_1>;
156 #cooling-cells = <2>;
159 idle-states {
160 entry-method = "psci";
162 cpu_off_l: cpu-off-l {
163 compatible = "arm,idle-state";
164 arm,psci-suspend-param = <0x00010001>;
165 local-timer-stop;
166 entry-latency-us = <50>;
167 exit-latency-us = <100>;
168 min-residency-us = <1600>;
171 cpu_off_b: cpu-off-b {
172 compatible = "arm,idle-state";
173 arm,psci-suspend-param = <0x00010001>;
174 local-timer-stop;
175 entry-latency-us = <50>;
176 exit-latency-us = <100>;
177 min-residency-us = <1400>;
180 cluster_off_l: cluster-off-l {
181 compatible = "arm,idle-state";
182 arm,psci-suspend-param = <0x01010001>;
183 local-timer-stop;
184 entry-latency-us = <100>;
185 exit-latency-us = <250>;
186 min-residency-us = <2100>;
189 cluster_off_b: cluster-off-b {
190 compatible = "arm,idle-state";
191 arm,psci-suspend-param = <0x01010001>;
192 local-timer-stop;
193 entry-latency-us = <100>;
194 exit-latency-us = <250>;
195 min-residency-us = <1900>;
199 l2_0: l2-cache0 {
201 next-level-cache = <&l3_0>;
204 l2_1: l2-cache1 {
206 next-level-cache = <&l3_0>;
209 l3_0: l3-cache {
214 clk13m: oscillator-13m {
215 compatible = "fixed-clock";
216 #clock-cells = <0>;
217 clock-frequency = <13000000>;
218 clock-output-names = "clk13m";
221 clk26m: oscillator-26m {
222 compatible = "fixed-clock";
223 #clock-cells = <0>;
224 clock-frequency = <26000000>;
225 clock-output-names = "clk26m";
228 clk32k: oscillator-32k {
229 compatible = "fixed-clock";
230 #clock-cells = <0>;
231 clock-frequency = <32768>;
232 clock-output-names = "clk32k";
235 pmu-a55 {
236 compatible = "arm,cortex-a55-pmu";
237 interrupt-parent = <&gic>;
241 pmu-a76 {
242 compatible = "arm,cortex-a76-pmu";
243 interrupt-parent = <&gic>;
248 compatible = "arm,psci-1.0";
253 compatible = "arm,armv8-timer";
254 interrupt-parent = <&gic>;
262 #address-cells = <2>;
263 #size-cells = <2>;
264 compatible = "simple-bus";
267 gic: interrupt-controller@c000000 {
268 compatible = "arm,gic-v3";
269 #interrupt-cells = <4>;
270 #redistributor-regions = <1>;
271 interrupt-parent = <&gic>;
272 interrupt-controller;
277 ppi-partitions {
278 ppi_cluster0: interrupt-partition-0 {
282 ppi_cluster1: interrupt-partition-1 {
289 compatible = "mediatek,mt8186-mcusys", "syscon";
291 #clock-cells = <1>;
295 compatible = "mediatek,mt8186-topckgen", "syscon";
297 #clock-cells = <1>;
301 compatible = "mediatek,mt8186-infracfg_ao", "syscon";
303 #clock-cells = <1>;
304 #reset-cells = <1>;
308 compatible = "mediatek,mt8186-pericfg", "syscon";
313 compatible = "mediatek,mt8186-pinctrl";
322 reg-names = "iocfg0", "iocfg_lt", "iocfg_lm", "iocfg_lb",
324 gpio-controller;
325 #gpio-cells = <2>;
326 gpio-ranges = <&pio 0 0 185>;
327 interrupt-controller;
329 #interrupt-cells = <2>;
333 compatible = "mediatek,mt8186-wdt",
334 "mediatek,mt6589-wdt";
335 mediatek,disable-extrst;
337 #reset-cells = <1>;
341 compatible = "mediatek,mt8186-apmixedsys", "syscon";
343 #clock-cells = <1>;
347 compatible = "mediatek,mt8186-pwrap", "syscon";
349 reg-names = "pwrap";
353 clock-names = "spi", "wrap";
357 compatible = "mediatek,mt8186-timer",
358 "mediatek,mt6765-timer";
365 compatible = "mediatek,mt8186-scp";
368 reg-names = "sram", "cfg";
373 compatible = "mediatek,mt8186-nor";
379 clock-names = "spi", "sf", "axi", "axi_s";
380 assigned-clocks = <&topckgen CLK_TOP_SPINOR>;
381 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3_D8>;
387 compatible = "mediatek,mt8186-auxadc", "mediatek,mt8173-auxadc";
389 #io-channel-cells = <1>;
391 clock-names = "main";
395 compatible = "mediatek,mt8186-uart",
396 "mediatek,mt6577-uart";
400 clock-names = "baud", "bus";
405 compatible = "mediatek,mt8186-uart",
406 "mediatek,mt6577-uart";
410 clock-names = "baud", "bus";
415 compatible = "mediatek,mt8186-i2c";
421 clock-names = "main", "dma";
422 clock-div = <1>;
423 #address-cells = <1>;
424 #size-cells = <0>;
429 compatible = "mediatek,mt8186-i2c";
435 clock-names = "main", "dma";
436 clock-div = <1>;
437 #address-cells = <1>;
438 #size-cells = <0>;
443 compatible = "mediatek,mt8186-i2c";
449 clock-names = "main", "dma";
450 clock-div = <1>;
451 #address-cells = <1>;
452 #size-cells = <0>;
457 compatible = "mediatek,mt8186-i2c";
463 clock-names = "main", "dma";
464 clock-div = <1>;
465 #address-cells = <1>;
466 #size-cells = <0>;
471 compatible = "mediatek,mt8186-i2c";
477 clock-names = "main", "dma";
478 clock-div = <1>;
479 #address-cells = <1>;
480 #size-cells = <0>;
485 compatible = "mediatek,mt8186-i2c";
491 clock-names = "main", "dma";
492 clock-div = <1>;
493 #address-cells = <1>;
494 #size-cells = <0>;
499 compatible = "mediatek,mt8186-i2c";
505 clock-names = "main", "dma";
506 clock-div = <1>;
507 #address-cells = <1>;
508 #size-cells = <0>;
513 compatible = "mediatek,mt8186-i2c";
519 clock-names = "main", "dma";
520 clock-div = <1>;
521 #address-cells = <1>;
522 #size-cells = <0>;
527 compatible = "mediatek,mt8186-i2c";
533 clock-names = "main", "dma";
534 clock-div = <1>;
535 #address-cells = <1>;
536 #size-cells = <0>;
541 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
542 #address-cells = <1>;
543 #size-cells = <0>;
549 clock-names = "parent-clk", "sel-clk", "spi-clk";
554 compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm";
557 #pwm-cells = <2>;
560 clock-names = "main", "mm";
565 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
566 #address-cells = <1>;
567 #size-cells = <0>;
573 clock-names = "parent-clk", "sel-clk", "spi-clk";
578 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
579 #address-cells = <1>;
580 #size-cells = <0>;
586 clock-names = "parent-clk", "sel-clk", "spi-clk";
591 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
592 #address-cells = <1>;
593 #size-cells = <0>;
599 clock-names = "parent-clk", "sel-clk", "spi-clk";
604 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
605 #address-cells = <1>;
606 #size-cells = <0>;
612 clock-names = "parent-clk", "sel-clk", "spi-clk";
617 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
618 #address-cells = <1>;
619 #size-cells = <0>;
625 clock-names = "parent-clk", "sel-clk", "spi-clk";
629 imp_iic_wrap: clock-controller@11017000 {
630 compatible = "mediatek,mt8186-imp_iic_wrap";
632 #clock-cells = <1>;
636 compatible = "mediatek,mt8186-uart",
637 "mediatek,mt6577-uart";
641 clock-names = "baud", "bus";
646 compatible = "mediatek,mt8186-i2c";
652 clock-names = "main", "dma";
653 clock-div = <1>;
654 #address-cells = <1>;
655 #size-cells = <0>;
660 compatible = "mediatek,mt8186-mmc",
661 "mediatek,mt8183-mmc";
667 clock-names = "source", "hclk", "source_cg";
669 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0>;
670 assigned-clock-parents = <&apmixedsys CLK_APMIXED_MSDCPLL>;
675 compatible = "mediatek,mt8186-mmc",
676 "mediatek,mt8183-mmc";
682 clock-names = "source", "hclk", "source_cg";
684 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
685 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
689 u3phy0: t-phy@11c80000 {
690 compatible = "mediatek,mt8186-tphy",
691 "mediatek,generic-tphy-v2";
692 #address-cells = <1>;
693 #size-cells = <1>;
697 u2port1: usb-phy@0 {
700 clock-names = "ref";
701 #phy-cells = <1>;
704 u3port1: usb-phy@700 {
707 clock-names = "ref";
708 #phy-cells = <1>;
712 u3phy1: t-phy@11ca0000 {
713 compatible = "mediatek,mt8186-tphy",
714 "mediatek,generic-tphy-v2";
715 #address-cells = <1>;
716 #size-cells = <1>;
720 u2port0: usb-phy@0 {
723 clock-names = "ref";
724 #phy-cells = <1>;
730 compatible = "mediatek,mt8186-efuse", "mediatek,efuse";
732 #address-cells = <1>;
733 #size-cells = <1>;
736 mipi_tx0: dsi-phy@11cc0000 {
737 compatible = "mediatek,mt8183-mipi-tx";
740 #clock-cells = <0>;
741 #phy-cells = <0>;
742 clock-output-names = "mipi_tx0_pll";
746 mfgsys: clock-controller@13000000 {
747 compatible = "mediatek,mt8186-mfgsys";
749 #clock-cells = <1>;
753 compatible = "mediatek,mt8186-mmsys", "syscon";
755 #clock-cells = <1>;
756 #reset-cells = <1>;
759 wpesys: clock-controller@14020000 {
760 compatible = "mediatek,mt8186-wpesys";
762 #clock-cells = <1>;
765 imgsys1: clock-controller@15020000 {
766 compatible = "mediatek,mt8186-imgsys1";
768 #clock-cells = <1>;
771 imgsys2: clock-controller@15820000 {
772 compatible = "mediatek,mt8186-imgsys2";
774 #clock-cells = <1>;
777 vdecsys: clock-controller@1602f000 {
778 compatible = "mediatek,mt8186-vdecsys";
780 #clock-cells = <1>;
783 vencsys: clock-controller@17000000 {
784 compatible = "mediatek,mt8186-vencsys";
786 #clock-cells = <1>;
789 camsys: clock-controller@1a000000 {
790 compatible = "mediatek,mt8186-camsys";
792 #clock-cells = <1>;
795 camsys_rawa: clock-controller@1a04f000 {
796 compatible = "mediatek,mt8186-camsys_rawa";
798 #clock-cells = <1>;
801 camsys_rawb: clock-controller@1a06f000 {
802 compatible = "mediatek,mt8186-camsys_rawb";
804 #clock-cells = <1>;
807 mdpsys: clock-controller@1b000000 {
808 compatible = "mediatek,mt8186-mdpsys";
810 #clock-cells = <1>;
813 ipesys: clock-controller@1c000000 {
814 compatible = "mediatek,mt8186-ipesys";
816 #clock-cells = <1>;