Lines Matching +full:0 +full:x10002600
23 #size-cells = <0>;
63 cpu0: cpu@0 {
66 reg = <0x000>;
78 reg = <0x100>;
90 reg = <0x200>;
102 reg = <0x300>;
114 reg = <0x400>;
126 reg = <0x500>;
138 reg = <0x600>;
150 reg = <0x700>;
164 arm,psci-suspend-param = <0x00010001>;
173 arm,psci-suspend-param = <0x00010001>;
182 arm,psci-suspend-param = <0x01010001>;
191 arm,psci-suspend-param = <0x01010001>;
216 #clock-cells = <0>;
223 #clock-cells = <0>;
230 #clock-cells = <0>;
255 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
256 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
257 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
258 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
273 reg = <0 0x0c000000 0 0x40000>,
274 <0 0x0c040000 0 0x200000>;
275 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
278 ppi_cluster0: interrupt-partition-0 {
290 reg = <0 0xc53a000 0 0x1000>;
296 reg = <0 0x10000000 0 0x1000>;
302 reg = <0 0x10001000 0 0x1000>;
309 reg = <0 0x10003000 0 0x1000>;
314 reg = <0 0x10005000 0 0x1000>,
315 <0 0x10002000 0 0x0200>,
316 <0 0x10002200 0 0x0200>,
317 <0 0x10002400 0 0x0200>,
318 <0 0x10002600 0 0x0200>,
319 <0 0x10002a00 0 0x0200>,
320 <0 0x10002c00 0 0x0200>,
321 <0 0x1000b000 0 0x1000>;
326 gpio-ranges = <&pio 0 0 185>;
328 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
336 reg = <0 0x10007000 0 0x1000>;
342 reg = <0 0x1000c000 0 0x1000>;
348 reg = <0 0x1000d000 0 0x1000>;
350 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>;
359 reg = <0 0x10017000 0 0x1000>;
360 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>;
366 reg = <0 0x10500000 0 0x40000>,
367 <0 0x105c0000 0 0x19080>;
369 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>;
374 reg = <0 0x11000000 0 0x1000>;
382 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>;
388 reg = <0 0x11001000 0 0x1000>;
397 reg = <0 0x11002000 0 0x1000>;
398 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
407 reg = <0 0x11003000 0 0x1000>;
408 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
416 reg = <0 0x11007000 0 0x1000>,
417 <0 0x10200100 0 0x100>;
418 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
424 #size-cells = <0>;
430 reg = <0 0x11008000 0 0x1000>,
431 <0 0x10200200 0 0x100>;
432 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
438 #size-cells = <0>;
444 reg = <0 0x11009000 0 0x1000>,
445 <0 0x10200300 0 0x180>;
446 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>;
452 #size-cells = <0>;
458 reg = <0 0x1100f000 0 0x1000>,
459 <0 0x10200480 0 0x100>;
460 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
466 #size-cells = <0>;
472 reg = <0 0x11011000 0 0x1000>,
473 <0 0x10200580 0 0x180>;
474 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
480 #size-cells = <0>;
486 reg = <0 0x11016000 0 0x1000>,
487 <0 0x10200700 0 0x100>;
488 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>;
494 #size-cells = <0>;
500 reg = <0 0x1100d000 0 0x1000>,
501 <0 0x10200800 0 0x100>;
502 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>;
508 #size-cells = <0>;
514 reg = <0 0x11004000 0 0x1000>,
515 <0 0x10200900 0 0x180>;
516 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
522 #size-cells = <0>;
528 reg = <0 0x11005000 0 0x1000>,
529 <0 0x10200A80 0 0x180>;
530 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
536 #size-cells = <0>;
543 #size-cells = <0>;
544 reg = <0 0x1100a000 0 0x1000>;
545 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH 0>;
555 reg = <0 0x1100e000 0 0x1000>;
556 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>;
567 #size-cells = <0>;
568 reg = <0 0x11010000 0 0x1000>;
569 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH 0>;
580 #size-cells = <0>;
581 reg = <0 0x11012000 0 0x1000>;
582 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>;
593 #size-cells = <0>;
594 reg = <0 0x11013000 0 0x1000>;
595 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>;
606 #size-cells = <0>;
607 reg = <0 0x11014000 0 0x1000>;
608 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
619 #size-cells = <0>;
620 reg = <0 0x11015000 0 0x1000>;
621 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
631 reg = <0 0x11017000 0 0x1000>;
638 reg = <0 0x11018000 0 0x1000>;
639 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>;
647 reg = <0 0x11019000 0 0x1000>,
648 <0 0x10200c00 0 0x180>;
649 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>;
655 #size-cells = <0>;
662 reg = <0 0x11230000 0 0x1000>,
663 <0 0x11cd0000 0 0x1000>;
668 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
677 reg = <0 0x11240000 0 0x1000>,
678 <0 0x11c90000 0 0x1000>;
683 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
694 ranges = <0x0 0x0 0x11c80000 0x1000>;
697 u2port1: usb-phy@0 {
698 reg = <0x0 0x700>;
705 reg = <0x700 0x900>;
717 ranges = <0x0 0x0 0x11ca0000 0x1000>;
720 u2port0: usb-phy@0 {
721 reg = <0x0 0x700>;
725 mediatek,discth = <0x8>;
731 reg = <0 0x11cb0000 0 0x1000>;
738 reg = <0 0x11cc0000 0 0x1000>;
740 #clock-cells = <0>;
741 #phy-cells = <0>;
748 reg = <0 0x13000000 0 0x1000>;
754 reg = <0 0x14000000 0 0x1000>;
761 reg = <0 0x14020000 0 0x1000>;
767 reg = <0 0x15020000 0 0x1000>;
773 reg = <0 0x15820000 0 0x1000>;
779 reg = <0 0x1602f000 0 0x1000>;
785 reg = <0 0x17000000 0 0x1000>;
791 reg = <0 0x1a000000 0 0x1000>;
797 reg = <0 0x1a04f000 0 0x1000>;
803 reg = <0 0x1a06f000 0 0x1000>;
809 reg = <0 0x1b000000 0 0x1000>;
815 reg = <0 0x1c000000 0 0x1000>;