Lines Matching refs:mmsys

825 						 <&mmsys CLK_MM_SMI_COMMON>,
826 						 <&mmsys CLK_MM_SMI_LARB0>,
827 						 <&mmsys CLK_MM_SMI_LARB1>,
828 						 <&mmsys CLK_MM_GALS_COMM0>,
829 						 <&mmsys CLK_MM_GALS_COMM1>,
830 						 <&mmsys CLK_MM_GALS_CCU2MM>,
831 						 <&mmsys CLK_MM_GALS_IPU12MM>,
832 						 <&mmsys CLK_MM_GALS_IMG2MM>,
833 						 <&mmsys CLK_MM_GALS_CAM2MM>,
834 						 <&mmsys CLK_MM_GALS_IPU2MM>;
1692 		mmsys: syscon@14000000 {  label
1693 			compatible = "mediatek,mt8183-mmsys", "syscon";
1709 			clocks = <&mmsys CLK_MM_MDP_RDMA0>,
1710 				 <&mmsys CLK_MM_MDP_RSZ1>;
1722 			clocks = <&mmsys CLK_MM_MDP_RSZ0>;
1731 			clocks = <&mmsys CLK_MM_MDP_RSZ1>;
1741 			clocks = <&mmsys CLK_MM_MDP_WROT0>;
1752 			clocks = <&mmsys CLK_MM_MDP_WDMA0>;
1761 			clocks = <&mmsys CLK_MM_DISP_OVL0>;
1771 			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
1781 			clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
1791 			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
1802 			clocks = <&mmsys CLK_MM_DISP_RDMA1>;
1814 			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
1823 			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
1832 			clocks = <&mmsys CLK_MM_DISP_AAL0>;
1841 			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
1850 			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
1859 			clocks = <&mmsys CLK_MM_DSI0_MM>,
1860 				 <&mmsys CLK_MM_DSI0_IF>,
1863 			resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;
1882 			clocks = <&mmsys CLK_MM_SMI_LARB0>,
1883 				 <&mmsys CLK_MM_SMI_LARB0>;
1891 			clocks = <&mmsys CLK_MM_SMI_COMMON>,
1892 				 <&mmsys CLK_MM_SMI_COMMON>,
1893 				 <&mmsys CLK_MM_GALS_COMM0>,
1894 				 <&mmsys CLK_MM_GALS_COMM1>;
1905 			clocks = <&mmsys CLK_MM_MDP_CCORR>;
1919 				 <&mmsys CLK_MM_GALS_IMG2MM>;
1929 				 <&mmsys CLK_MM_GALS_IPU2MM>;
2011 				 <&mmsys CLK_MM_GALS_CAM2MM>;
2021 				 <&mmsys CLK_MM_GALS_IPU12MM>;