Lines Matching +full:mediatek +full:- +full:thermal
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (c) 2018 MediaTek Inc.
4 * Author: Ben Ho <ben.ho@mediatek.com>
5 * Erin Lo <erin.lo@mediatek.com>
8 #include <dt-bindings/clock/mt8183-clk.h>
9 #include <dt-bindings/gce/mt8183-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8183-larb-port.h>
13 #include <dt-bindings/power/mt8183-power.h>
14 #include <dt-bindings/reset/mt8183-resets.h>
15 #include <dt-bindings/phy/phy.h>
16 #include <dt-bindings/thermal/thermal.h>
17 #include <dt-bindings/pinctrl/mt8183-pinfunc.h>
20 compatible = "mediatek,mt8183";
21 interrupt-parent = <&sysirq>;
22 #address-cells = <2>;
23 #size-cells = <2>;
39 ovl-2l0 = &ovl_2l0;
40 ovl-2l1 = &ovl_2l1;
45 cluster0_opp: opp-table-cluster0 {
46 compatible = "operating-points-v2";
47 opp-shared;
48 opp0-793000000 {
49 opp-hz = /bits/ 64 <793000000>;
50 opp-microvolt = <650000>;
51 required-opps = <&opp2_00>;
53 opp0-910000000 {
54 opp-hz = /bits/ 64 <910000000>;
55 opp-microvolt = <687500>;
56 required-opps = <&opp2_01>;
58 opp0-1014000000 {
59 opp-hz = /bits/ 64 <1014000000>;
60 opp-microvolt = <718750>;
61 required-opps = <&opp2_02>;
63 opp0-1131000000 {
64 opp-hz = /bits/ 64 <1131000000>;
65 opp-microvolt = <756250>;
66 required-opps = <&opp2_03>;
68 opp0-1248000000 {
69 opp-hz = /bits/ 64 <1248000000>;
70 opp-microvolt = <800000>;
71 required-opps = <&opp2_04>;
73 opp0-1326000000 {
74 opp-hz = /bits/ 64 <1326000000>;
75 opp-microvolt = <818750>;
76 required-opps = <&opp2_05>;
78 opp0-1417000000 {
79 opp-hz = /bits/ 64 <1417000000>;
80 opp-microvolt = <850000>;
81 required-opps = <&opp2_06>;
83 opp0-1508000000 {
84 opp-hz = /bits/ 64 <1508000000>;
85 opp-microvolt = <868750>;
86 required-opps = <&opp2_07>;
88 opp0-1586000000 {
89 opp-hz = /bits/ 64 <1586000000>;
90 opp-microvolt = <893750>;
91 required-opps = <&opp2_08>;
93 opp0-1625000000 {
94 opp-hz = /bits/ 64 <1625000000>;
95 opp-microvolt = <906250>;
96 required-opps = <&opp2_09>;
98 opp0-1677000000 {
99 opp-hz = /bits/ 64 <1677000000>;
100 opp-microvolt = <931250>;
101 required-opps = <&opp2_10>;
103 opp0-1716000000 {
104 opp-hz = /bits/ 64 <1716000000>;
105 opp-microvolt = <943750>;
106 required-opps = <&opp2_11>;
108 opp0-1781000000 {
109 opp-hz = /bits/ 64 <1781000000>;
110 opp-microvolt = <975000>;
111 required-opps = <&opp2_12>;
113 opp0-1846000000 {
114 opp-hz = /bits/ 64 <1846000000>;
115 opp-microvolt = <1000000>;
116 required-opps = <&opp2_13>;
118 opp0-1924000000 {
119 opp-hz = /bits/ 64 <1924000000>;
120 opp-microvolt = <1025000>;
121 required-opps = <&opp2_14>;
123 opp0-1989000000 {
124 opp-hz = /bits/ 64 <1989000000>;
125 opp-microvolt = <1050000>;
126 required-opps = <&opp2_15>;
129 cluster1_opp: opp-table-cluster1 {
130 compatible = "operating-points-v2";
131 opp-shared;
132 opp1-793000000 {
133 opp-hz = /bits/ 64 <793000000>;
134 opp-microvolt = <700000>;
135 required-opps = <&opp2_00>;
137 opp1-910000000 {
138 opp-hz = /bits/ 64 <910000000>;
139 opp-microvolt = <725000>;
140 required-opps = <&opp2_01>;
142 opp1-1014000000 {
143 opp-hz = /bits/ 64 <1014000000>;
144 opp-microvolt = <750000>;
145 required-opps = <&opp2_02>;
147 opp1-1131000000 {
148 opp-hz = /bits/ 64 <1131000000>;
149 opp-microvolt = <775000>;
150 required-opps = <&opp2_03>;
152 opp1-1248000000 {
153 opp-hz = /bits/ 64 <1248000000>;
154 opp-microvolt = <800000>;
155 required-opps = <&opp2_04>;
157 opp1-1326000000 {
158 opp-hz = /bits/ 64 <1326000000>;
159 opp-microvolt = <825000>;
160 required-opps = <&opp2_05>;
162 opp1-1417000000 {
163 opp-hz = /bits/ 64 <1417000000>;
164 opp-microvolt = <850000>;
165 required-opps = <&opp2_06>;
167 opp1-1508000000 {
168 opp-hz = /bits/ 64 <1508000000>;
169 opp-microvolt = <875000>;
170 required-opps = <&opp2_07>;
172 opp1-1586000000 {
173 opp-hz = /bits/ 64 <1586000000>;
174 opp-microvolt = <900000>;
175 required-opps = <&opp2_08>;
177 opp1-1625000000 {
178 opp-hz = /bits/ 64 <1625000000>;
179 opp-microvolt = <912500>;
180 required-opps = <&opp2_09>;
182 opp1-1677000000 {
183 opp-hz = /bits/ 64 <1677000000>;
184 opp-microvolt = <931250>;
185 required-opps = <&opp2_10>;
187 opp1-1716000000 {
188 opp-hz = /bits/ 64 <1716000000>;
189 opp-microvolt = <950000>;
190 required-opps = <&opp2_11>;
192 opp1-1781000000 {
193 opp-hz = /bits/ 64 <1781000000>;
194 opp-microvolt = <975000>;
195 required-opps = <&opp2_12>;
197 opp1-1846000000 {
198 opp-hz = /bits/ 64 <1846000000>;
199 opp-microvolt = <1000000>;
200 required-opps = <&opp2_13>;
202 opp1-1924000000 {
203 opp-hz = /bits/ 64 <1924000000>;
204 opp-microvolt = <1025000>;
205 required-opps = <&opp2_14>;
207 opp1-1989000000 {
208 opp-hz = /bits/ 64 <1989000000>;
209 opp-microvolt = <1050000>;
210 required-opps = <&opp2_15>;
214 cci_opp: opp-table-cci {
215 compatible = "operating-points-v2";
216 opp-shared;
217 opp2_00: opp-273000000 {
218 opp-hz = /bits/ 64 <273000000>;
219 opp-microvolt = <650000>;
221 opp2_01: opp-338000000 {
222 opp-hz = /bits/ 64 <338000000>;
223 opp-microvolt = <687500>;
225 opp2_02: opp-403000000 {
226 opp-hz = /bits/ 64 <403000000>;
227 opp-microvolt = <718750>;
229 opp2_03: opp-463000000 {
230 opp-hz = /bits/ 64 <463000000>;
231 opp-microvolt = <756250>;
233 opp2_04: opp-546000000 {
234 opp-hz = /bits/ 64 <546000000>;
235 opp-microvolt = <800000>;
237 opp2_05: opp-624000000 {
238 opp-hz = /bits/ 64 <624000000>;
239 opp-microvolt = <818750>;
241 opp2_06: opp-689000000 {
242 opp-hz = /bits/ 64 <689000000>;
243 opp-microvolt = <850000>;
245 opp2_07: opp-767000000 {
246 opp-hz = /bits/ 64 <767000000>;
247 opp-microvolt = <868750>;
249 opp2_08: opp-845000000 {
250 opp-hz = /bits/ 64 <845000000>;
251 opp-microvolt = <893750>;
253 opp2_09: opp-871000000 {
254 opp-hz = /bits/ 64 <871000000>;
255 opp-microvolt = <906250>;
257 opp2_10: opp-923000000 {
258 opp-hz = /bits/ 64 <923000000>;
259 opp-microvolt = <931250>;
261 opp2_11: opp-962000000 {
262 opp-hz = /bits/ 64 <962000000>;
263 opp-microvolt = <943750>;
265 opp2_12: opp-1027000000 {
266 opp-hz = /bits/ 64 <1027000000>;
267 opp-microvolt = <975000>;
269 opp2_13: opp-1092000000 {
270 opp-hz = /bits/ 64 <1092000000>;
271 opp-microvolt = <1000000>;
273 opp2_14: opp-1144000000 {
274 opp-hz = /bits/ 64 <1144000000>;
275 opp-microvolt = <1025000>;
277 opp2_15: opp-1196000000 {
278 opp-hz = /bits/ 64 <1196000000>;
279 opp-microvolt = <1050000>;
284 compatible = "mediatek,mt8183-cci";
287 clock-names = "cci", "intermediate";
288 operating-points-v2 = <&cci_opp>;
292 #address-cells = <1>;
293 #size-cells = <0>;
295 cpu-map {
329 compatible = "arm,cortex-a53";
331 enable-method = "psci";
332 capacity-dmips-mhz = <741>;
333 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
336 clock-names = "cpu", "intermediate";
337 operating-points-v2 = <&cluster0_opp>;
338 dynamic-power-coefficient = <84>;
339 #cooling-cells = <2>;
340 mediatek,cci = <&cci>;
345 compatible = "arm,cortex-a53";
347 enable-method = "psci";
348 capacity-dmips-mhz = <741>;
349 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
352 clock-names = "cpu", "intermediate";
353 operating-points-v2 = <&cluster0_opp>;
354 dynamic-power-coefficient = <84>;
355 #cooling-cells = <2>;
356 mediatek,cci = <&cci>;
361 compatible = "arm,cortex-a53";
363 enable-method = "psci";
364 capacity-dmips-mhz = <741>;
365 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
368 clock-names = "cpu", "intermediate";
369 operating-points-v2 = <&cluster0_opp>;
370 dynamic-power-coefficient = <84>;
371 #cooling-cells = <2>;
372 mediatek,cci = <&cci>;
377 compatible = "arm,cortex-a53";
379 enable-method = "psci";
380 capacity-dmips-mhz = <741>;
381 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
384 clock-names = "cpu", "intermediate";
385 operating-points-v2 = <&cluster0_opp>;
386 dynamic-power-coefficient = <84>;
387 #cooling-cells = <2>;
388 mediatek,cci = <&cci>;
393 compatible = "arm,cortex-a73";
395 enable-method = "psci";
396 capacity-dmips-mhz = <1024>;
397 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
400 clock-names = "cpu", "intermediate";
401 operating-points-v2 = <&cluster1_opp>;
402 dynamic-power-coefficient = <211>;
403 #cooling-cells = <2>;
404 mediatek,cci = <&cci>;
409 compatible = "arm,cortex-a73";
411 enable-method = "psci";
412 capacity-dmips-mhz = <1024>;
413 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
416 clock-names = "cpu", "intermediate";
417 operating-points-v2 = <&cluster1_opp>;
418 dynamic-power-coefficient = <211>;
419 #cooling-cells = <2>;
420 mediatek,cci = <&cci>;
425 compatible = "arm,cortex-a73";
427 enable-method = "psci";
428 capacity-dmips-mhz = <1024>;
429 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
432 clock-names = "cpu", "intermediate";
433 operating-points-v2 = <&cluster1_opp>;
434 dynamic-power-coefficient = <211>;
435 #cooling-cells = <2>;
436 mediatek,cci = <&cci>;
441 compatible = "arm,cortex-a73";
443 enable-method = "psci";
444 capacity-dmips-mhz = <1024>;
445 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
448 clock-names = "cpu", "intermediate";
449 operating-points-v2 = <&cluster1_opp>;
450 dynamic-power-coefficient = <211>;
451 #cooling-cells = <2>;
452 mediatek,cci = <&cci>;
455 idle-states {
456 entry-method = "psci";
458 CPU_SLEEP: cpu-sleep {
459 compatible = "arm,idle-state";
460 local-timer-stop;
461 arm,psci-suspend-param = <0x00010001>;
462 entry-latency-us = <200>;
463 exit-latency-us = <200>;
464 min-residency-us = <800>;
467 CLUSTER_SLEEP0: cluster-sleep-0 {
468 compatible = "arm,idle-state";
469 local-timer-stop;
470 arm,psci-suspend-param = <0x01010001>;
471 entry-latency-us = <250>;
472 exit-latency-us = <400>;
473 min-residency-us = <1000>;
475 CLUSTER_SLEEP1: cluster-sleep-1 {
476 compatible = "arm,idle-state";
477 local-timer-stop;
478 arm,psci-suspend-param = <0x01010001>;
479 entry-latency-us = <250>;
480 exit-latency-us = <400>;
481 min-residency-us = <1300>;
486 gpu_opp_table: opp-table-0 {
487 compatible = "operating-points-v2";
488 opp-shared;
490 opp-300000000 {
491 opp-hz = /bits/ 64 <300000000>;
492 opp-microvolt = <625000>, <850000>;
495 opp-320000000 {
496 opp-hz = /bits/ 64 <320000000>;
497 opp-microvolt = <631250>, <850000>;
500 opp-340000000 {
501 opp-hz = /bits/ 64 <340000000>;
502 opp-microvolt = <637500>, <850000>;
505 opp-360000000 {
506 opp-hz = /bits/ 64 <360000000>;
507 opp-microvolt = <643750>, <850000>;
510 opp-380000000 {
511 opp-hz = /bits/ 64 <380000000>;
512 opp-microvolt = <650000>, <850000>;
515 opp-400000000 {
516 opp-hz = /bits/ 64 <400000000>;
517 opp-microvolt = <656250>, <850000>;
520 opp-420000000 {
521 opp-hz = /bits/ 64 <420000000>;
522 opp-microvolt = <662500>, <850000>;
525 opp-460000000 {
526 opp-hz = /bits/ 64 <460000000>;
527 opp-microvolt = <675000>, <850000>;
530 opp-500000000 {
531 opp-hz = /bits/ 64 <500000000>;
532 opp-microvolt = <687500>, <850000>;
535 opp-540000000 {
536 opp-hz = /bits/ 64 <540000000>;
537 opp-microvolt = <700000>, <850000>;
540 opp-580000000 {
541 opp-hz = /bits/ 64 <580000000>;
542 opp-microvolt = <712500>, <850000>;
545 opp-620000000 {
546 opp-hz = /bits/ 64 <620000000>;
547 opp-microvolt = <725000>, <850000>;
550 opp-653000000 {
551 opp-hz = /bits/ 64 <653000000>;
552 opp-microvolt = <743750>, <850000>;
555 opp-698000000 {
556 opp-hz = /bits/ 64 <698000000>;
557 opp-microvolt = <768750>, <868750>;
560 opp-743000000 {
561 opp-hz = /bits/ 64 <743000000>;
562 opp-microvolt = <793750>, <893750>;
565 opp-800000000 {
566 opp-hz = /bits/ 64 <800000000>;
567 opp-microvolt = <825000>, <925000>;
571 pmu-a53 {
572 compatible = "arm,cortex-a53-pmu";
573 interrupt-parent = <&gic>;
577 pmu-a73 {
578 compatible = "arm,cortex-a73-pmu";
579 interrupt-parent = <&gic>;
584 compatible = "arm,psci-1.0";
589 compatible = "fixed-clock";
590 #clock-cells = <0>;
591 clock-frequency = <26000000>;
592 clock-output-names = "clk26m";
596 compatible = "arm,armv8-timer";
597 interrupt-parent = <&gic>;
605 #address-cells = <2>;
606 #size-cells = <2>;
607 compatible = "simple-bus";
611 compatible = "mediatek,mt8183-efuse",
612 "mediatek,efuse";
614 #address-cells = <1>;
615 #size-cells = <1>;
619 gic: interrupt-controller@c000000 {
620 compatible = "arm,gic-v3";
621 #interrupt-cells = <4>;
622 interrupt-parent = <&gic>;
623 interrupt-controller;
631 ppi-partitions {
632 ppi_cluster0: interrupt-partition-0 {
635 ppi_cluster1: interrupt-partition-1 {
642 compatible = "mediatek,mt8183-mcucfg", "syscon";
644 #clock-cells = <1>;
647 sysirq: interrupt-controller@c530a80 {
648 compatible = "mediatek,mt8183-sysirq",
649 "mediatek,mt6577-sysirq";
650 interrupt-controller;
651 #interrupt-cells = <3>;
652 interrupt-parent = <&gic>;
656 cpu_debug0: cpu-debug@d410000 {
657 compatible = "arm,coresight-cpu-debug", "arm,primecell";
660 clock-names = "apb_pclk";
664 cpu_debug1: cpu-debug@d510000 {
665 compatible = "arm,coresight-cpu-debug", "arm,primecell";
668 clock-names = "apb_pclk";
672 cpu_debug2: cpu-debug@d610000 {
673 compatible = "arm,coresight-cpu-debug", "arm,primecell";
676 clock-names = "apb_pclk";
680 cpu_debug3: cpu-debug@d710000 {
681 compatible = "arm,coresight-cpu-debug", "arm,primecell";
684 clock-names = "apb_pclk";
688 cpu_debug4: cpu-debug@d810000 {
689 compatible = "arm,coresight-cpu-debug", "arm,primecell";
692 clock-names = "apb_pclk";
696 cpu_debug5: cpu-debug@d910000 {
697 compatible = "arm,coresight-cpu-debug", "arm,primecell";
700 clock-names = "apb_pclk";
704 cpu_debug6: cpu-debug@da10000 {
705 compatible = "arm,coresight-cpu-debug", "arm,primecell";
708 clock-names = "apb_pclk";
712 cpu_debug7: cpu-debug@db10000 {
713 compatible = "arm,coresight-cpu-debug", "arm,primecell";
716 clock-names = "apb_pclk";
721 compatible = "mediatek,mt8183-topckgen", "syscon";
723 #clock-cells = <1>;
727 compatible = "mediatek,mt8183-infracfg", "syscon";
729 #clock-cells = <1>;
730 #reset-cells = <1>;
734 compatible = "mediatek,mt8183-pericfg", "syscon";
736 #clock-cells = <1>;
740 compatible = "mediatek,mt8183-pinctrl";
751 reg-names = "iocfg0", "iocfg1", "iocfg2",
755 gpio-controller;
756 #gpio-cells = <2>;
757 gpio-ranges = <&pio 0 0 192>;
758 interrupt-controller;
760 #interrupt-cells = <2>;
764 compatible = "mediatek,mt8183-scpsys", "syscon", "simple-mfd";
768 spm: power-controller {
769 compatible = "mediatek,mt8183-power-controller";
770 #address-cells = <1>;
771 #size-cells = <0>;
772 #power-domain-cells = <1>;
775 power-domain@MT8183_POWER_DOMAIN_AUDIO {
780 clock-names = "audio", "audio1", "audio2";
781 #power-domain-cells = <0>;
784 power-domain@MT8183_POWER_DOMAIN_CONN {
786 mediatek,infracfg = <&infracfg>;
787 #power-domain-cells = <0>;
790 mfg_async: power-domain@MT8183_POWER_DOMAIN_MFG_ASYNC {
793 clock-names = "mfg";
794 #address-cells = <1>;
795 #size-cells = <0>;
796 #power-domain-cells = <1>;
798 mfg: power-domain@MT8183_POWER_DOMAIN_MFG {
800 #address-cells = <1>;
801 #size-cells = <0>;
802 #power-domain-cells = <1>;
804 power-domain@MT8183_POWER_DOMAIN_MFG_CORE0 {
806 #power-domain-cells = <0>;
809 power-domain@MT8183_POWER_DOMAIN_MFG_CORE1 {
811 #power-domain-cells = <0>;
814 power-domain@MT8183_POWER_DOMAIN_MFG_2D {
816 mediatek,infracfg = <&infracfg>;
817 #power-domain-cells = <0>;
822 power-domain@MT8183_POWER_DOMAIN_DISP {
835 clock-names = "mm", "mm-0", "mm-1", "mm-2", "mm-3",
836 "mm-4", "mm-5", "mm-6", "mm-7",
837 "mm-8", "mm-9";
838 mediatek,infracfg = <&infracfg>;
839 mediatek,smi = <&smi_common>;
840 #address-cells = <1>;
841 #size-cells = <0>;
842 #power-domain-cells = <1>;
844 power-domain@MT8183_POWER_DOMAIN_CAM {
854 clock-names = "cam", "cam-0", "cam-1",
855 "cam-2", "cam-3", "cam-4",
856 "cam-5", "cam-6";
857 mediatek,infracfg = <&infracfg>;
858 mediatek,smi = <&smi_common>;
859 #power-domain-cells = <0>;
862 power-domain@MT8183_POWER_DOMAIN_ISP {
867 clock-names = "isp", "isp-0", "isp-1";
868 mediatek,infracfg = <&infracfg>;
869 mediatek,smi = <&smi_common>;
870 #power-domain-cells = <0>;
873 power-domain@MT8183_POWER_DOMAIN_VDEC {
875 mediatek,smi = <&smi_common>;
876 #power-domain-cells = <0>;
879 power-domain@MT8183_POWER_DOMAIN_VENC {
881 mediatek,smi = <&smi_common>;
882 #power-domain-cells = <0>;
885 power-domain@MT8183_POWER_DOMAIN_VPU_TOP {
895 clock-names = "vpu", "vpu1", "vpu-0", "vpu-1",
896 "vpu-2", "vpu-3", "vpu-4", "vpu-5";
897 mediatek,infracfg = <&infracfg>;
898 mediatek,smi = <&smi_common>;
899 #address-cells = <1>;
900 #size-cells = <0>;
901 #power-domain-cells = <1>;
903 power-domain@MT8183_POWER_DOMAIN_VPU_CORE0 {
906 clock-names = "vpu2";
907 mediatek,infracfg = <&infracfg>;
908 #power-domain-cells = <0>;
911 power-domain@MT8183_POWER_DOMAIN_VPU_CORE1 {
914 clock-names = "vpu3";
915 mediatek,infracfg = <&infracfg>;
916 #power-domain-cells = <0>;
924 compatible = "mediatek,mt8183-wdt";
926 #reset-cells = <1>;
930 compatible = "mediatek,mt8183-apmixedsys", "syscon";
932 #clock-cells = <1>;
936 compatible = "mediatek,mt8183-pwrap";
938 reg-names = "pwrap";
942 clock-names = "spi", "wrap";
946 compatible = "mediatek,mt6779-keypad";
950 clock-names = "kpd";
955 compatible = "mediatek,mt8183-scp";
958 reg-names = "sram", "cfg";
961 clock-names = "main";
962 memory-region = <&scp_mem_reserved>;
967 compatible = "mediatek,mt8183-timer",
968 "mediatek,mt6765-timer";
972 clock-names = "clk13m";
976 compatible = "mediatek,mt8183-m4u";
979 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>,
981 #iommu-cells = <1>;
985 compatible = "mediatek,mt8183-gce";
988 #mbox-cells = <2>;
990 clock-names = "gce";
994 compatible = "mediatek,mt8183-auxadc",
995 "mediatek,mt8173-auxadc";
998 clock-names = "main";
999 #io-channel-cells = <1>;
1004 compatible = "mediatek,mt8183-uart",
1005 "mediatek,mt6577-uart";
1009 clock-names = "baud", "bus";
1014 compatible = "mediatek,mt8183-uart",
1015 "mediatek,mt6577-uart";
1019 clock-names = "baud", "bus";
1024 compatible = "mediatek,mt8183-uart",
1025 "mediatek,mt6577-uart";
1029 clock-names = "baud", "bus";
1034 compatible = "mediatek,mt8183-i2c";
1040 clock-names = "main", "dma";
1041 clock-div = <1>;
1042 #address-cells = <1>;
1043 #size-cells = <0>;
1048 compatible = "mediatek,mt8183-i2c";
1054 clock-names = "main", "dma";
1055 clock-div = <1>;
1056 #address-cells = <1>;
1057 #size-cells = <0>;
1062 compatible = "mediatek,mt8183-i2c";
1069 clock-names = "main", "dma","arb";
1070 clock-div = <1>;
1071 #address-cells = <1>;
1072 #size-cells = <0>;
1077 compatible = "mediatek,mt8183-i2c";
1084 clock-names = "main", "dma", "arb";
1085 clock-div = <1>;
1086 #address-cells = <1>;
1087 #size-cells = <0>;
1092 compatible = "mediatek,mt8183-spi";
1093 #address-cells = <1>;
1094 #size-cells = <0>;
1100 clock-names = "parent-clk", "sel-clk", "spi-clk";
1105 compatible = "mediatek,mt8183-svs";
1109 clock-names = "main";
1110 nvmem-cells = <&svs_calibration>,
1112 nvmem-cell-names = "svs-calibration-data",
1113 "t-calibration-data";
1116 thermal: thermal@1100b000 { label
1117 #thermal-sensor-cells = <1>;
1118 compatible = "mediatek,mt8183-thermal";
1122 clock-names = "therm", "auxadc";
1125 mediatek,auxadc = <&auxadc>;
1126 mediatek,apmixedsys = <&apmixedsys>;
1127 nvmem-cells = <&thermal_calibration>;
1128 nvmem-cell-names = "calibration-data";
1131 thermal_zones: thermal-zones {
1132 cpu_thermal: cpu-thermal {
1133 polling-delay-passive = <100>;
1134 polling-delay = <500>;
1135 thermal-sensors = <&thermal 0>;
1136 sustainable-power = <5000>;
1139 threshold: trip-point0 {
1145 target: trip-point1 {
1151 cpu_crit: cpu-crit {
1158 cooling-maps {
1161 cooling-device = <&cpu0
1177 cooling-device = <&cpu4
1195 /* The tzts1 ~ tzts6 don't need to thermal throttle */
1198 polling-delay-passive = <0>;
1199 polling-delay = <0>;
1200 thermal-sensors = <&thermal 1>;
1201 sustainable-power = <5000>;
1203 cooling-maps {};
1207 polling-delay-passive = <0>;
1208 polling-delay = <0>;
1209 thermal-sensors = <&thermal 2>;
1210 sustainable-power = <5000>;
1212 cooling-maps {};
1216 polling-delay-passive = <0>;
1217 polling-delay = <0>;
1218 thermal-sensors = <&thermal 3>;
1219 sustainable-power = <5000>;
1221 cooling-maps {};
1225 polling-delay-passive = <0>;
1226 polling-delay = <0>;
1227 thermal-sensors = <&thermal 4>;
1228 sustainable-power = <5000>;
1230 cooling-maps {};
1234 polling-delay-passive = <0>;
1235 polling-delay = <0>;
1236 thermal-sensors = <&thermal 5>;
1237 sustainable-power = <5000>;
1239 cooling-maps {};
1243 polling-delay-passive = <0>;
1244 polling-delay = <0>;
1245 thermal-sensors = <&thermal 6>;
1246 sustainable-power = <5000>;
1248 cooling-maps {};
1253 compatible = "mediatek,mt8183-disp-pwm";
1256 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1257 #pwm-cells = <2>;
1260 clock-names = "main", "mm";
1264 compatible = "mediatek,mt8183-pwm";
1266 #pwm-cells = <2>;
1273 clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
1278 compatible = "mediatek,mt8183-i2c";
1284 clock-names = "main", "dma";
1285 clock-div = <1>;
1286 #address-cells = <1>;
1287 #size-cells = <0>;
1292 compatible = "mediatek,mt8183-spi";
1293 #address-cells = <1>;
1294 #size-cells = <0>;
1300 clock-names = "parent-clk", "sel-clk", "spi-clk";
1305 compatible = "mediatek,mt8183-i2c";
1311 clock-names = "main", "dma";
1312 clock-div = <1>;
1313 #address-cells = <1>;
1314 #size-cells = <0>;
1319 compatible = "mediatek,mt8183-spi";
1320 #address-cells = <1>;
1321 #size-cells = <0>;
1327 clock-names = "parent-clk", "sel-clk", "spi-clk";
1332 compatible = "mediatek,mt8183-spi";
1333 #address-cells = <1>;
1334 #size-cells = <0>;
1340 clock-names = "parent-clk", "sel-clk", "spi-clk";
1345 compatible = "mediatek,mt8183-i2c";
1352 clock-names = "main", "dma", "arb";
1353 clock-div = <1>;
1354 #address-cells = <1>;
1355 #size-cells = <0>;
1360 compatible = "mediatek,mt8183-i2c";
1367 clock-names = "main", "dma", "arb";
1368 clock-div = <1>;
1369 #address-cells = <1>;
1370 #size-cells = <0>;
1375 compatible = "mediatek,mt8183-i2c";
1382 clock-names = "main", "dma", "arb";
1383 clock-div = <1>;
1384 #address-cells = <1>;
1385 #size-cells = <0>;
1390 compatible = "mediatek,mt8183-i2c";
1397 clock-names = "main", "dma", "arb";
1398 clock-div = <1>;
1399 #address-cells = <1>;
1400 #size-cells = <0>;
1405 compatible = "mediatek,mt8183-spi";
1406 #address-cells = <1>;
1407 #size-cells = <0>;
1413 clock-names = "parent-clk", "sel-clk", "spi-clk";
1418 compatible = "mediatek,mt8183-spi";
1419 #address-cells = <1>;
1420 #size-cells = <0>;
1426 clock-names = "parent-clk", "sel-clk", "spi-clk";
1431 compatible = "mediatek,mt8183-i2c";
1437 clock-names = "main", "dma";
1438 clock-div = <1>;
1439 #address-cells = <1>;
1440 #size-cells = <0>;
1445 compatible = "mediatek,mt8183-i2c";
1451 clock-names = "main", "dma";
1452 clock-div = <1>;
1453 #address-cells = <1>;
1454 #size-cells = <0>;
1459 compatible = "mediatek,mt8183-mtu3", "mediatek,mtu3";
1462 reg-names = "mac", "ippc";
1468 clock-names = "sys_ck", "ref_ck";
1469 mediatek,syscon-wakeup = <&pericfg 0x420 101>;
1470 #address-cells = <2>;
1471 #size-cells = <2>;
1476 compatible = "mediatek,mt8183-xhci",
1477 "mediatek,mtk-xhci";
1479 reg-names = "mac";
1483 clock-names = "sys_ck", "ref_ck";
1488 audiosys: audio-controller@11220000 {
1489 compatible = "mediatek,mt8183-audiosys", "syscon";
1491 #clock-cells = <1>;
1492 afe: mt8183-afe-pcm {
1493 compatible = "mediatek,mt8183-audio";
1496 reset-names = "audiosys";
1497 power-domains =
1541 clock-names = "aud_afe_clk",
1587 compatible = "mediatek,mt8183-mmc";
1594 clock-names = "source", "hclk", "source_cg";
1599 compatible = "mediatek,mt8183-mmc";
1606 clock-names = "source", "hclk", "source_cg";
1610 mipi_tx0: dsi-phy@11e50000 {
1611 compatible = "mediatek,mt8183-mipi-tx";
1614 #clock-cells = <0>;
1615 #phy-cells = <0>;
1616 clock-output-names = "mipi_tx0_pll";
1617 nvmem-cells = <&mipi_tx_calibration>;
1618 nvmem-cell-names = "calibration-data";
1622 compatible = "mediatek,mt8183-efuse",
1623 "mediatek,efuse";
1625 #address-cells = <1>;
1626 #size-cells = <1>;
1640 u3phy: t-phy@11f40000 {
1641 compatible = "mediatek,mt8183-tphy",
1642 "mediatek,generic-tphy-v2";
1643 #address-cells = <1>;
1644 #size-cells = <1>;
1648 u2port0: usb-phy@0 {
1651 clock-names = "ref";
1652 #phy-cells = <1>;
1653 mediatek,discth = <15>;
1657 u3port0: usb-phy@700 {
1660 clock-names = "ref";
1661 #phy-cells = <1>;
1667 compatible = "mediatek,mt8183-mfgcfg", "syscon";
1669 #clock-cells = <1>;
1673 compatible = "mediatek,mt8183-mali", "arm,mali-bifrost";
1679 interrupt-names = "job", "mmu", "gpu";
1683 power-domains =
1687 power-domain-names = "core0", "core1", "core2";
1689 operating-points-v2 = <&gpu_opp_table>;
1693 compatible = "mediatek,mt8183-mmsys", "syscon";
1695 #clock-cells = <1>;
1696 #reset-cells = <1>;
1699 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1702 mdp3-rdma0@14001000 {
1703 compatible = "mediatek,mt8183-mdp3-rdma";
1705 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
1706 mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
1708 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1716 mdp3-rsz0@14003000 {
1717 compatible = "mediatek,mt8183-mdp3-rsz";
1719 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
1720 mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ0_SOF>,
1725 mdp3-rsz1@14004000 {
1726 compatible = "mediatek,mt8183-mdp3-rsz";
1728 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;
1729 mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ1_SOF>,
1734 mdp3-wrot0@14005000 {
1735 compatible = "mediatek,mt8183-mdp3-wrot";
1737 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
1738 mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>,
1740 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1745 mdp3-wdma@14006000 {
1746 compatible = "mediatek,mt8183-mdp3-wdma";
1748 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
1749 mediatek,gce-events = <CMDQ_EVENT_MDP_WDMA0_SOF>,
1751 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1757 compatible = "mediatek,mt8183-disp-ovl";
1760 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1763 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
1767 compatible = "mediatek,mt8183-disp-ovl-2l";
1770 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1773 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
1777 compatible = "mediatek,mt8183-disp-ovl-2l";
1780 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1783 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
1787 compatible = "mediatek,mt8183-disp-rdma";
1790 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1793 mediatek,rdma-fifo-size = <5120>;
1794 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
1798 compatible = "mediatek,mt8183-disp-rdma";
1801 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1804 mediatek,rdma-fifo-size = <2048>;
1805 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1809 compatible = "mediatek,mt8183-disp-color",
1810 "mediatek,mt8173-disp-color";
1813 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1815 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1819 compatible = "mediatek,mt8183-disp-ccorr";
1822 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1824 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
1828 compatible = "mediatek,mt8183-disp-aal";
1831 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1833 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
1837 compatible = "mediatek,mt8183-disp-gamma";
1840 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1842 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
1846 compatible = "mediatek,mt8183-disp-dither";
1849 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1851 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
1855 compatible = "mediatek,mt8183-dsi";
1858 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1862 clock-names = "engine", "digital", "hs";
1865 phy-names = "dphy";
1869 compatible = "mediatek,mt8183-disp-mutex";
1872 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1873 mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
1875 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
1879 compatible = "mediatek,mt8183-smi-larb";
1881 mediatek,smi = <&smi_common>;
1884 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1885 clock-names = "apb", "smi";
1889 compatible = "mediatek,mt8183-smi-common";
1895 clock-names = "apb", "smi", "gals0", "gals1";
1896 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1899 mdp3-ccorr@1401c000 {
1900 compatible = "mediatek,mt8183-mdp3-ccorr";
1902 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;
1903 mediatek,gce-events = <CMDQ_EVENT_MDP_CCORR_SOF>,
1909 compatible = "mediatek,mt8183-imgsys", "syscon";
1911 #clock-cells = <1>;
1915 compatible = "mediatek,mt8183-smi-larb";
1917 mediatek,smi = <&smi_common>;
1920 clock-names = "apb", "smi", "gals";
1921 power-domains = <&spm MT8183_POWER_DOMAIN_ISP>;
1925 compatible = "mediatek,mt8183-smi-larb";
1927 mediatek,smi = <&smi_common>;
1930 clock-names = "apb", "smi", "gals";
1931 power-domains = <&spm MT8183_POWER_DOMAIN_ISP>;
1935 compatible = "mediatek,mt8183-vdecsys", "syscon";
1937 #clock-cells = <1>;
1941 compatible = "mediatek,mt8183-smi-larb";
1943 mediatek,smi = <&smi_common>;
1945 clock-names = "apb", "smi";
1946 power-domains = <&spm MT8183_POWER_DOMAIN_VDEC>;
1950 compatible = "mediatek,mt8183-vencsys", "syscon";
1952 #clock-cells = <1>;
1956 compatible = "mediatek,mt8183-smi-larb";
1958 mediatek,smi = <&smi_common>;
1961 clock-names = "apb", "smi";
1962 power-domains = <&spm MT8183_POWER_DOMAIN_VENC>;
1966 compatible = "mediatek,mt8183-jpgenc", "mediatek,mtk-jpgenc";
1971 power-domains = <&spm MT8183_POWER_DOMAIN_VENC>;
1973 clock-names = "jpgenc";
1977 compatible = "mediatek,mt8183-ipu_conn", "syscon";
1979 #clock-cells = <1>;
1983 compatible = "mediatek,mt8183-ipu_adl", "syscon";
1985 #clock-cells = <1>;
1989 compatible = "mediatek,mt8183-ipu_core0", "syscon";
1991 #clock-cells = <1>;
1995 compatible = "mediatek,mt8183-ipu_core1", "syscon";
1997 #clock-cells = <1>;
2001 compatible = "mediatek,mt8183-camsys", "syscon";
2003 #clock-cells = <1>;
2007 compatible = "mediatek,mt8183-smi-larb";
2009 mediatek,smi = <&smi_common>;
2012 clock-names = "apb", "smi", "gals";
2013 power-domains = <&spm MT8183_POWER_DOMAIN_CAM>;
2017 compatible = "mediatek,mt8183-smi-larb";
2019 mediatek,smi = <&smi_common>;
2022 clock-names = "apb", "smi", "gals";
2023 power-domains = <&spm MT8183_POWER_DOMAIN_CAM>;