Lines Matching full:infracfg
659 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
667 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
675 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
683 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
691 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
699 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
707 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
715 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
726 infracfg: syscon@10001000 { label
727 compatible = "mediatek,mt8183-infracfg", "syscon";
778 <&infracfg CLK_INFRA_AUDIO>,
779 <&infracfg CLK_INFRA_AUDIO_26M_BCLK>;
786 mediatek,infracfg = <&infracfg>;
816 mediatek,infracfg = <&infracfg>;
838 mediatek,infracfg = <&infracfg>;
857 mediatek,infracfg = <&infracfg>;
868 mediatek,infracfg = <&infracfg>;
897 mediatek,infracfg = <&infracfg>;
907 mediatek,infracfg = <&infracfg>;
915 mediatek,infracfg = <&infracfg>;
941 <&infracfg CLK_INFRA_PMIC_AP>;
960 clocks = <&infracfg CLK_INFRA_SCPSYS>;
989 clocks = <&infracfg CLK_INFRA_GCE>;
997 clocks = <&infracfg CLK_INFRA_AUXADC>;
1008 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
1018 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
1028 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>;
1038 clocks = <&infracfg CLK_INFRA_I2C6>,
1039 <&infracfg CLK_INFRA_AP_DMA>;
1052 clocks = <&infracfg CLK_INFRA_I2C0>,
1053 <&infracfg CLK_INFRA_AP_DMA>;
1066 clocks = <&infracfg CLK_INFRA_I2C1>,
1067 <&infracfg CLK_INFRA_AP_DMA>,
1068 <&infracfg CLK_INFRA_I2C1_ARBITER>;
1081 clocks = <&infracfg CLK_INFRA_I2C2>,
1082 <&infracfg CLK_INFRA_AP_DMA>,
1083 <&infracfg CLK_INFRA_I2C2_ARBITER>;
1099 <&infracfg CLK_INFRA_SPI0>;
1108 clocks = <&infracfg CLK_INFRA_THERM>;
1120 clocks = <&infracfg CLK_INFRA_THERM>,
1121 <&infracfg CLK_INFRA_AUXADC>;
1123 resets = <&infracfg MT8183_INFRACFG_AO_THERM_SW_RST>;
1259 <&infracfg CLK_INFRA_DISP_PWM>;
1267 clocks = <&infracfg CLK_INFRA_PWM>,
1268 <&infracfg CLK_INFRA_PWM_HCLK>,
1269 <&infracfg CLK_INFRA_PWM1>,
1270 <&infracfg CLK_INFRA_PWM2>,
1271 <&infracfg CLK_INFRA_PWM3>,
1272 <&infracfg CLK_INFRA_PWM4>;
1282 clocks = <&infracfg CLK_INFRA_I2C3>,
1283 <&infracfg CLK_INFRA_AP_DMA>;
1299 <&infracfg CLK_INFRA_SPI1>;
1309 clocks = <&infracfg CLK_INFRA_I2C4>,
1310 <&infracfg CLK_INFRA_AP_DMA>;
1326 <&infracfg CLK_INFRA_SPI2>;
1339 <&infracfg CLK_INFRA_SPI3>;
1349 clocks = <&infracfg CLK_INFRA_I2C1_IMM>,
1350 <&infracfg CLK_INFRA_AP_DMA>,
1351 <&infracfg CLK_INFRA_I2C1_ARBITER>;
1364 clocks = <&infracfg CLK_INFRA_I2C2_IMM>,
1365 <&infracfg CLK_INFRA_AP_DMA>,
1366 <&infracfg CLK_INFRA_I2C2_ARBITER>;
1379 clocks = <&infracfg CLK_INFRA_I2C5>,
1380 <&infracfg CLK_INFRA_AP_DMA>,
1381 <&infracfg CLK_INFRA_I2C5_ARBITER>;
1394 clocks = <&infracfg CLK_INFRA_I2C5_IMM>,
1395 <&infracfg CLK_INFRA_AP_DMA>,
1396 <&infracfg CLK_INFRA_I2C5_ARBITER>;
1412 <&infracfg CLK_INFRA_SPI4>;
1425 <&infracfg CLK_INFRA_SPI5>;
1435 clocks = <&infracfg CLK_INFRA_I2C7>,
1436 <&infracfg CLK_INFRA_AP_DMA>;
1449 clocks = <&infracfg CLK_INFRA_I2C8>,
1450 <&infracfg CLK_INFRA_AP_DMA>;
1466 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
1467 <&infracfg CLK_INFRA_USB>;
1481 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
1482 <&infracfg CLK_INFRA_USB>;
1514 <&infracfg CLK_INFRA_AUDIO>,
1515 <&infracfg CLK_INFRA_AUDIO_26M_BCLK>,
1592 <&infracfg CLK_INFRA_MSDC0>,
1593 <&infracfg CLK_INFRA_MSDC0_SCK>;
1604 <&infracfg CLK_INFRA_MSDC1>,
1605 <&infracfg CLK_INFRA_MSDC1_SCK>;